Wolfgang Denk
16 years ago
commit
09cc0487b8
@ -0,0 +1,122 @@ |
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/*
|
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* (C) Copyright 2009 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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|
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#include <common.h> |
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#include <asm/ppc4xx_config.h> |
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|
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struct ppc4xx_config ppc4xx_config_val[] = { |
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{ |
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"333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66", |
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{ |
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0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55", |
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{ |
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0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55", |
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{ |
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0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30, |
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", |
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{ |
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0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53", |
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{ |
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0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55", |
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{ |
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0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55", |
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{ |
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0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10, |
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55", |
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{ |
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0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55", |
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{ |
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0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30, |
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66", |
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{ |
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0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66", |
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{ |
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0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55", |
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{ |
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0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55", |
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{ |
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0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30, |
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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}; |
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int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); |
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@ -1,231 +0,0 @@ |
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/*
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <i2c.h> |
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#include <asm/io.h> |
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/*
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* There are 2 versions of production Sequoia & Rainier platforms. |
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* The primary difference is the reference clock. Those with |
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* 33333333 reference clocks will also have 667MHz rated |
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* processors. Not enough differences to have unique clock |
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* settings. |
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* |
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* NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The |
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* values are independent of the rest of the clock settings. |
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* |
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* All Sequoias & Rainiers select from two possible EEPROMs in Boot |
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* Config F. One for 33MHz PCI, one for 66MHz PCI. The following |
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* values are for the 33MHz PCI configuration. Byte 5 (0 base) is |
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* the only value affected for a 33MHz PCI and simply needs a | 0x08. |
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*/ |
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#define NAND_COMPATIBLE 0x01 |
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#define NOR_COMPATIBLE 0x02 |
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/* check with Stefan on CONFIG_SYS_I2C_EEPROM_ADDR */ |
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#define I2C_EEPROM_ADDR 0x52 |
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static char *config_labels[] = { |
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"CPU: 333 PLB: 133 OPB: 66 EBC: 66", |
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"CPU: 333 PLB: 166 OPB: 83 EBC: 55", |
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"CPU: 400 PLB: 133 OPB: 66 EBC: 66", |
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"CPU: 400 PLB: 160 OPB: 80 EBC: 53", |
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"CPU: 416 PLB: 166 OPB: 83 EBC: 55", |
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"CPU: 500 PLB: 166 OPB: 83 EBC: 55", |
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"CPU: 533 PLB: 133 OPB: 66 EBC: 66", |
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"CPU: 667 PLB: 133 OPB: 66 EBC: 66", |
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"CPU: 667 PLB: 166 OPB: 83 EBC: 55", |
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NULL |
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}; |
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static u8 boot_configs[][17] = { |
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{ |
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(NOR_COMPATIBLE), |
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0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NAND_COMPATIBLE | NOR_COMPATIBLE), |
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0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NOR_COMPATIBLE), |
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0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NOR_COMPATIBLE), |
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0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NAND_COMPATIBLE | NOR_COMPATIBLE), |
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0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NAND_COMPATIBLE | NOR_COMPATIBLE), |
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0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NOR_COMPATIBLE), |
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0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NOR_COMPATIBLE), |
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0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NAND_COMPATIBLE | NOR_COMPATIBLE), |
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0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40, |
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0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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0, |
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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} |
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}; |
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/*
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* Bytes 6,8,9,11 change for NAND boot |
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*/ |
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static u8 nand_boot[] = { |
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0xd0, 0xa0, 0x68, 0x58 |
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}; |
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static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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u8 *buf, bNAND; |
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int x, y, nbytes, selcfg; |
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extern char console_buffer[]; |
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if (argc < 2) { |
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cmd_usage(cmdtp); |
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return 1; |
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} |
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if ((strcmp(argv[1], "nor") != 0) && |
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(strcmp(argv[1], "nand") != 0)) { |
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printf("Unsupported boot-device - only nor|nand support\n"); |
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return 1; |
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} |
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/* set the nand flag based on provided input */ |
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if ((strcmp(argv[1], "nand") == 0)) |
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bNAND = 1; |
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else |
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bNAND = 0; |
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printf("Available configurations: \n\n"); |
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if (bNAND) { |
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for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { |
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/* filter on nand compatible */ |
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if (boot_configs[x][0] & NAND_COMPATIBLE) { |
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printf(" %d - %s\n", (y+1), config_labels[x]); |
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y++; |
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} |
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} |
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} else { |
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for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { |
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/* filter on nor compatible */ |
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if (boot_configs[x][0] & NOR_COMPATIBLE) { |
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printf(" %d - %s\n", (y+1), config_labels[x]); |
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y++; |
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} |
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} |
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} |
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do { |
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nbytes = readline(" Selection [1-x / quit]: "); |
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if (nbytes) { |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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selcfg = simple_strtol(console_buffer, NULL, 10); |
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if ((selcfg < 1) || (selcfg > y)) |
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nbytes = 0; |
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} |
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} while (nbytes == 0); |
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y = (selcfg - 1); |
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for (x = 0; boot_configs[x][0] != 0; x++) { |
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if (bNAND) { |
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if (boot_configs[x][0] & NAND_COMPATIBLE) { |
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if (y > 0) |
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y--; |
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else if (y < 1) |
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break; |
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} |
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} else { |
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if (boot_configs[x][0] & NOR_COMPATIBLE) { |
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if (y > 0) |
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y--; |
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else if (y < 1) |
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break; |
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} |
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} |
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} |
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buf = &boot_configs[x][1]; |
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if (bNAND) { |
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buf[6] = nand_boot[0]; |
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buf[8] = nand_boot[1]; |
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buf[9] = nand_boot[2]; |
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buf[11] = nand_boot[3]; |
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} |
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/* check CPLD register +5 for PCI 66MHz flag */ |
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if ((in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN) == 0) |
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/*
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* PLB-to-PCI divisor = 3 for 33MHz sync PCI |
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* instead of 2 for 66MHz systems |
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*/ |
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buf[5] |= 0x08; |
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if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) |
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printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); |
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udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); |
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printf("Done\n"); |
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printf("Please power-cycle the board for the changes to take effect\n"); |
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return 0; |
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} |
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U_BOOT_CMD( |
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bootstrap, 2, 0, do_bootstrap, |
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"program the I2C bootstrap EEPROM", |
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"<nand|nor> - strap to boot from NAND or NOR flash" |
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); |
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