These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
9 years ago
committed by
Tom Rini
parent
b6073fd211
commit
0abdd9d01a
@ -1,17 +0,0 @@ |
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if ARCH_NOMADIK |
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|
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choice |
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prompt "Nomadik board select" |
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optional |
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config NOMADIK_NHK8815 |
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bool "ST 8815 Nomadik Hardware Kit" |
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endchoice |
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config SYS_SOC |
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default "nomadik" |
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source "board/st/nhk8815/Kconfig" |
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endif |
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = timer.o gpio.o
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obj-y += reset.o
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@ -1,83 +0,0 @@ |
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/*
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* (C) Copyright 2009 Alessandro Rubini |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/gpio.h> |
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|
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static unsigned long gpio_base[4] = { |
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NOMADIK_GPIO0_BASE, |
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NOMADIK_GPIO1_BASE, |
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NOMADIK_GPIO2_BASE, |
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NOMADIK_GPIO3_BASE |
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}; |
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|
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enum gpio_registers { |
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GPIO_DAT = 0x00, /* data register */ |
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GPIO_DATS = 0x04, /* data set */ |
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GPIO_DATC = 0x08, /* data clear */ |
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GPIO_PDIS = 0x0c, /* pull disable */ |
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GPIO_DIR = 0x10, /* direction */ |
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GPIO_DIRS = 0x14, /* direction set */ |
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GPIO_DIRC = 0x18, /* direction clear */ |
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GPIO_AFSLA = 0x20, /* alternate function select A */ |
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GPIO_AFSLB = 0x24, /* alternate function select B */ |
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}; |
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|
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static inline unsigned long gpio_to_base(int gpio) |
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{ |
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return gpio_base[gpio / 32]; |
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} |
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static inline u32 gpio_to_bit(int gpio) |
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{ |
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return 1 << (gpio & 0x1f); |
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} |
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void nmk_gpio_af(int gpio, int alternate_function) |
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{ |
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unsigned long base = gpio_to_base(gpio); |
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u32 bit = gpio_to_bit(gpio); |
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u32 afunc, bfunc; |
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|
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/* alternate function is 0..3, with one bit per register */ |
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afunc = readl(base + GPIO_AFSLA) & ~bit; |
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bfunc = readl(base + GPIO_AFSLB) & ~bit; |
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if (alternate_function & 1) afunc |= bit; |
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if (alternate_function & 2) bfunc |= bit; |
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writel(afunc, base + GPIO_AFSLA); |
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writel(bfunc, base + GPIO_AFSLB); |
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} |
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|
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void nmk_gpio_dir(int gpio, int dir) |
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{ |
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unsigned long base = gpio_to_base(gpio); |
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u32 bit = gpio_to_bit(gpio); |
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|
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if (dir) |
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writel(bit, base + GPIO_DIRS); |
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else |
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writel(bit, base + GPIO_DIRC); |
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} |
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|
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void nmk_gpio_set(int gpio, int val) |
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{ |
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unsigned long base = gpio_to_base(gpio); |
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u32 bit = gpio_to_bit(gpio); |
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if (val) |
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writel(bit, base + GPIO_DATS); |
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else |
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writel(bit, base + GPIO_DATC); |
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} |
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int nmk_gpio_get(int gpio) |
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{ |
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unsigned long base = gpio_to_base(gpio); |
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u32 bit = gpio_to_bit(gpio); |
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return readl(base + GPIO_DAT) & bit; |
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} |
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@ -1,26 +0,0 @@ |
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/*
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* (C) Copyright 2009 Alessandro Rubini |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __NMK_GPIO_H__ |
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#define __NMK_GPIO_H__ |
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/*
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* These functions are called from the soft-i2c driver, but |
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* are also used by board files to set output bits. |
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*/ |
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enum nmk_af { /* alternate function settings */ |
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GPIO_GPIO = 0, |
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GPIO_ALT_A, |
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GPIO_ALT_B, |
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GPIO_ALT_C |
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}; |
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extern void nmk_gpio_af(int gpio, int alternate_function); |
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extern void nmk_gpio_dir(int gpio, int dir); |
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extern void nmk_gpio_set(int gpio, int val); |
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extern int nmk_gpio_get(int gpio); |
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#endif /* __NMK_GPIO_H__ */ |
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@ -1,50 +0,0 @@ |
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/*
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* (C) Copyright 2009 Alessandro Rubini |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __ASM_ARCH_MTU_H |
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#define __ASM_ARCH_MTU_H |
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/*
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* The MTU device hosts four different counters, with 4 set of |
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* registers. These are register names. |
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*/ |
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#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ |
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#define MTU_RIS 0x04 /* Raw interrupt status */ |
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#define MTU_MIS 0x08 /* Masked interrupt status */ |
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#define MTU_ICR 0x0C /* Interrupt clear register */ |
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|
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/* per-timer registers take 0..3 as argument */ |
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#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ |
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#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ |
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#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ |
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#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ |
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|
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/* bits for the control register */ |
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#define MTU_CRn_ENA 0x80 |
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#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ |
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#define MTU_CRn_PRESCALE_MASK 0x0c |
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#define MTU_CRn_PRESCALE_1 0x00 |
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#define MTU_CRn_PRESCALE_16 0x04 |
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#define MTU_CRn_PRESCALE_256 0x08 |
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#define MTU_CRn_32BITS 0x02 |
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#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ |
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/* Other registers are usual amba/primecell registers, currently not used */ |
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#define MTU_ITCR 0xff0 |
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#define MTU_ITOP 0xff4 |
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#define MTU_PERIPH_ID0 0xfe0 |
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#define MTU_PERIPH_ID1 0xfe4 |
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#define MTU_PERIPH_ID2 0xfe8 |
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#define MTU_PERIPH_ID3 0xfeC |
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#define MTU_PCELL0 0xff0 |
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#define MTU_PCELL1 0xff4 |
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#define MTU_PCELL2 0xff8 |
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#define MTU_PCELL3 0xffC |
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#endif /* __ASM_ARCH_MTU_H */ |
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@ -1,14 +0,0 @@ |
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#include <config.h> |
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/* |
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* Processor reset for Nomadik |
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*/ |
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.align 5
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.globl reset_cpu
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reset_cpu: |
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ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */ |
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ldr r1, =0x1 |
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str r1, [r0, #0x18] |
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_loop_forever: |
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b _loop_forever |
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@ -1,71 +0,0 @@ |
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/*
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* (C) Copyright 2009 Alessandro Rubini |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/mtu.h> |
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/*
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* The timer is a decrementer, we'll left it free running at 2.4MHz. |
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* We have 2.4 ticks per microsecond and an overflow in almost 30min |
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*/ |
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#define TIMER_CLOCK (24 * 100 * 1000) |
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#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */ |
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#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */ |
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#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) |
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#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) |
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/* macro to read the decrementing 32 bit timer as an increasing count */ |
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#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) |
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/* Configure a free-running, auto-wrap counter with no prescaler */ |
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int timer_init(void) |
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{ |
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ulong val; |
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writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, |
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CONFIG_SYS_TIMERBASE + MTU_CR(0)); |
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/* Reset the timer */ |
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writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); |
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/*
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* The load-register isn't really immediate: it changes on clock |
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* edges, so we must wait for our newly-written value to appear. |
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* Since we might miss reading 0, wait for any change in value. |
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*/ |
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val = READ_TIMER(); |
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while (READ_TIMER() == val) |
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; |
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return 0; |
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} |
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/* Return how many HZ passed since "base" */ |
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ulong get_timer(ulong base) |
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{ |
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return TICKS_TO_HZ(READ_TIMER()) - base; |
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} |
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/* Delay x useconds */ |
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void __udelay(unsigned long usec) |
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{ |
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ulong ini, end; |
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ini = READ_TIMER(); |
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end = ini + USEC_TO_COUNT(usec); |
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while ((signed)(end - READ_TIMER()) > 0) |
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; |
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} |
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unsigned long long get_ticks(void) |
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{ |
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return get_timer(0); |
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} |
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ulong get_tbclk(void) |
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{ |
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return CONFIG_SYS_HZ; |
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} |
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@ -1,12 +0,0 @@ |
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if NOMADIK_NHK8815 |
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config SYS_BOARD |
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default "nhk8815" |
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config SYS_VENDOR |
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default "st" |
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config SYS_CONFIG_NAME |
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default "nhk8815" |
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endif |
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@ -1,8 +0,0 @@ |
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NHK8815 BOARD |
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M: Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com> |
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M: Alessandro Rubini <rubini@unipv.it> |
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S: Maintained |
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F: board/st/nhk8815/ |
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F: include/configs/nhk8815.h |
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F: configs/nhk8815_defconfig |
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F: configs/nhk8815_onenand_defconfig |
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@ -1,12 +0,0 @@ |
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2004
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# ARM Ltd.
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# Philippe Robin, <philippe.robin@arm.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := nhk8815.o
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@ -1,32 +0,0 @@ |
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The Nomadik 8815 CPU has a "secure" boot mode where no external access |
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(not even JTAG) is allowed. The "remap" bits in the evaluation board |
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are configured in order to boot from the internal ROM memory (in |
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secure mode). |
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|
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The boot process as defined by the manufacturer executes external code |
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(loaded from NAND or OneNAND) that that disables such "security" in |
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order to run u-boot and later the kernel without constraints. Such |
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code is a proprietary initial boot loader, called "X-Loader" (in case |
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anyone wonders, it has no relations with other loaders with the same |
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name and there is no GPL code inside the ST X-Loader). |
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SDRAM configuration, PLL setup and initial loading from NAND is |
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implemented in the X-Loader, so U-Boot is already running in SDRAM |
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when control is handed over to it. |
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The Makefile offers two different configurations to be used if you |
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boot from Nand or OneNand. |
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make nhk8815_config |
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make nhk8815_onenand_config |
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Both support OneNand and Nand. Since U-Boot, running in RAM, can't know |
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where it was loaded from, the configurations differ in where the filesystem |
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is looked for by default. |
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On www.st.com/nomadik and on www.stnwireless.com there are documents, |
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summary data and white papers on Nomadik. The full datasheet for |
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STn8815 is not currently available on line but under specific request |
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to the local ST sales offices. |
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@ -1,92 +0,0 @@ |
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/*
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* (C) Copyright 2005 |
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* STMicrolelctronics, <www.st.com> |
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* |
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* (C) Copyright 2004 |
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* ARM Ltd. |
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* Philippe Robin, <philippe.robin@arm.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/arch/gpio.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#ifdef CONFIG_SHOW_BOOT_PROGRESS |
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void show_boot_progress(int progress) |
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{ |
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printf("%i\n", progress); |
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} |
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#endif |
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/*
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* Miscellaneous platform dependent initialisations |
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*/ |
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int board_init(void) |
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{ |
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gd->bd->bi_arch_number = MACH_TYPE_NOMADIK; |
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gd->bd->bi_boot_params = 0x00000100; |
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writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20); |
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writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24); |
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writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28); |
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writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE); |
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/* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */ |
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writel(0x0000305b, REG_FSMC_BCR1); |
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writel(0x00033f33, REG_FSMC_BTR1); |
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/* Set up SMCS0 for OneNand: sram-like once again */ |
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writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */ |
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writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */ |
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icache_enable(); |
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return 0; |
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} |
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int board_late_init(void) |
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{ |
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/* Set the two I2C gpio lines to be gpio high */ |
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nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1); |
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nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1); |
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nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO); |
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/* Reset the I2C port expander, on GPIO77 */ |
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nmk_gpio_af(77, GPIO_GPIO); |
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nmk_gpio_dir(77, 1); |
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nmk_gpio_set(77, 0); |
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udelay(10); |
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nmk_gpio_set(77, 1); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, |
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CONFIG_SYS_SDRAM_SIZE); |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
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} |
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|
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#ifdef CONFIG_CMD_NET |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_SMC91111 |
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); |
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#endif |
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return rc; |
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} |
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#endif |
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@ -1,7 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_NOMADIK=y |
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CONFIG_NOMADIK_NHK8815=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_SYS_PROMPT="Nomadik> " |
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@ -1,7 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_NOMADIK=y |
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CONFIG_NOMADIK_NHK8815=y |
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CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND" |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_SETEXPR is not set |
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@ -1,206 +0,0 @@ |
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/*
|
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* (C) Copyright 2007 STMicroelectronics, <www.st.com> |
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* (C) Copyright 2009 Alessandro Rubini <rubini@unipv.it> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <nand.h> |
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#include <asm/io.h> |
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|
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static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */ |
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{ |
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__asm__ __volatile__( |
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"eor %0, %0, %0, lsr #4\n\t" |
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"eor %0, %0, %0, lsr #2\n\t" |
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"eor %0, %0, %0, lsr #1\n\t" |
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"ands %0, %0, #1\n\t" |
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"subne %0, %0, #2\t" |
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: "=r" (b) : "0" (b)); |
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return b; |
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} |
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|
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/*
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* This is the ECC routine used in hardware, according to the manual. |
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* HW claims to make the calculation but not the correction; so we must |
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* recalculate the bytes for a comparison. |
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*/ |
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static int ecc512(const unsigned char *data, unsigned char *ecc) |
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{ |
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int gpar = 0; |
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int i, val, par; |
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int pbits = 0; /* P8, P16, ... P2048 */ |
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int pprime = 0; /* P8', P16', ... P2048' */ |
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int lowbits; /* P1, P2, P4 and primes */ |
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|
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for (i = 0; i < 512; i++) { |
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par = parity((val = data[i])); |
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gpar ^= val; |
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pbits ^= (i & par); |
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} |
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/*
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* Ok, now gpar is global parity (xor of all bytes) |
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* pbits are all the parity bits (non-prime ones) |
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*/ |
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par = parity(gpar); |
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pprime = pbits ^ par; |
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/* Put low bits in the right position for ecc[2] (bits 7..2) */ |
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lowbits = 0 |
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| (parity(gpar & 0xf0) & 0x80) /* P4 */ |
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| (parity(gpar & 0x0f) & 0x40) /* P4' */ |
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| (parity(gpar & 0xcc) & 0x20) /* P2 */ |
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| (parity(gpar & 0x33) & 0x10) /* P2' */ |
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| (parity(gpar & 0xaa) & 0x08) /* P1 */ |
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| (parity(gpar & 0x55) & 0x04); /* P1' */ |
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|
||||
ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8)); |
||||
/* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */ |
||||
ecc[1] = ~( (pbits & 0x80) >> 0 | ((pprime & 0x80) >> 1) |
||||
| ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2) |
||||
| ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3) |
||||
| ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4)); |
||||
|
||||
ecc[0] = ~( (pbits & 0x8) << 4 | ((pprime & 0x8) << 3) |
||||
| ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2) |
||||
| ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1) |
||||
| ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0)); |
||||
return 0; |
||||
} |
||||
|
||||
/* This is the method in the chip->ecc field */ |
||||
static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, |
||||
uint8_t *ecc_code) |
||||
{ |
||||
return ecc512(dat, ecc_code); |
||||
} |
||||
|
||||
static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat, |
||||
uint8_t *r_ecc, uint8_t *c_ecc) |
||||
{ |
||||
struct nand_chip *chip = mtd->priv; |
||||
uint32_t r, c, d, diff; /*read, calculated, xor of them */ |
||||
|
||||
if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes)) |
||||
return 0; |
||||
|
||||
/* Reorder the bytes into ascending-order 24 bits -- see manual */ |
||||
r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2; |
||||
c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2; |
||||
diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */ |
||||
|
||||
/* If 12 bits are different, one per pair, it's correctable */ |
||||
if (((diff | (diff>>1)) & 0x555555) == 0x555555) { |
||||
int bit = ((diff & 2) >> 1) |
||||
| ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3); |
||||
int byte; |
||||
|
||||
d = diff >> 6; /* remove bit-order info */ |
||||
byte = ((d & 2) >> 1) |
||||
| ((d & 0x8) >> 2) | ((d & 0x20) >> 3) |
||||
| ((d & 0x80) >> 4) | ((d & 0x200) >> 5) |
||||
| ((d & 0x800) >> 6) | ((d & 0x2000) >> 7) |
||||
| ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9); |
||||
/* correct the single bit */ |
||||
dat[byte] ^= 1<<bit; |
||||
return 0; |
||||
} |
||||
/* If 1 bit only differs, it's one bit error in ECC, ignore */ |
||||
if ((diff ^ (1 << (ffs(diff) - 1))) == 0) |
||||
return 0; |
||||
/* Otherwise, uncorrectable */ |
||||
return -1; |
||||
} |
||||
|
||||
static void nomadik_ecc_hwctl(struct mtd_info *mtd, int mode) |
||||
{ /* mandatory in the structure but not used here */ } |
||||
|
||||
|
||||
/* This is the layout used by older installations, we keep compatible */ |
||||
struct nand_ecclayout nomadik_ecc_layout = { |
||||
.eccbytes = 3 * 4, |
||||
.eccpos = { /* each subpage has 16 bytes: pos 2,3,4 hosts ECC */ |
||||
0x02, 0x03, 0x04, |
||||
0x12, 0x13, 0x14, |
||||
0x22, 0x23, 0x24, |
||||
0x32, 0x33, 0x34}, |
||||
.oobfree = { {0x08, 0x08}, {0x18, 0x08}, {0x28, 0x08}, {0x38, 0x08} }, |
||||
}; |
||||
|
||||
#define MASK_ALE (1 << 24) /* our ALE is AD21 */ |
||||
#define MASK_CLE (1 << 23) /* our CLE is AD22 */ |
||||
|
||||
/* This is copied from the AT91SAM9 devices (Stelian Pop, Lead Tech Design) */ |
||||
static void nomadik_nand_hwcontrol(struct mtd_info *mtd, |
||||
int cmd, unsigned int ctrl) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
u32 pcr0 = readl(REG_FSMC_PCR0); |
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) { |
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
||||
IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); |
||||
|
||||
if (ctrl & NAND_CLE) |
||||
IO_ADDR_W |= MASK_CLE; |
||||
if (ctrl & NAND_ALE) |
||||
IO_ADDR_W |= MASK_ALE; |
||||
|
||||
if (ctrl & NAND_NCE) |
||||
writel(pcr0 | 0x4, REG_FSMC_PCR0); |
||||
else |
||||
writel(pcr0 & ~0x4, REG_FSMC_PCR0); |
||||
|
||||
this->IO_ADDR_W = (void *) IO_ADDR_W; |
||||
this->IO_ADDR_R = (void *) IO_ADDR_W; |
||||
} |
||||
|
||||
if (cmd != NAND_CMD_NONE) |
||||
writeb(cmd, this->IO_ADDR_W); |
||||
} |
||||
|
||||
/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */ |
||||
static int nomadik_nand_ready(struct mtd_info *mtd) |
||||
{ |
||||
return 1; /* The ready bit is handled in hardware */ |
||||
} |
||||
|
||||
/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */ |
||||
static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
||||
{ |
||||
int i; |
||||
struct nand_chip *chip = mtd->priv; |
||||
u32 *p = (u32 *) buf; |
||||
|
||||
len >>= 2; |
||||
writel(0, REG_FSMC_ECCR0); |
||||
for (i = 0; i < len; i++) |
||||
p[i] = readl(chip->IO_ADDR_R); |
||||
} |
||||
|
||||
int board_nand_init(struct nand_chip *chip) |
||||
{ |
||||
/* Set up the FSMC_PCR0 for nand access*/ |
||||
writel(0x0000004a, REG_FSMC_PCR0); |
||||
/* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */ |
||||
writel(0x00020401, REG_FSMC_PMEM0); |
||||
writel(0x00020404, REG_FSMC_PATT0); |
||||
|
||||
chip->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; |
||||
chip->cmd_ctrl = nomadik_nand_hwcontrol; |
||||
chip->dev_ready = nomadik_nand_ready; |
||||
/* The chip allows 32bit reads, so avoid the default 8bit copy */ |
||||
chip->read_buf = nomadik_nand_read_buf; |
||||
|
||||
/* ECC: follow the hardware-defined rulse, but do it in sw */ |
||||
chip->ecc.mode = NAND_ECC_HW; |
||||
chip->ecc.bytes = 3; |
||||
chip->ecc.size = 512; |
||||
chip->ecc.strength = 1; |
||||
chip->ecc.layout = &nomadik_ecc_layout; |
||||
chip->ecc.calculate = nomadik_ecc_calculate; |
||||
chip->ecc.hwctl = nomadik_ecc_hwctl; |
||||
chip->ecc.correct = nomadik_ecc_correct; |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,170 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* STMicroelectronics. |
||||
* Configuration settings for the "Nomadik Hardware Kit" NHK-8815, |
||||
* the evaluation board for the Nomadik 8815 System on Chip. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <nomadik.h> |
||||
|
||||
#define CONFIG_NOMADIK_8815 /* cpu variant */ |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ |
||||
|
||||
/* commands */ |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_SYS_NO_FLASH |
||||
/* There is NAND storage */ |
||||
#define CONFIG_NAND_NOMADIK |
||||
#define CONFIG_CMD_JFFS2 |
||||
|
||||
/* user interface */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
||||
+ sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE |
||||
|
||||
/* boot config */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_BOOTDELAY 1 |
||||
#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc" |
||||
#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \ |
||||
" fsload 0x800000 initrd.gz.uimg;" \
|
||||
" bootm 0x100000 0x800000" |
||||
|
||||
/* memory-related information */ |
||||
#define CONFIG_NR_DRAM_BANKS 2 |
||||
#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
||||
#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/ |
||||
#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) |
||||
/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */ |
||||
#define CONFIG_SYS_TEXT_BASE 0x00000000 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20)) |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024) |
||||
|
||||
#define CONFIG_BOARD_LATE_INIT /* call board_late_init during start up */ |
||||
|
||||
/* timing informazion */ |
||||
#define CONFIG_SYS_TIMERBASE 0x101E2000 |
||||
|
||||
/* serial port (PL011) configuration */ |
||||
#define CONFIG_PL011_SERIAL |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_SERIAL0 0x101FD000 |
||||
#define CFG_SERIAL1 0x101FB000 |
||||
|
||||
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } |
||||
#define CONFIG_PL011_CLOCK 48000000 |
||||
|
||||
/* i2c, for the port extenders (uses gpio.c in board directory) */ |
||||
#ifndef __ASSEMBLY__ |
||||
#include <asm/arch/gpio.h> |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SOFT 1 /* I2C bit-banged */ |
||||
#define I2C_SOFT_DEFS |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 400000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F |
||||
#define __SDA 63 |
||||
#define __SCL 62 |
||||
#define I2C_SDA(x) nmk_gpio_set(__SDA, x) |
||||
#define I2C_SCL(x) nmk_gpio_set(__SCL, x) |
||||
#define I2C_READ (nmk_gpio_get(__SDA)!=0) |
||||
#define I2C_ACTIVE nmk_gpio_dir(__SDA, 1) |
||||
#define I2C_TRISTATE nmk_gpio_dir(__SDA, 0) |
||||
#define I2C_DELAY (udelay(2)) |
||||
#endif /* __ASSEMBLY__ */ |
||||
|
||||
/* Ethernet */ |
||||
#define PCI_MEMORY_VADDR 0xe8000000 |
||||
#define PCI_IO_VADDR 0xee000000 |
||||
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) |
||||
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR) |
||||
|
||||
#define CONFIG_SMC91111 /* Using SMC91c111*/ |
||||
#define CONFIG_SMC91111_BASE 0x34000300 |
||||
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ |
||||
#define CONFIG_SMC_USE_32_BIT |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
|
||||
#define CONFIG_IP_DEFRAG /* Allows faster download, TFTP and NFS */ |
||||
#define CONFIG_TFTP_BLOCKSIZE 4096 |
||||
#define CONFIG_NFS_READ_SIZE 4096 |
||||
|
||||
/* Storage information: onenand and nand */ |
||||
#define CONFIG_CMD_ONENAND |
||||
#define CONFIG_MTD_ONENAND_VERIFY_WRITE |
||||
#define CONFIG_SYS_ONENAND_BASE 0x30000000 |
||||
|
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */ |
||||
|
||||
/*
|
||||
* Filesystem information |
||||
* |
||||
* Since U-Boot has been loaded to RAM by vendor code, we could use |
||||
* either or both OneNand and Nand. However, we need to know where the |
||||
* filesystem lives. Comments below report vendor-selected partitions |
||||
*/ |
||||
#ifdef CONFIG_BOOT_ONENAND |
||||
/* Partition Size Start
|
||||
* XloaderTOC + X-Loader 256KB 0x00000000 |
||||
* Memory init function 256KB 0x00040000 |
||||
* U-Boot + env 2MB 0x00080000 |
||||
* Sysimage (kernel + ramdisk) 4MB 0x00280000 |
||||
* JFFS2 Root filesystem 22MB 0x00680000 |
||||
* JFFS2 User Data 227.5MB 0x01C80000 |
||||
*/ |
||||
# define CONFIG_JFFS2_DEV "onenand0" |
||||
# define CONFIG_JFFS2_PART_SIZE 0x01600000 |
||||
# define CONFIG_JFFS2_PART_OFFSET 0x00680000 |
||||
# define CONFIG_ENV_IS_IN_ONENAND |
||||
# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ |
||||
# define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE) |
||||
|
||||
#else /* BOOT_NAND */ |
||||
/* Partition Size Start
|
||||
* XloaderTOC + X-Loader 256KB 0x00000000 |
||||
* Memory init function 256KB 0x00040000 |
||||
* U-Boot + env 2MB 0x00080000 |
||||
* Kernel Image 3MB 0x00280000 |
||||
* JFFS2 Root filesystem 22MB 0x00580000 |
||||
* JFFS2 User Data 100.5MB 0x01b80000 |
||||
*/ |
||||
# define CONFIG_JFFS2_DEV "nand0" |
||||
# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/ |
||||
# define CONFIG_JFFS2_PART_SIZE 0x01600000 |
||||
# define CONFIG_JFFS2_PART_OFFSET 0x00580000 |
||||
# define CONFIG_ENV_IS_IN_NAND |
||||
# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ |
||||
# define CONFIG_ENV_OFFSET (0x00280000 - CONFIG_ENV_SIZE) |
||||
|
||||
#endif /* CONFIG_BOOT_ONENAND */ |
||||
|
||||
/* this is needed to make hello_world.c and other stuff happy */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,40 +0,0 @@ |
||||
/* Collection of constants used to access Nomadik registers */ |
||||
|
||||
#ifndef __NOMADIK_H__ |
||||
#define __NOMADIK_H__ |
||||
|
||||
/* Base addresses of our peripherals */ |
||||
#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */ |
||||
#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */ |
||||
#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */ |
||||
#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */ |
||||
#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */ |
||||
#define NOMADIK_1NAND_BASE 0x30000000 |
||||
#define NOMADIK_GPIO0_BASE 0x101E4000 |
||||
#define NOMADIK_GPIO1_BASE 0x101E5000 |
||||
#define NOMADIK_GPIO2_BASE 0x101E6000 |
||||
#define NOMADIK_GPIO3_BASE 0x101E7000 |
||||
#define NOMADIK_CPLD_BASE 0x36000000 |
||||
#define NOMADIK_UART0_BASE 0x101FD000 |
||||
#define NOMADIK_UART1_BASE 0x101FB000 |
||||
#define NOMADIK_UART2_BASE 0x101F2000 |
||||
|
||||
#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */ |
||||
#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */ |
||||
|
||||
#define NOMADIK_RTC_BASE 0x101E8000 |
||||
#define NOMADIK_ETH0_BASE 0x36800300 |
||||
#define NOMADIK_CPLD_UART_BASE 0x36480000 |
||||
|
||||
/* Chip select registers ("Flexible Static Memory Controller") */ |
||||
|
||||
#define REG_FSMC_BCR0 (NOMADIK_FSMC_BASE + 0x00) |
||||
#define REG_FSMC_BTR0 (NOMADIK_FSMC_BASE + 0x04) |
||||
#define REG_FSMC_BCR1 (NOMADIK_FSMC_BASE + 0x08) |
||||
#define REG_FSMC_BTR1 (NOMADIK_FSMC_BASE + 0x0c) |
||||
#define REG_FSMC_PCR0 (NOMADIK_FSMC_BASE + 0x40) |
||||
#define REG_FSMC_PMEM0 (NOMADIK_FSMC_BASE + 0x48) |
||||
#define REG_FSMC_PATT0 (NOMADIK_FSMC_BASE + 0x4c) |
||||
#define REG_FSMC_ECCR0 (NOMADIK_FSMC_BASE + 0x54) |
||||
|
||||
#endif /* __NOMADIK_H__ */ |
||||
Loading…
Reference in new issue