T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]master
Chunhe Lan
11 years ago
committed by
York Sun
parent
652e29b4a0
commit
0b2e13d9cc
@ -0,0 +1,12 @@ |
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#
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# Copyright 2014 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_T4240RDB) += t4240rdb.o
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obj-y += ddr.o
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obj-y += eth.o
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obj-$(CONFIG_PCI) += pci.o
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obj-y += law.o
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obj-y += tlb.o
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@ -0,0 +1,118 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <hwconfig.h> |
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#include <asm/mmu.h> |
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#include <fsl_ddr_sdram.h> |
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#include <fsl_ddr_dimm_params.h> |
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#include <asm/fsl_law.h> |
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#include "ddr.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
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ulong ddr_freq; |
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if (ctrl_num > 2) { |
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printf("Not supported controller number %d\n", ctrl_num); |
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return; |
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} |
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if (!pdimm->n_ranks) |
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return; |
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/*
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* we use identical timing for all slots. If needed, change the code |
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* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; |
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*/ |
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if (popts->registered_dimm_en) |
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pbsp = rdimms[0]; |
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else |
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pbsp = udimms[0]; |
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table. |
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*/ |
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ddr_freq = get_ddr_freq(0) / 1000000; |
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while (pbsp->datarate_mhz_high) { |
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if (pbsp->n_ranks == pdimm->n_ranks && |
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(pdimm->rank_density >> 30) >= pbsp->rank_gb) { |
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if (ddr_freq <= pbsp->datarate_mhz_high) { |
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popts->clk_adjust = pbsp->clk_adjust; |
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popts->wrlvl_start = pbsp->wrlvl_start; |
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
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goto found; |
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} |
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pbsp_highest = pbsp; |
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} |
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pbsp++; |
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} |
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if (pbsp_highest) { |
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printf("Error: board specific timing not found for data\n" |
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"rate %lu MT/s\n" |
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"Trying to use the highest speed (%u) parameters\n", |
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ddr_freq, pbsp_highest->datarate_mhz_high); |
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popts->clk_adjust = pbsp_highest->clk_adjust; |
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popts->wrlvl_start = pbsp_highest->wrlvl_start; |
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
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} else { |
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panic("DIMM is not supported by this board"); |
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} |
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found: |
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" |
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"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" |
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"wrlvl_ctrl_3 0x%x\n", |
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, |
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pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, |
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pbsp->wrlvl_ctl_3); |
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/*
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* Factors to consider for half-strength driver enable: |
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* - number of DIMMs installed |
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*/ |
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popts->half_strength_driver_enable = 0; |
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/*
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* Write leveling override |
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*/ |
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popts->wrlvl_override = 1; |
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popts->wrlvl_sample = 0xf; |
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/*
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* Rtt and Rtt_WR override |
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*/ |
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popts->rtt_override = 0; |
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/* Enable ZQ calibration */ |
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popts->zq_en = 1; |
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/* DHC_EN =1, ODT = 75 Ohm */ |
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); |
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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phys_size_t dram_size; |
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puts("Initializing....using SPD\n"); |
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dram_size = fsl_ddr_sdram(); |
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dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
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dram_size *= 0x100000; |
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puts(" DDR: "); |
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return dram_size; |
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} |
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@ -0,0 +1,78 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __DDR_H__ |
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#define __DDR_H__ |
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struct board_specific_parameters { |
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u32 n_ranks; |
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u32 datarate_mhz_high; |
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u32 rank_gb; |
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u32 clk_adjust; |
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u32 wrlvl_start; |
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u32 wrlvl_ctl_2; |
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u32 wrlvl_ctl_3; |
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}; |
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/*
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* These tables contain all valid speeds we want to override with board |
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* specific parameters. datarate_mhz_high values need to be in ascending order |
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* for each n_ranks group. |
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*/ |
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static const struct board_specific_parameters udimm0[] = { |
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/*
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* memory controller 0 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/ |
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{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a}, |
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{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09}, |
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{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b}, |
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{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a}, |
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{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, |
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{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, |
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{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a}, |
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{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a}, |
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{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a}, |
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{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b}, |
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{} |
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}; |
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static const struct board_specific_parameters rdimm0[] = { |
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/*
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* memory controller 0 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/ |
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{4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
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{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, |
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{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, |
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{2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
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{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, |
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{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, |
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{1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
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{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, |
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{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, |
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{} |
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}; |
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/*
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* The three slots have slightly different timing. The center values are good |
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* for all slots. We use identical speed tables for them. In future use, if |
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* DIMMs require separated tables, make more entries as needed. |
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*/ |
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static const struct board_specific_parameters *udimms[] = { |
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udimm0, |
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}; |
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/*
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* The three slots have slightly different timing. See comments above. |
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*/ |
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static const struct board_specific_parameters *rdimms[] = { |
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rdimm0, |
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}; |
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#endif |
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@ -0,0 +1,146 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* Chunhe Lan <Chunhe.Lan@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <netdev.h> |
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#include <asm/mmu.h> |
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#include <asm/processor.h> |
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#include <asm/cache.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/fsl_law.h> |
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#include <fsl_ddr_sdram.h> |
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#include <asm/fsl_serdes.h> |
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#include <asm/fsl_portals.h> |
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#include <asm/fsl_liodn.h> |
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#include <malloc.h> |
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#include <fm_eth.h> |
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#include <fsl_mdio.h> |
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#include <miiphy.h> |
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#include <phy.h> |
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#include <asm/fsl_dtsec.h> |
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#include <asm/fsl_serdes.h> |
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#include <hwconfig.h> |
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#include "../common/fman.h" |
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#include "t4rdb.h" |
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void fdt_fixup_board_enet(void *fdt) |
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{ |
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return; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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#if defined(CONFIG_FMAN_ENET) |
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int i, interface; |
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struct memac_mdio_info dtsec_mdio_info; |
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struct memac_mdio_info tgec_mdio_info; |
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struct mii_dev *dev; |
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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u32 srds_prtcl_s1, srds_prtcl_s2; |
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srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & |
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
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srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
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srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & |
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL; |
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srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; |
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dtsec_mdio_info.regs = |
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(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; |
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
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/* Register the 1G MDIO bus */ |
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fm_memac_mdio_init(bis, &dtsec_mdio_info); |
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tgec_mdio_info.regs = |
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(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; |
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; |
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/* Register the 10G MDIO bus */ |
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fm_memac_mdio_init(bis, &tgec_mdio_info); |
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if (srds_prtcl_s1 == 28) { |
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/* SGMII */ |
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); |
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); |
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fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); |
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fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); |
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} else { |
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puts("Invalid SerDes1 protocol for T4240RDB\n"); |
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} |
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
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interface = fm_info_get_enet_if(i); |
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switch (interface) { |
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case PHY_INTERFACE_MODE_SGMII: |
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); |
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fm_info_set_mdio(i, dev); |
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break; |
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default: |
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break; |
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} |
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} |
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for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { |
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switch (fm_info_get_enet_if(i)) { |
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case PHY_INTERFACE_MODE_XGMII: |
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dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); |
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fm_info_set_mdio(i, dev); |
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break; |
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default: |
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break; |
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} |
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} |
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#if (CONFIG_SYS_NUM_FMAN == 2) |
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if (srds_prtcl_s2 == 56) { |
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/* SGMII && XFI */ |
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fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); |
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fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); |
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fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); |
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fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); |
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fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); |
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fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); |
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fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); |
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fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); |
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} else { |
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puts("Invalid SerDes2 protocol for T4240RDB\n"); |
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} |
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for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { |
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interface = fm_info_get_enet_if(i); |
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switch (interface) { |
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case PHY_INTERFACE_MODE_SGMII: |
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); |
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fm_info_set_mdio(i, dev); |
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break; |
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default: |
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break; |
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} |
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} |
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for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { |
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switch (fm_info_get_enet_if(i)) { |
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case PHY_INTERFACE_MODE_XGMII: |
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dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); |
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fm_info_set_mdio(i, dev); |
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break; |
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default: |
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break; |
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} |
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} |
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#endif /* CONFIG_SYS_NUM_FMAN */ |
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cpu_eth_init(bis); |
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#endif /* CONFIG_FMAN_ENET */ |
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return pci_eth_init(bis); |
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} |
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@ -0,0 +1,28 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mmu.h> |
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struct law_entry law_table[] = { |
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), |
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#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
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SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), |
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#endif |
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#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
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SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), |
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#endif |
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#ifdef CONFIG_SYS_DCSRBAR_PHYS |
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/* Limit DCSR to 32M to access NPC Trace Buffer */ |
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SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), |
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#endif |
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#ifdef CONFIG_SYS_NAND_BASE_PHYS |
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), |
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#endif |
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}; |
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int num_law_entries = ARRAY_SIZE(law_table); |
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@ -0,0 +1,23 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <pci.h> |
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#include <asm/fsl_pci.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include <asm/fsl_serdes.h> |
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void pci_init_board(void) |
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{ |
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fsl_pcie_init_board(0); |
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} |
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void pci_of_setup(void *blob, bd_t *bd) |
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{ |
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FT_FSL_PCI_SETUP; |
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} |
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@ -0,0 +1,125 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <i2c.h> |
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#include <netdev.h> |
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#include <linux/compiler.h> |
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#include <asm/mmu.h> |
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#include <asm/processor.h> |
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#include <asm/cache.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/fsl_law.h> |
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#include <asm/fsl_serdes.h> |
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#include <asm/fsl_portals.h> |
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#include <asm/fsl_liodn.h> |
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#include <fm_eth.h> |
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#include "t4rdb.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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struct cpu_type *cpu = gd->arch.cpu; |
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printf("Board: %sRDB, ", cpu->name); |
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puts("SERDES Reference Clocks:\n"); |
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printf(" SERDES1=100MHz SERDES2=156.25MHz\n" |
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" SERDES3=100MHz SERDES4=100MHz\n"); |
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return 0; |
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} |
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int board_early_init_r(void) |
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{ |
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); |
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited |
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* so that flash can be erased properly. |
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*/ |
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/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||
flush_dcache(); |
||||
invalidate_icache(); |
||||
|
||||
/* invalidate existing TLB entry for flash + promjet */ |
||||
disable_tlb(flash_esel); |
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1); |
||||
|
||||
set_liodns(); |
||||
#ifdef CONFIG_SYS_DPAA_QBMAN |
||||
setup_portals(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
#ifdef CONFIG_PCI |
||||
pci_of_setup(blob, bd); |
||||
#endif |
||||
|
||||
fdt_fixup_liodn(blob); |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
fdt_fixup_fman_ethernet(blob); |
||||
fdt_fixup_board_enet(blob); |
||||
#endif |
||||
} |
||||
|
||||
/*
|
||||
* This function is called by bdinfo to print detail board information. |
||||
* As an exmaple for future board, we organize the messages into |
||||
* several sections. If applicable, the message is in the format of |
||||
* <name> = <value> |
||||
* It should aligned with normal output of bdinfo command. |
||||
* |
||||
* Voltage: Core, DDR and another configurable voltages |
||||
* Clock : Critical clocks which are not printed already |
||||
* RCW : RCW source if not printed already |
||||
* Misc : Other important information not in above catagories |
||||
*/ |
||||
void board_detail(void) |
||||
{ |
||||
int rcwsrc; |
||||
|
||||
/* RCW section SW3[4] */ |
||||
rcwsrc = 0x0; |
||||
puts("RCW source = "); |
||||
switch (rcwsrc & 0x1) { |
||||
case 0x1: |
||||
puts("SDHC/eMMC\n"); |
||||
break; |
||||
default: |
||||
puts("I2C normal addressing\n"); |
||||
break; |
||||
} |
||||
} |
||||
@ -0,0 +1,31 @@ |
||||
# |
||||
# Copyright 2014 Freescale Semiconductor, Inc. |
||||
# |
||||
# SPDX-License-Identifier: GPL-2.0+ |
||||
# |
||||
|
||||
#PBI commands |
||||
#Initialize CPC1 |
||||
09010000 00200400 |
||||
09138000 00000000 |
||||
091380c0 00000100 |
||||
#512KB SRAM |
||||
09010100 00000000 |
||||
09010104 fff80009 |
||||
09010f00 08000000 |
||||
#enable CPC1 |
||||
09010000 80000000 |
||||
#Configure LAW for CPC1 |
||||
09000d00 00000000 |
||||
09000d04 fff80000 |
||||
09000d08 81000012 |
||||
#slow mdio clock |
||||
095fc030 00008148 |
||||
095fd030 00808148 |
||||
#Configure alternate space |
||||
09000010 00000000 |
||||
09000014 ff000000 |
||||
09000018 81000000 |
||||
#Flush PBL data |
||||
09138000 00000000 |
||||
091380c0 00000000 |
||||
@ -0,0 +1,7 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 010e0100 |
||||
#serdes protocol 28_56_2_10 |
||||
16070019 18101916 00000000 00000000 |
||||
70701050 00448c00 6c020000 f5000000 |
||||
00000000 ee0000ee 00000000 000287fc |
||||
00000000 50000000 00000000 00000028 |
||||
@ -0,0 +1,18 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __T4RDB_H__ |
||||
#define __T4RDB_H__ |
||||
|
||||
#undef CONFIG_SYS_NUM_FM1_DTSEC |
||||
#undef CONFIG_SYS_NUM_FM2_DTSEC |
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 4 |
||||
#define CONFIG_SYS_NUM_FM2_DTSEC 4 |
||||
|
||||
void fdt_fixup_board_enet(void *blob); |
||||
void pci_of_setup(void *blob, bd_t *bd); |
||||
|
||||
#endif |
||||
@ -0,0 +1,111 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 */ |
||||
/* *I*** - Covers boot page */ |
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) |
||||
/*
|
||||
* *I*G - L3SRAM. When L3 is used as 512K SRAM */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_512K, 1), |
||||
#else |
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_4K, 1), |
||||
#endif |
||||
|
||||
/* *I*G* - CCSRBAR */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/* *I*G* - Flash, localbus */ |
||||
/* This will be changed to *I*G* after relocation to RAM. */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, |
||||
CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, |
||||
CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/* *I*G* - PCI I/O */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_256K, 1), |
||||
|
||||
/* Bman/Qman */ |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 9, BOOKE_PAGESZ_16M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, |
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 10, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 11, BOOKE_PAGESZ_16M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, |
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 12, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 13, BOOKE_PAGESZ_32M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE |
||||
/*
|
||||
* *I*G - NAND |
||||
* entry 14 and 15 has been used hard coded, they will be disabled |
||||
* in cpu_init_f, so we use entry 16 for nand. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 16, BOOKE_PAGESZ_64K, 1), |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -0,0 +1,752 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* T4240 RDB board configuration file |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_T4240RDB |
||||
#define CONFIG_PHYS_64BIT |
||||
|
||||
#define CONFIG_FSL_SATA_V2 |
||||
#define CONFIG_PCIE4 |
||||
|
||||
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL |
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
||||
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg |
||||
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg |
||||
#endif |
||||
|
||||
#define CONFIG_DDR_ECC |
||||
|
||||
#define CONFIG_CMD_REGINFO |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE |
||||
#define CONFIG_E500 /* BOOKE e500 family */ |
||||
#define CONFIG_E500MC /* BOOKE e500mc family */ |
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
||||
#define CONFIG_MP /* support multiple processors */ |
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_TEXT_BASE 0xeff40000 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS |
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS |
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */ |
||||
#define CONFIG_PCI /* Enable PCI/PCIE */ |
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */ |
||||
#define CONFIG_PCIE2 /* PCIE controler 2 */ |
||||
#define CONFIG_PCIE3 /* PCIE controler 3 */ |
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_SYS_CACHE_STASHING |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
#ifdef CONFIG_DDR_ECC |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
||||
#endif |
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS |
||||
|
||||
#define CONFIG_ADDR_MAP |
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000 |
||||
#define CONFIG_SYS_ALT_MEMTEST |
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */ |
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM |
||||
*/ |
||||
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE |
||||
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000 |
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_VERY_BIG_RAM |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ |
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
||||
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE |
||||
|
||||
#define CONFIG_DDR_SPD |
||||
#define CONFIG_SYS_FSL_DDR3 |
||||
|
||||
|
||||
/*
|
||||
* IFC Definitions |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000 |
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
||||
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_HWCONFIG |
||||
|
||||
/* define to use L1 as initial stack */ |
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CONFIG_SYS_INIT_RAM_LOCK |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 |
||||
/* The assembler doesn't like typecast */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2 |
||||
* shorted - index 1 |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_FSL |
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||
*/ |
||||
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull |
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 4, Base address 203000 */ |
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull |
||||
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
||||
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_PCI_INDIRECT_BRIDGE |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_E1000 |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
/* SATA */ |
||||
#ifdef CONFIG_FSL_SATA_V2 |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_FSL_SATA |
||||
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2 |
||||
#define CONFIG_SATA1 |
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
||||
#define CONFIG_SATA2 |
||||
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
||||
|
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_CMD_SATA |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT2 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FMAN_ENET |
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1" |
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_ERRATA |
||||
#define CONFIG_CMD_GREPENV |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_NET |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 64 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||
|
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ROOTPATH "/opt/nfsroot" |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ |
||||
|
||||
/* default location for tftp and bootm */ |
||||
#define CONFIG_LOADADDR 1000000 |
||||
|
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_HVBOOT \ |
||||
"setenv bootargs config-addr=0x60000000; " \
|
||||
"bootm 0x01000000 - 0x00f00000" |
||||
|
||||
#ifdef CONFIG_SYS_NO_FLASH |
||||
#ifndef CONFIG_RAMBOOT_PBL |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#endif |
||||
#else |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SPIFLASH) |
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SPI_BUS 0 |
||||
#define CONFIG_ENV_SPI_CS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000 |
||||
#define CONFIG_ENV_SPI_MODE 0 |
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#elif defined(CONFIG_SDCARD) |
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_OFFSET (512 * 1658) |
||||
#elif defined(CONFIG_NAND) |
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||
#define CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
||||
#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
||||
#elif defined(CONFIG_ENV_IS_NOWHERE) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666 |
||||
#define CONFIG_DDR_CLK_FREQ 133333333 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
unsigned long get_board_sys_clk(void); |
||||
unsigned long get_board_ddr_clk(void); |
||||
#endif |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 |
||||
#define SPD_EEPROM_ADDRESS1 0x52 |
||||
#define SPD_EEPROM_ADDRESS2 0x54 |
||||
#define SPD_EEPROM_ADDRESS3 0x56 |
||||
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
||||
|
||||
/*
|
||||
* IFC Definitions |
||||
*/ |
||||
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) |
||||
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
||||
+ 0x8000000) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) |
||||
#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V) |
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
||||
/* NOR Flash Timing Params */ |
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
||||
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5)) |
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13)) |
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c)) |
||||
#define CONFIG_SYS_NOR_FTIM3 0x0 |
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ |
||||
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
||||
|
||||
/* NAND Flash on IFC */ |
||||
#define CONFIG_NAND_FSL_IFC |
||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256 |
||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
||||
#define CONFIG_SYS_NAND_BASE 0xff800000 |
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) |
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0xf) |
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V) |
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
|
||||
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
|
||||
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
|
||||
| CSOR_NAND_PB(128)) /*Page Per Block = 128*/ |
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */ |
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a)) |
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18)) |
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e)) |
||||
#define CONFIG_SYS_NAND_FTIM3 0x0 |
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11 |
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND |
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) |
||||
|
||||
#if defined(CONFIG_NAND) |
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR |
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
#else |
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
#endif |
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT |
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR |
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR |
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 |
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 |
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 |
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 |
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL) |
||||
#define CONFIG_SYS_RAMBOOT |
||||
#endif |
||||
|
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ |
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ |
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ |
||||
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ |
||||
|
||||
#define I2C_MUX_CH_DEFAULT 0x8 |
||||
#define I2C_MUX_CH_VOL_MONITOR 0xa |
||||
#define I2C_MUX_CH_VSC3316_FS 0xc |
||||
#define I2C_MUX_CH_VSC3316_BS 0xd |
||||
|
||||
/* Voltage monitor on channel 2*/ |
||||
#define I2C_VOL_MONITOR_ADDR 0x40 |
||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 |
||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 |
||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 |
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI |
||||
*/ |
||||
#define CONFIG_FSL_ESPI |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_SST |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000 |
||||
#define CONFIG_SF_DEFAULT_MODE 0 |
||||
|
||||
|
||||
/* Qman/Bman */ |
||||
#ifndef CONFIG_NOBQFMAN |
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 50 |
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN |
||||
#define CONFIG_SYS_DPAA_PME |
||||
#define CONFIG_SYS_PMAN |
||||
#define CONFIG_SYS_DPAA_DCE |
||||
#define CONFIG_SYS_DPAA_RMAN |
||||
#define CONFIG_SYS_INTERLAKEN |
||||
|
||||
/* Default address of microcode for the Linux Fman driver */ |
||||
#if defined(CONFIG_SPIFLASH) |
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after |
||||
* env, so we got 0x110000. |
||||
*/ |
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH |
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
||||
#elif defined(CONFIG_SDCARD) |
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
||||
* about 825KB (1650 blocks), Env is stored after the image, and the env size is |
||||
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. |
||||
*/ |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
||||
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
||||
#elif defined(CONFIG_NAND) |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
||||
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
||||
#else |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
||||
#endif |
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
||||
#endif /* CONFIG_NOBQFMAN */ |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
#define CONFIG_FMAN_ENET |
||||
#define CONFIG_PHYLIB_10G |
||||
#define CONFIG_PHY_VITESSE |
||||
#define CONFIG_PHY_CORTINA |
||||
#define CONFIG_CORTINA_FW_ADDR 0xefe00000 |
||||
#define CONFIG_CORTINA_FW_LENGTH 0x40000 |
||||
#define CONFIG_PHY_TERANETICS |
||||
#define SGMII_PHY_ADDR1 0x0 |
||||
#define SGMII_PHY_ADDR2 0x1 |
||||
#define SGMII_PHY_ADDR3 0x2 |
||||
#define SGMII_PHY_ADDR4 0x3 |
||||
#define SGMII_PHY_ADDR5 0x4 |
||||
#define SGMII_PHY_ADDR6 0x5 |
||||
#define SGMII_PHY_ADDR7 0x6 |
||||
#define SGMII_PHY_ADDR8 0x7 |
||||
#define FM1_10GEC1_PHY_ADDR 0x10 |
||||
#define FM1_10GEC2_PHY_ADDR 0x11 |
||||
#define FM2_10GEC1_PHY_ADDR 0x12 |
||||
#define FM2_10GEC2_PHY_ADDR 0x13 |
||||
#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR |
||||
#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR |
||||
#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR |
||||
#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR |
||||
#endif |
||||
|
||||
|
||||
/* SATA */ |
||||
#ifdef CONFIG_FSL_SATA_V2 |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_FSL_SATA |
||||
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2 |
||||
#define CONFIG_SATA1 |
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
||||
#define CONFIG_SATA2 |
||||
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
||||
|
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_CMD_SATA |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT2 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FMAN_ENET |
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1" |
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
||||
#endif |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_FSL |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_HAS_FSL_DR_USB |
||||
|
||||
#define CONFIG_MMC |
||||
|
||||
#ifdef CONFIG_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
||||
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
|
||||
#define __USB_PHY_TYPE utmi |
||||
|
||||
/*
|
||||
* T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be |
||||
* 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way |
||||
* interleaving. It can be cacheline, page, bank, superbank. |
||||
* See doc/README.fsl-ddr for details. |
||||
*/ |
||||
#define CTRL_INTLV_PREFERED 3way_4KB |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:" \
|
||||
"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
|
||||
"bank_intlv=auto;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=t4240rdb/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=t4240rdb/t4240rdb.dtb\0" \
|
||||
"bdev=sda3\0" |
||||
|
||||
#define CONFIG_HVBOOT \ |
||||
"setenv bootargs config-addr=0x60000000; " \
|
||||
"bootm 0x01000000 - 0x00f00000" |
||||
|
||||
#define CONFIG_LINUX \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_HDBOOT \ |
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX |
||||
|
||||
#include <asm/fsl_secure_boot.h> |
||||
|
||||
#ifdef CONFIG_SECURE_BOOT |
||||
/* Secure Boot target was not getting build for T4240 because of
|
||||
* increased binary size. So the size is being reduced by removing USB |
||||
* which is anyways not used in Secure Environment. |
||||
*/ |
||||
#undef CONFIG_CMD_USB |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue