diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index e8c7503..7c8c05c 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -43,14 +43,6 @@ int board_init(void) /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) - /* configuring the clock based on handoff */ - cm_basic_init(gd->fdt_blob); - - /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); -#endif - return 0; } diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 1b4052c..334a79f 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -11,8 +11,7 @@ #include #include -static const struct socfpga_clock_manager *clock_manager_base = - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; +#ifdef CONFIG_SPL_BUILD static u32 eosc1_hz; static u32 cb_intosc_hz; @@ -232,6 +231,9 @@ static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, return 0; } +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; + /* calculate the intended main VCO frequency based on handoff */ static unsigned int cm_calc_handoff_main_vco_clk_hz (struct mainpll_cfg *main_cfg) @@ -897,7 +899,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) return 0; } -void cm_use_intosc(void) +static void cm_use_intosc(void) { setbits_le32(&clock_manager_base->ctrl, CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); @@ -917,8 +919,11 @@ int cm_basic_init(const void *blob) if (rval) return rval; + cm_use_intosc(); + return cm_full_cfg(&main_cfg, &per_cfg); } +#endif static u32 cm_get_rate_dm(char *name) { diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h index b3c8853..de8c225 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -89,8 +89,9 @@ struct socfpga_clock_manager { struct socfpga_clock_manager_altera altera; }; -void cm_use_intosc(void); +#ifdef CONFIG_SPL_BUILD int cm_basic_init(const void *blob); +#endif unsigned int cm_get_l4_sp_clk_hz(void); unsigned long cm_get_mpu_clk_hz(void); diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index e7e08b7..4fc9570 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -25,6 +25,11 @@ static inline void socfpga_fpga_add(void) {} void socfpga_sdram_remap_zero(void); #endif +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +void socfpga_init_security_policies(void); +void socfpga_sdram_remap_zero(void); +#endif + void do_bridge_reset(int enable); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 284e076..f347ae8 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -28,17 +28,14 @@ #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; #if defined(CONFIG_SPL_BUILD) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; -#endif - -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -#if defined(CONFIG_SPL_BUILD) /* + * This function initializes security policies to be consistent across + * all logic units in the Arria 10. @@ -46,7 +43,7 @@ static struct socfpga_system_manager *sysmgr_regs = + * The idea is to set all security policies to be normal, nonsecure + * for all units. + */ -static void initialize_security_policies(void) +void socfpga_init_security_policies(void) { /* Put OCRAM in non-secure */ writel(0x003f0000, &noc_fw_ocram_base->region0); @@ -66,24 +63,20 @@ static void initialize_security_policies(void) writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); } -int arch_early_init_r(void) +void socfpga_sdram_remap_zero(void) { - initialize_security_policies(); - /* Configure the L2 controller to make SDRAM start at 0 */ writel(0x1, &pl310->pl310_addr_filter_start); - - /* assert reset to all except L4WD0 and L4TIMER0 */ - socfpga_per_reset_all(); - - return 0; } -#else +#endif + int arch_early_init_r(void) { + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + return 0; } -#endif /* * Print CPU information diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 7d35e9d..3ea64f7 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -68,33 +68,26 @@ u32 spl_boot_mode(const u32 boot_device) void spl_board_init(void) { - /* configuring the clock based on handoff */ - cm_basic_init(gd->fdt_blob); - WATCHDOG_RESET(); - - config_dedicated_pins(gd->fdt_blob); - WATCHDOG_RESET(); - /* enable console uart printing */ preloader_console_init(); - WATCHDOG_RESET(); - /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); + arch_early_init_r(); } void board_init_f(ulong dummy) { - /* - * Configure Clock Manager to use intosc clock instead external osc to - * ensure success watchdog operation. We do it as early as possible. - */ - cm_use_intosc(); + socfpga_init_security_policies(); + socfpga_sdram_remap_zero(); + /* Assert reset to all except L4WD0 and L4TIMER0 */ + socfpga_per_reset_all(); socfpga_watchdog_disable(); - arch_early_init_r(); + spl_early_init(); + + /* Configure the clock based on handoff */ + cm_basic_init(gd->fdt_blob); #ifdef CONFIG_HW_WATCHDOG /* release osc1 watchdog timer 0 from reset */ @@ -104,4 +97,7 @@ void board_init_f(ulong dummy) hw_watchdog_init(); WATCHDOG_RESET(); #endif /* CONFIG_HW_WATCHDOG */ + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); }