Wolfgang Denk
16 years ago
commit
0d8cb9c04f
@ -0,0 +1 @@ |
||||
/u-boot.lds |
||||
@ -0,0 +1,57 @@ |
||||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y := $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS-y))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
$(obj)u-boot.lds: u-boot.lds.S |
||||
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,101 @@ |
||||
/*
|
||||
* U-boot - main board file |
||||
* |
||||
* Copyright (c) 2008-2009 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <command.h> |
||||
#include <net.h> |
||||
#include <netdev.h> |
||||
#include <spi.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/net.h> |
||||
#include <asm/mach-common/bits/otp.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("Board: ADI BF518F EZ-Board board\n"); |
||||
printf(" Support: http://blackfin.uclinux.org/\n"); |
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
||||
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; |
||||
return gd->bd->bi_memsize; |
||||
} |
||||
|
||||
#if defined(CONFIG_BFIN_MAC) |
||||
static void board_init_enetaddr(uchar *mac_addr) |
||||
{ |
||||
bool valid_mac = false; |
||||
|
||||
#if 0 |
||||
/* the MAC is stored in OTP memory page 0xDF */ |
||||
uint32_t ret; |
||||
uint64_t otp_mac; |
||||
|
||||
ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac); |
||||
if (!(ret & OTP_MASTER_ERROR)) { |
||||
uchar *otp_mac_p = (uchar *)&otp_mac; |
||||
|
||||
for (ret = 0; ret < 6; ++ret) |
||||
mac_addr[ret] = otp_mac_p[5 - ret]; |
||||
|
||||
if (is_valid_ether_addr(mac_addr)) |
||||
valid_mac = true; |
||||
} |
||||
#endif |
||||
|
||||
if (!valid_mac) { |
||||
puts("Warning: Generating 'random' MAC address\n"); |
||||
bfin_gen_rand_mac(mac_addr); |
||||
} |
||||
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr); |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
static bool switch_is_alive = false; |
||||
int ret; |
||||
|
||||
if (!switch_is_alive) { |
||||
struct spi_slave *slave = spi_setup_slave(0, 1, 5000000, SPI_MODE_3); |
||||
if (slave) { |
||||
if (!spi_claim_bus(slave)) { |
||||
unsigned char dout[3] = { 2, 1, 1, }; |
||||
unsigned char din[3]; |
||||
ret = spi_xfer(slave, sizeof(dout) * 8, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); |
||||
if (!ret) |
||||
switch_is_alive = true; |
||||
spi_release_bus(slave); |
||||
} |
||||
spi_free_slave(slave); |
||||
} |
||||
} |
||||
|
||||
if (switch_is_alive) |
||||
return bfin_EMAC_initialize(bis); |
||||
else |
||||
return -1; |
||||
} |
||||
#endif |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_BFIN_MAC |
||||
uchar enetaddr[6]; |
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
||||
board_init_enetaddr(enetaddr); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,32 @@ |
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# This is not actually used for Blackfin boards so do not change it
|
||||
#TEXT_BASE = do-not-use-me
|
||||
|
||||
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
|
||||
|
||||
# Set some default LDR flags based on boot mode.
|
||||
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
|
||||
@ -0,0 +1,124 @@ |
||||
/* |
||||
* U-boot - u-boot.lds.S |
||||
* |
||||
* Copyright (c) 2005-2008 Analog Device Inc. |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#undef ALIGN |
||||
#undef ENTRY |
||||
#undef bfin |
||||
|
||||
/* If we don't actually load anything into L1 data, this will avoid |
||||
* a syntax error. If we do actually load something into L1 data, |
||||
* we'll get a linker memory load error (which is what we'd want). |
||||
* This is here in the first place so we can quickly test building |
||||
* for different CPU's which may lack non-cache L1 data. |
||||
*/ |
||||
#ifndef L1_DATA_B_SRAM |
||||
# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE |
||||
# define L1_DATA_B_SRAM_SIZE 0 |
||||
#endif |
||||
|
||||
OUTPUT_ARCH(bfin) |
||||
|
||||
MEMORY |
||||
{ |
||||
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
||||
l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE |
||||
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
||||
} |
||||
|
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
.text : |
||||
{ |
||||
cpu/blackfin/start.o (.text .text.*) |
||||
__initcode_start = .;
|
||||
cpu/blackfin/initcode.o (.text .text.*) |
||||
__initcode_end = .;
|
||||
*(.text .text.*) |
||||
} >ram |
||||
|
||||
.rodata : |
||||
{ |
||||
. = ALIGN(4);
|
||||
*(.rodata .rodata.*) |
||||
*(.rodata1) |
||||
*(.eh_frame) |
||||
. = ALIGN(4);
|
||||
} >ram |
||||
|
||||
.data : |
||||
{ |
||||
. = ALIGN(256);
|
||||
*(.data .data.*) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} >ram |
||||
|
||||
.u_boot_cmd : |
||||
{ |
||||
___u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd) |
||||
___u_boot_cmd_end = .;
|
||||
} >ram |
||||
|
||||
.text_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__stext_l1 = .;
|
||||
*(.l1.text) |
||||
. = ALIGN(4);
|
||||
__etext_l1 = .;
|
||||
} >l1_code AT>ram |
||||
__stext_l1_lma = LOADADDR(.text_l1);
|
||||
|
||||
.data_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__sdata_l1 = .;
|
||||
*(.l1.data) |
||||
*(.l1.bss) |
||||
. = ALIGN(4);
|
||||
__edata_l1 = .;
|
||||
} >l1_data AT>ram |
||||
__sdata_l1_lma = LOADADDR(.data_l1);
|
||||
|
||||
.bss : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss .bss.*) |
||||
*(COMMON) |
||||
__bss_end = .;
|
||||
} >ram |
||||
} |
||||
@ -0,0 +1 @@ |
||||
/u-boot.lds |
||||
@ -0,0 +1,58 @@ |
||||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y := $(BOARD).o
|
||||
COBJS-$(CONFIG_STATUS_LED) += status-led.o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS-y))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
$(obj)u-boot.lds: u-boot.lds.S |
||||
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* U-boot - main board file |
||||
* |
||||
* Copyright (c) 2005-2009 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <command.h> |
||||
#include <net.h> |
||||
#include <netdev.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/net.h> |
||||
#include <asm/mach-common/bits/otp.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("Board: ADI BF526 EZ-Board board\n"); |
||||
printf(" Support: http://blackfin.uclinux.org/\n"); |
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
||||
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; |
||||
return gd->bd->bi_memsize; |
||||
} |
||||
|
||||
#ifdef CONFIG_BFIN_MAC |
||||
static void board_init_enetaddr(uchar *mac_addr) |
||||
{ |
||||
bool valid_mac = false; |
||||
|
||||
/* the MAC is stored in OTP memory page 0xDF */ |
||||
uint32_t ret; |
||||
uint64_t otp_mac; |
||||
|
||||
ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac); |
||||
if (!(ret & OTP_MASTER_ERROR)) { |
||||
uchar *otp_mac_p = (uchar *)&otp_mac; |
||||
|
||||
for (ret = 0; ret < 6; ++ret) |
||||
mac_addr[ret] = otp_mac_p[5 - ret]; |
||||
|
||||
if (is_valid_ether_addr(mac_addr)) |
||||
valid_mac = true; |
||||
} |
||||
|
||||
if (!valid_mac) { |
||||
puts("Warning: Generating 'random' MAC address\n"); |
||||
bfin_gen_rand_mac(mac_addr); |
||||
} |
||||
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr); |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return bfin_EMAC_initialize(bis); |
||||
} |
||||
#endif |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_BFIN_MAC |
||||
uchar enetaddr[6]; |
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
||||
board_init_enetaddr(enetaddr); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,32 @@ |
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# This is not actually used for Blackfin boards so do not change it
|
||||
#TEXT_BASE = do-not-use-me
|
||||
|
||||
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
|
||||
|
||||
# Set some default LDR flags based on boot mode.
|
||||
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
|
||||
@ -0,0 +1,56 @@ |
||||
/*
|
||||
* U-boot - status leds |
||||
* |
||||
* Copyright (c) 2005-2009 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <command.h> |
||||
#include <status_led.h> |
||||
|
||||
static void set_led_f(int pf, int state) |
||||
{ |
||||
switch (state) { |
||||
case STATUS_LED_OFF: bfin_write_PORTFIO_CLEAR(pf); break; |
||||
case STATUS_LED_BLINKING: bfin_write_PORTFIO_TOGGLE(pf); break; |
||||
case STATUS_LED_ON: bfin_write_PORTFIO_SET(pf); break; |
||||
} |
||||
} |
||||
static void set_led_g(int pf, int state) |
||||
{ |
||||
switch (state) { |
||||
case STATUS_LED_OFF: bfin_write_PORTGIO_CLEAR(pf); break; |
||||
case STATUS_LED_BLINKING: bfin_write_PORTGIO_TOGGLE(pf); break; |
||||
case STATUS_LED_ON: bfin_write_PORTGIO_SET(pf); break; |
||||
} |
||||
} |
||||
|
||||
static void set_leds(led_id_t mask, int state) |
||||
{ |
||||
if (mask & 0x1) set_led_f(PF8, state); |
||||
if (mask & 0x2) set_led_g(PG11, state); |
||||
if (mask & 0x4) set_led_g(PG12, state); |
||||
} |
||||
|
||||
void __led_init(led_id_t mask, int state) |
||||
{ |
||||
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8)); |
||||
bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12)); |
||||
bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8)); |
||||
bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12)); |
||||
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8)); |
||||
bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12)); |
||||
} |
||||
|
||||
void __led_set(led_id_t mask, int state) |
||||
{ |
||||
set_leds(mask, state); |
||||
} |
||||
|
||||
void __led_toggle(led_id_t mask) |
||||
{ |
||||
set_leds(mask, STATUS_LED_BLINKING); |
||||
} |
||||
@ -0,0 +1,124 @@ |
||||
/* |
||||
* U-boot - u-boot.lds.S |
||||
* |
||||
* Copyright (c) 2005-2008 Analog Device Inc. |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#undef ALIGN |
||||
#undef ENTRY |
||||
#undef bfin |
||||
|
||||
/* If we don't actually load anything into L1 data, this will avoid |
||||
* a syntax error. If we do actually load something into L1 data, |
||||
* we'll get a linker memory load error (which is what we'd want). |
||||
* This is here in the first place so we can quickly test building |
||||
* for different CPU's which may lack non-cache L1 data. |
||||
*/ |
||||
#ifndef L1_DATA_B_SRAM |
||||
# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE |
||||
# define L1_DATA_B_SRAM_SIZE 0 |
||||
#endif |
||||
|
||||
OUTPUT_ARCH(bfin) |
||||
|
||||
MEMORY |
||||
{ |
||||
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
||||
l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE |
||||
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
||||
} |
||||
|
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
.text : |
||||
{ |
||||
cpu/blackfin/start.o (.text .text.*) |
||||
__initcode_start = .;
|
||||
cpu/blackfin/initcode.o (.text .text.*) |
||||
__initcode_end = .;
|
||||
*(.text .text.*) |
||||
} >ram |
||||
|
||||
.rodata : |
||||
{ |
||||
. = ALIGN(4);
|
||||
*(.rodata .rodata.*) |
||||
*(.rodata1) |
||||
*(.eh_frame) |
||||
. = ALIGN(4);
|
||||
} >ram |
||||
|
||||
.data : |
||||
{ |
||||
. = ALIGN(256);
|
||||
*(.data .data.*) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} >ram |
||||
|
||||
.u_boot_cmd : |
||||
{ |
||||
___u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd) |
||||
___u_boot_cmd_end = .;
|
||||
} >ram |
||||
|
||||
.text_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__stext_l1 = .;
|
||||
*(.l1.text) |
||||
. = ALIGN(4);
|
||||
__etext_l1 = .;
|
||||
} >l1_code AT>ram |
||||
__stext_l1_lma = LOADADDR(.text_l1);
|
||||
|
||||
.data_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__sdata_l1 = .;
|
||||
*(.l1.data) |
||||
*(.l1.bss) |
||||
. = ALIGN(4);
|
||||
__edata_l1 = .;
|
||||
} >l1_data AT>ram |
||||
__sdata_l1_lma = LOADADDR(.data_l1);
|
||||
|
||||
.bss : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss .bss.*) |
||||
*(COMMON) |
||||
__bss_end = .;
|
||||
} >ram |
||||
} |
||||
@ -0,0 +1 @@ |
||||
/u-boot.lds |
||||
@ -0,0 +1,58 @@ |
||||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y := $(BOARD).o
|
||||
COBJS-$(CONFIG_VIDEO) += video.o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS-y))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
$(obj)u-boot.lds: u-boot.lds.S |
||||
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* U-boot - main board file |
||||
* |
||||
* Copyright (c) 2005-2009 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <command.h> |
||||
#include <net.h> |
||||
#include <netdev.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/net.h> |
||||
#include <asm/mach-common/bits/otp.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("Board: ADI BF527 EZ-Kit board\n"); |
||||
printf(" Support: http://blackfin.uclinux.org/\n"); |
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
||||
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; |
||||
return gd->bd->bi_memsize; |
||||
} |
||||
|
||||
#ifdef CONFIG_BFIN_MAC |
||||
static void board_init_enetaddr(uchar *mac_addr) |
||||
{ |
||||
bool valid_mac = false; |
||||
|
||||
/* the MAC is stored in OTP memory page 0xDF */ |
||||
uint32_t ret; |
||||
uint64_t otp_mac; |
||||
|
||||
ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac); |
||||
if (!(ret & OTP_MASTER_ERROR)) { |
||||
uchar *otp_mac_p = (uchar *)&otp_mac; |
||||
|
||||
for (ret = 0; ret < 6; ++ret) |
||||
mac_addr[ret] = otp_mac_p[5 - ret]; |
||||
|
||||
if (is_valid_ether_addr(mac_addr)) |
||||
valid_mac = true; |
||||
} |
||||
|
||||
if (!valid_mac) { |
||||
puts("Warning: Generating 'random' MAC address\n"); |
||||
bfin_gen_rand_mac(mac_addr); |
||||
} |
||||
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr); |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return bfin_EMAC_initialize(bis); |
||||
} |
||||
#endif |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_BFIN_MAC |
||||
uchar enetaddr[6]; |
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
||||
board_init_enetaddr(enetaddr); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,32 @@ |
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# This is not actually used for Blackfin boards so do not change it
|
||||
#TEXT_BASE = do-not-use-me
|
||||
|
||||
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
|
||||
|
||||
# Set some default LDR flags based on boot mode.
|
||||
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
|
||||
@ -0,0 +1,124 @@ |
||||
/* |
||||
* U-boot - u-boot.lds.S |
||||
* |
||||
* Copyright (c) 2005-2008 Analog Device Inc. |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#undef ALIGN |
||||
#undef ENTRY |
||||
#undef bfin |
||||
|
||||
/* If we don't actually load anything into L1 data, this will avoid |
||||
* a syntax error. If we do actually load something into L1 data, |
||||
* we'll get a linker memory load error (which is what we'd want). |
||||
* This is here in the first place so we can quickly test building |
||||
* for different CPU's which may lack non-cache L1 data. |
||||
*/ |
||||
#ifndef L1_DATA_B_SRAM |
||||
# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE |
||||
# define L1_DATA_B_SRAM_SIZE 0 |
||||
#endif |
||||
|
||||
OUTPUT_ARCH(bfin) |
||||
|
||||
MEMORY |
||||
{ |
||||
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
||||
l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE |
||||
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
||||
} |
||||
|
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
.text : |
||||
{ |
||||
cpu/blackfin/start.o (.text .text.*) |
||||
__initcode_start = .;
|
||||
cpu/blackfin/initcode.o (.text .text.*) |
||||
__initcode_end = .;
|
||||
*(.text .text.*) |
||||
} >ram |
||||
|
||||
.rodata : |
||||
{ |
||||
. = ALIGN(4);
|
||||
*(.rodata .rodata.*) |
||||
*(.rodata1) |
||||
*(.eh_frame) |
||||
. = ALIGN(4);
|
||||
} >ram |
||||
|
||||
.data : |
||||
{ |
||||
. = ALIGN(256);
|
||||
*(.data .data.*) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} >ram |
||||
|
||||
.u_boot_cmd : |
||||
{ |
||||
___u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd) |
||||
___u_boot_cmd_end = .;
|
||||
} >ram |
||||
|
||||
.text_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__stext_l1 = .;
|
||||
*(.l1.text) |
||||
. = ALIGN(4);
|
||||
__etext_l1 = .;
|
||||
} >l1_code AT>ram |
||||
__stext_l1_lma = LOADADDR(.text_l1);
|
||||
|
||||
.data_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__sdata_l1 = .;
|
||||
*(.l1.data) |
||||
*(.l1.bss) |
||||
. = ALIGN(4);
|
||||
__edata_l1 = .;
|
||||
} >l1_data AT>ram |
||||
__sdata_l1_lma = LOADADDR(.data_l1);
|
||||
|
||||
.bss : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss .bss.*) |
||||
*(COMMON) |
||||
__bss_end = .;
|
||||
} >ram |
||||
} |
||||
@ -0,0 +1,317 @@ |
||||
/*
|
||||
* video.c - run splash screen on lcd |
||||
* |
||||
* Copyright (c) 2007-2008 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <stdarg.h> |
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <malloc.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/mach-common/bits/dma.h> |
||||
#include <i2c.h> |
||||
#include <linux/types.h> |
||||
#include <devices.h> |
||||
|
||||
int gunzip(void *, int, unsigned char *, unsigned long *); |
||||
|
||||
#define DMA_SIZE16 2 |
||||
|
||||
#include <asm/mach-common/bits/ppi.h> |
||||
#include <asm/mach-common/bits/timer.h> |
||||
|
||||
#include <asm/bfin_logo_230x230.h> |
||||
|
||||
#define LCD_X_RES 320 /* Horizontal Resolution */ |
||||
#define LCD_Y_RES 240 /* Vertical Resolution */ |
||||
#define LCD_BPP 24 /* Bit Per Pixel */ |
||||
#define LCD_PIXEL_SIZE (LCD_BPP / 8) |
||||
|
||||
#define DMA_BUS_SIZE 16 |
||||
#define LCD_CLK (12*1000*1000) /* 12MHz */ |
||||
|
||||
#define CLOCKS_PER_PIX 3 |
||||
|
||||
/* HS and VS timing parameters (all in number of PPI clk ticks) */ |
||||
#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */ |
||||
#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */ |
||||
#define H_PULSE 90 /* HS pulse width */ |
||||
#define H_START 204 /* first valid pixel */ |
||||
|
||||
#define U_LINE 1 /* Blanking Lines */ |
||||
|
||||
#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */ |
||||
#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */ |
||||
#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */ |
||||
|
||||
#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX) |
||||
|
||||
#define PPI_TX_MODE 0x2 |
||||
#define PPI_XFER_TYPE_11 0xC |
||||
#define PPI_PORT_CFG_01 0x10 |
||||
#define PPI_PACK_EN 0x80 |
||||
#define PPI_POLS_1 0x8000 |
||||
|
||||
/* enable and disable PPI functions */ |
||||
void EnablePPI(void) |
||||
{ |
||||
*pPPI_CONTROL |= PORT_EN; |
||||
} |
||||
|
||||
void DisablePPI(void) |
||||
{ |
||||
*pPPI_CONTROL &= ~PORT_EN; |
||||
} |
||||
|
||||
void Init_Ports(void) |
||||
{ |
||||
*pPORTF_MUX &= ~PORT_x_MUX_0_MASK; |
||||
*pPORTF_MUX |= PORT_x_MUX_0_FUNC_1; |
||||
*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7; |
||||
|
||||
*pPORTG_MUX &= ~PORT_x_MUX_1_MASK; |
||||
*pPORTG_MUX |= PORT_x_MUX_1_FUNC_1; |
||||
*pPORTG_FER |= PG5; |
||||
} |
||||
|
||||
void Init_PPI(void) |
||||
{ |
||||
|
||||
*pPPI_DELAY = H_START; |
||||
*pPPI_COUNT = (H_ACTPIX-1); |
||||
*pPPI_FRAME = 0; |
||||
|
||||
/* PPI control, to be replaced with definitions */ |
||||
*pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */ |
||||
PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ |
||||
PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ |
||||
PPI_PACK_EN | /* packing enabled PACK_EN */ |
||||
PPI_POLS_1; /* faling edge syncs POLS */ |
||||
} |
||||
|
||||
void Init_DMA(void *dst) |
||||
{ |
||||
*pDMA0_START_ADDR = dst; |
||||
|
||||
/* X count */ |
||||
*pDMA0_X_COUNT = H_ACTPIX / 2; |
||||
*pDMA0_X_MODIFY = DMA_BUS_SIZE / 8; |
||||
|
||||
/* Y count */ |
||||
*pDMA0_Y_COUNT = V_LINES; |
||||
*pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8; |
||||
|
||||
/* DMA Config */ |
||||
*pDMA0_CONFIG = |
||||
WDSIZE_16 | /* 16 bit DMA */ |
||||
DMA2D | /* 2D DMA */ |
||||
FLOW_AUTO; /* autobuffer mode */ |
||||
} |
||||
|
||||
|
||||
void EnableDMA(void) |
||||
{ |
||||
*pDMA0_CONFIG |= DMAEN; |
||||
} |
||||
|
||||
void DisableDMA(void) |
||||
{ |
||||
*pDMA0_CONFIG &= ~DMAEN; |
||||
} |
||||
|
||||
|
||||
/* Init TIMER0 as Frame Sync 1 generator */ |
||||
void InitTIMER0(void) |
||||
{ |
||||
*pTIMER_DISABLE |= TIMDIS0; /* disable Timer */ |
||||
SSYNC(); |
||||
*pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */ |
||||
SSYNC(); |
||||
|
||||
*pTIMER0_PERIOD = H_PERIOD; |
||||
SSYNC(); |
||||
*pTIMER0_WIDTH = H_PULSE; |
||||
SSYNC(); |
||||
|
||||
*pTIMER0_CONFIG = PWM_OUT | |
||||
PERIOD_CNT | |
||||
TIN_SEL | |
||||
CLK_SEL | |
||||
EMU_RUN; |
||||
SSYNC(); |
||||
} |
||||
|
||||
void EnableTIMER0(void) |
||||
{ |
||||
*pTIMER_ENABLE |= TIMEN0; |
||||
SSYNC(); |
||||
} |
||||
|
||||
void DisableTIMER0(void) |
||||
{ |
||||
*pTIMER_DISABLE |= TIMDIS0; |
||||
SSYNC(); |
||||
} |
||||
|
||||
|
||||
void InitTIMER1(void) |
||||
{ |
||||
*pTIMER_DISABLE |= TIMDIS1; /* disable Timer */ |
||||
SSYNC(); |
||||
*pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */ |
||||
SSYNC(); |
||||
|
||||
|
||||
*pTIMER1_PERIOD = V_PERIOD; |
||||
SSYNC(); |
||||
*pTIMER1_WIDTH = V_PULSE; |
||||
SSYNC(); |
||||
|
||||
*pTIMER1_CONFIG = PWM_OUT | |
||||
PERIOD_CNT | |
||||
TIN_SEL | |
||||
CLK_SEL | |
||||
EMU_RUN; |
||||
SSYNC(); |
||||
} |
||||
|
||||
void EnableTIMER1(void) |
||||
{ |
||||
*pTIMER_ENABLE |= TIMEN1; |
||||
SSYNC(); |
||||
} |
||||
|
||||
void DisableTIMER1(void) |
||||
{ |
||||
*pTIMER_DISABLE |= TIMDIS1; |
||||
SSYNC(); |
||||
} |
||||
|
||||
int video_init(void *dst) |
||||
{ |
||||
|
||||
Init_Ports(); |
||||
Init_DMA(dst); |
||||
EnableDMA(); |
||||
InitTIMER0(); |
||||
InitTIMER1(); |
||||
Init_PPI(); |
||||
EnablePPI(); |
||||
|
||||
/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */ |
||||
EnableTIMER1(); |
||||
/* Add Some Delay ... */ |
||||
SSYNC(); |
||||
SSYNC(); |
||||
SSYNC(); |
||||
SSYNC(); |
||||
|
||||
/* now start frame sync 1 */ |
||||
EnableTIMER0(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) |
||||
{ |
||||
if (dcache_status()) |
||||
blackfin_dcache_flush_range(logo->data, logo->data + logo->size); |
||||
|
||||
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
||||
|
||||
/* Setup destination start address */ |
||||
bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE) |
||||
+ (y * LCD_X_RES * LCD_PIXEL_SIZE)); |
||||
/* Setup destination xcount */ |
||||
bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); |
||||
/* Setup destination xmodify */ |
||||
bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16); |
||||
|
||||
/* Setup destination ycount */ |
||||
bfin_write_MDMA_D0_Y_COUNT(logo->height); |
||||
/* Setup destination ymodify */ |
||||
bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16); |
||||
|
||||
|
||||
/* Setup Source start address */ |
||||
bfin_write_MDMA_S0_START_ADDR(logo->data); |
||||
/* Setup Source xcount */ |
||||
bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); |
||||
/* Setup Source xmodify */ |
||||
bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16); |
||||
|
||||
/* Setup Source ycount */ |
||||
bfin_write_MDMA_S0_Y_COUNT(logo->height); |
||||
/* Setup Source ymodify */ |
||||
bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16); |
||||
|
||||
|
||||
/* Enable source DMA */ |
||||
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D); |
||||
SSYNC(); |
||||
bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D); |
||||
|
||||
while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN); |
||||
|
||||
bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR); |
||||
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR); |
||||
|
||||
} |
||||
|
||||
void video_putc(const char c) |
||||
{ |
||||
} |
||||
|
||||
void video_puts(const char *s) |
||||
{ |
||||
} |
||||
|
||||
int drv_video_init(void) |
||||
{ |
||||
int error, devices = 1; |
||||
device_t videodev; |
||||
|
||||
u8 *dst; |
||||
u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET; |
||||
|
||||
dst = malloc(fbmem_size); |
||||
|
||||
if (dst == NULL) { |
||||
printf("Failed to alloc FB memory\n"); |
||||
return -1; |
||||
} |
||||
|
||||
#ifdef EASYLOGO_ENABLE_GZIP |
||||
unsigned char *data = EASYLOGO_DECOMP_BUFFER; |
||||
unsigned long src_len = EASYLOGO_ENABLE_GZIP; |
||||
if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { |
||||
puts("Failed to decompress logo\n"); |
||||
free(dst); |
||||
return -1; |
||||
} |
||||
bfin_logo.data = data; |
||||
#endif |
||||
|
||||
memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); |
||||
|
||||
dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo, |
||||
(LCD_X_RES - bfin_logo.width) / 2, |
||||
(LCD_Y_RES - bfin_logo.height) / 2); |
||||
|
||||
video_init(dst); /* Video initialization */ |
||||
|
||||
memset(&videodev, 0, sizeof(videodev)); |
||||
|
||||
strcpy(videodev.name, "video"); |
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ |
||||
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ |
||||
videodev.putc = video_putc; /* 'putc' function */ |
||||
videodev.puts = video_puts; /* 'puts' function */ |
||||
|
||||
error = device_register(&videodev); |
||||
|
||||
return (error == 0) ? devices : error; |
||||
} |
||||
@ -1,2 +0,0 @@ |
||||
/* Share the spi flash code */ |
||||
#include "../bf537-stamp/spi_flash.c" |
||||
@ -0,0 +1,66 @@ |
||||
/*
|
||||
* CF IDE addon card code |
||||
* |
||||
* Enter bugs at http://blackfin.uclinux.org/
|
||||
* |
||||
* Copyright (c) 2005-2009 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <command.h> |
||||
#include <asm/blackfin.h> |
||||
|
||||
void cf_outb(unsigned char val, volatile unsigned char *addr) |
||||
{ |
||||
*(addr) = val; |
||||
SSYNC(); |
||||
} |
||||
|
||||
unsigned char cf_inb(volatile unsigned char *addr) |
||||
{ |
||||
volatile unsigned char c; |
||||
|
||||
c = *(addr); |
||||
SSYNC(); |
||||
|
||||
return c; |
||||
} |
||||
|
||||
void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < words; i++) |
||||
*(sect_buf + i) = *(addr); |
||||
SSYNC(); |
||||
} |
||||
|
||||
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < words; i++) |
||||
*(addr) = *(sect_buf + i); |
||||
SSYNC(); |
||||
} |
||||
|
||||
void cf_ide_init(void) |
||||
{ |
||||
#if defined(CONFIG_BFIN_TRUE_IDE) |
||||
/* Enable ATASEL when in True IDE mode */ |
||||
printf("Using CF True IDE Mode\n"); |
||||
cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA); |
||||
udelay(1000); |
||||
#elif defined(CONFIG_BFIN_CF_IDE) |
||||
/* Disable ATASEL when we're in Common Memory Mode */ |
||||
printf("Using CF Common Memory Mode\n"); |
||||
cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS); |
||||
udelay(1000); |
||||
#elif defined(CONFIG_BFIN_HDD_IDE) |
||||
printf("Using HDD IDE Mode\n"); |
||||
#endif |
||||
ide_init(); |
||||
} |
||||
@ -0,0 +1 @@ |
||||
/u-boot.lds |
||||
@ -0,0 +1,57 @@ |
||||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y := $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS-y))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
$(obj)u-boot.lds: u-boot.lds.S |
||||
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* U-boot - main board file |
||||
* |
||||
* Copyright (c) 2008 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("Board: ADI BF538F EZ-Kit Lite board\n"); |
||||
printf(" Support: http://blackfin.uclinux.org/\n"); |
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
||||
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; |
||||
return gd->bd->bi_memsize; |
||||
} |
||||
@ -0,0 +1,33 @@ |
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# This is not actually used for Blackfin boards so do not change it
|
||||
#TEXT_BASE = do-not-use-me
|
||||
|
||||
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
|
||||
|
||||
# Set some default LDR flags based on boot mode.
|
||||
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
|
||||
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
|
||||
@ -0,0 +1,143 @@ |
||||
/* |
||||
* U-boot - u-boot.lds.S |
||||
* |
||||
* Copyright (c) 2005-2008 Analog Device Inc. |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#undef ALIGN |
||||
#undef ENTRY |
||||
#undef bfin |
||||
|
||||
/* If we don't actually load anything into L1 data, this will avoid |
||||
* a syntax error. If we do actually load something into L1 data, |
||||
* we'll get a linker memory load error (which is what we'd want). |
||||
* This is here in the first place so we can quickly test building |
||||
* for different CPU's which may lack non-cache L1 data. |
||||
*/ |
||||
#ifndef L1_DATA_B_SRAM |
||||
# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE |
||||
# define L1_DATA_B_SRAM_SIZE 0 |
||||
#endif |
||||
|
||||
OUTPUT_ARCH(bfin) |
||||
|
||||
MEMORY |
||||
{ |
||||
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
||||
l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE |
||||
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
||||
} |
||||
|
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
.text : |
||||
{ |
||||
cpu/blackfin/start.o (.text .text.*) |
||||
|
||||
#ifdef ENV_IS_EMBEDDED |
||||
/* WARNING - the following is hand-optimized to fit within |
||||
* the sector before the environment sector. If it throws |
||||
* an error during compilation remove an object here to get |
||||
* it linked after the configuration sector. |
||||
*/ |
||||
|
||||
cpu/blackfin/traps.o (.text .text.*) |
||||
cpu/blackfin/interrupt.o (.text .text.*) |
||||
cpu/blackfin/serial.o (.text .text.*) |
||||
common/dlmalloc.o (.text .text.*) |
||||
lib_generic/crc32.o (.text .text.*) |
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/env_embedded.o (.text .text.*) |
||||
#endif |
||||
|
||||
__initcode_start = .;
|
||||
cpu/blackfin/initcode.o (.text .text.*) |
||||
__initcode_end = .;
|
||||
|
||||
*(.text .text.*) |
||||
} >ram |
||||
|
||||
.rodata : |
||||
{ |
||||
. = ALIGN(4);
|
||||
*(.rodata .rodata.*) |
||||
*(.rodata1) |
||||
*(.eh_frame) |
||||
. = ALIGN(4);
|
||||
} >ram |
||||
|
||||
.data : |
||||
{ |
||||
. = ALIGN(256);
|
||||
*(.data .data.*) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} >ram |
||||
|
||||
.u_boot_cmd : |
||||
{ |
||||
___u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd) |
||||
___u_boot_cmd_end = .;
|
||||
} >ram |
||||
|
||||
.text_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__stext_l1 = .;
|
||||
*(.l1.text) |
||||
. = ALIGN(4);
|
||||
__etext_l1 = .;
|
||||
} >l1_code AT>ram |
||||
__stext_l1_lma = LOADADDR(.text_l1);
|
||||
|
||||
.data_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__sdata_l1 = .;
|
||||
*(.l1.data) |
||||
*(.l1.bss) |
||||
. = ALIGN(4);
|
||||
__edata_l1 = .;
|
||||
} >l1_data AT>ram |
||||
__sdata_l1_lma = LOADADDR(.data_l1);
|
||||
|
||||
.bss : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss .bss.*) |
||||
*(COMMON) |
||||
__bss_end = .;
|
||||
} >ram |
||||
} |
||||
@ -0,0 +1 @@ |
||||
/u-boot.lds |
||||
@ -0,0 +1,58 @@ |
||||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y := $(BOARD).o
|
||||
COBJS-$(CONFIG_VIDEO) += video.o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS-y))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
$(obj)u-boot.lds: u-boot.lds.S |
||||
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,79 @@ |
||||
/*
|
||||
* U-boot - main board file |
||||
* |
||||
* Copyright (c) 2005-2008 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <command.h> |
||||
#include <asm/blackfin.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("Board: ADI BF548 EZ-Kit board\n"); |
||||
printf(" Support: http://blackfin.uclinux.org/\n"); |
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
||||
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; |
||||
return gd->bd->bi_memsize; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
/* Port H: PH8 - PH13 == A4 - A9
|
||||
* address lines of the parallel asynchronous memory interface |
||||
*/ |
||||
|
||||
/************************************************
|
||||
* configure GPIO * |
||||
* set port H function enable register * |
||||
* configure PH8-PH13 as peripheral (not GPIO) * |
||||
*************************************************/ |
||||
bfin_write_PORTH_FER(0x3F03); |
||||
|
||||
/************************************************
|
||||
* set port H MUX to configure PH8-PH13 * |
||||
* 1st Function (MUX = 00) (bits 16-27 == 0) * |
||||
* Set to address signals A4-A9 * |
||||
*************************************************/ |
||||
bfin_write_PORTH_MUX(0); |
||||
|
||||
/************************************************
|
||||
* set port H direction register * |
||||
* enable PH8-PH13 as outputs * |
||||
*************************************************/ |
||||
bfin_write_PORTH_DIR_SET(0x3F00); |
||||
|
||||
/* Port I: PI0 - PH14 == A10 - A24
|
||||
* address lines of the parallel asynchronous memory interface |
||||
*/ |
||||
|
||||
/************************************************
|
||||
* set port I function enable register * |
||||
* configure PI0-PI14 as peripheral (not GPIO) * |
||||
*************************************************/ |
||||
bfin_write_PORTI_FER(0x7fff); |
||||
|
||||
/**************************************************
|
||||
* set PORT I MUX to configure PI14-PI0 as * |
||||
* 1st Function (MUX=00) - address signals A10-A24 * |
||||
***************************************************/ |
||||
bfin_write_PORTI_MUX(0); |
||||
|
||||
/****************************************
|
||||
* set PORT I direction register * |
||||
* enable PI0 - PI14 as outputs * |
||||
*****************************************/ |
||||
bfin_write_PORTI_DIR_SET(0x7fff); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,37 @@ |
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# This is not actually used for Blackfin boards so do not change it
|
||||
#TEXT_BASE = do-not-use-me
|
||||
|
||||
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
|
||||
|
||||
# Set some default LDR flags based on boot mode.
|
||||
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
|
||||
LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
|
||||
LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
|
||||
LDR_FLAGS-BFIN_BOOT_UART := --dma 1
|
||||
LDR_FLAGS-BFIN_BOOT_NAND := --dma 6
|
||||
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
|
||||
@ -0,0 +1,124 @@ |
||||
/* |
||||
* U-boot - u-boot.lds.S |
||||
* |
||||
* Copyright (c) 2005-2008 Analog Device Inc. |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#undef ALIGN |
||||
#undef ENTRY |
||||
#undef bfin |
||||
|
||||
/* If we don't actually load anything into L1 data, this will avoid |
||||
* a syntax error. If we do actually load something into L1 data, |
||||
* we'll get a linker memory load error (which is what we'd want). |
||||
* This is here in the first place so we can quickly test building |
||||
* for different CPU's which may lack non-cache L1 data. |
||||
*/ |
||||
#ifndef L1_DATA_B_SRAM |
||||
# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE |
||||
# define L1_DATA_B_SRAM_SIZE 0 |
||||
#endif |
||||
|
||||
OUTPUT_ARCH(bfin) |
||||
|
||||
MEMORY |
||||
{ |
||||
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
||||
l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE |
||||
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
||||
} |
||||
|
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
.text : |
||||
{ |
||||
cpu/blackfin/start.o (.text .text.*) |
||||
__initcode_start = .;
|
||||
cpu/blackfin/initcode.o (.text .text.*) |
||||
__initcode_end = .;
|
||||
*(.text .text.*) |
||||
} >ram |
||||
|
||||
.rodata : |
||||
{ |
||||
. = ALIGN(4);
|
||||
*(.rodata .rodata.*) |
||||
*(.rodata1) |
||||
*(.eh_frame) |
||||
. = ALIGN(4);
|
||||
} >ram |
||||
|
||||
.data : |
||||
{ |
||||
. = ALIGN(256);
|
||||
*(.data .data.*) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} >ram |
||||
|
||||
.u_boot_cmd : |
||||
{ |
||||
___u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd) |
||||
___u_boot_cmd_end = .;
|
||||
} >ram |
||||
|
||||
.text_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__stext_l1 = .;
|
||||
*(.l1.text) |
||||
. = ALIGN(4);
|
||||
__etext_l1 = .;
|
||||
} >l1_code AT>ram |
||||
__stext_l1_lma = LOADADDR(.text_l1);
|
||||
|
||||
.data_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__sdata_l1 = .;
|
||||
*(.l1.data) |
||||
*(.l1.bss) |
||||
. = ALIGN(4);
|
||||
__edata_l1 = .;
|
||||
} >l1_data AT>ram |
||||
__sdata_l1_lma = LOADADDR(.data_l1);
|
||||
|
||||
.bss : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss .bss.*) |
||||
*(COMMON) |
||||
__bss_end = .;
|
||||
} >ram |
||||
} |
||||
@ -0,0 +1,327 @@ |
||||
/*
|
||||
* video.c - run splash screen on lcd |
||||
* |
||||
* Copyright (c) 2007-2008 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <stdarg.h> |
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <malloc.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/mach-common/bits/dma.h> |
||||
#include <i2c.h> |
||||
#include <linux/types.h> |
||||
#include <devices.h> |
||||
|
||||
int gunzip(void *, int, unsigned char *, unsigned long *); |
||||
|
||||
#define DMA_SIZE16 2 |
||||
|
||||
#include <asm/mach-common/bits/eppi.h> |
||||
|
||||
#include <asm/bfin_logo_230x230.h> |
||||
|
||||
#define LCD_X_RES 480 /*Horizontal Resolution */ |
||||
#define LCD_Y_RES 272 /* Vertical Resolution */ |
||||
|
||||
#define LCD_BPP 24 /* Bit Per Pixel */ |
||||
#define LCD_PIXEL_SIZE (LCD_BPP / 8) |
||||
#define DMA_BUS_SIZE 32 |
||||
#define ACTIVE_VIDEO_MEM_OFFSET 0 |
||||
|
||||
/* -- Horizontal synchronizing --
|
||||
* |
||||
* Timing characteristics taken from the SHARP LQ043T1DG01 datasheet |
||||
* (LCY-W-06602A Page 9 of 22) |
||||
* |
||||
* Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz |
||||
* |
||||
* Period TH - 525 - Clock |
||||
* Pulse width THp - 41 - Clock |
||||
* Horizontal period THd - 480 - Clock |
||||
* Back porch THb - 2 - Clock |
||||
* Front porch THf - 2 - Clock |
||||
* |
||||
* -- Vertical synchronizing -- |
||||
* Period TV - 286 - Line |
||||
* Pulse width TVp - 10 - Line |
||||
* Vertical period TVd - 272 - Line |
||||
* Back porch TVb - 2 - Line |
||||
* Front porch TVf - 2 - Line |
||||
*/ |
||||
|
||||
#define LCD_CLK (8*1000*1000) /* 8MHz */ |
||||
|
||||
/* # active data to transfer after Horizontal Delay clock */ |
||||
#define EPPI_HCOUNT LCD_X_RES |
||||
|
||||
/* # active lines to transfer after Vertical Delay clock */ |
||||
#define EPPI_VCOUNT LCD_Y_RES |
||||
|
||||
/* Samples per Line = 480 (active data) + 45 (padding) */ |
||||
#define EPPI_LINE 525 |
||||
|
||||
/* Lines per Frame = 272 (active data) + 14 (padding) */ |
||||
#define EPPI_FRAME 286 |
||||
|
||||
/* FS1 (Hsync) Width (Typical)*/ |
||||
#define EPPI_FS1W_HBL 41 |
||||
|
||||
/* FS1 (Hsync) Period (Typical) */ |
||||
#define EPPI_FS1P_AVPL EPPI_LINE |
||||
|
||||
/* Horizontal Delay clock after assertion of Hsync (Typical) */ |
||||
#define EPPI_HDELAY 43 |
||||
|
||||
/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */ |
||||
#define EPPI_FS2W_LVB (EPPI_LINE * 10) |
||||
|
||||
/* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */ |
||||
#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME) |
||||
|
||||
/* Vertical Delay after assertion of Vsync (2 Lines) */ |
||||
#define EPPI_VDELAY 12 |
||||
|
||||
#define EPPI_CLIP 0xFF00FF00 |
||||
|
||||
/* EPPI Control register configuration value for RGB out
|
||||
* - EPPI as Output |
||||
* GP 2 frame sync mode, |
||||
* Internal Clock generation disabled, Internal FS generation enabled, |
||||
* Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge, |
||||
* FS1 & FS2 are active high, |
||||
* DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) |
||||
* DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled |
||||
* Swapping Enabled, |
||||
* One (DMA) Channel Mode, |
||||
* RGB Formatting Enabled for RGB666 output, disabled for RGB888 output |
||||
* Regular watermark - when FIFO is 100% full, |
||||
* Urgent watermark - when FIFO is 75% full |
||||
*/ |
||||
|
||||
#define EPPI_CONTROL (0x20136E2E) |
||||
|
||||
static inline u16 get_eppi_clkdiv(u32 target_ppi_clk) |
||||
{ |
||||
u32 sclk = get_sclk(); |
||||
|
||||
/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */ |
||||
|
||||
return (((sclk / target_ppi_clk) / 2) - 1); |
||||
} |
||||
|
||||
void Init_PPI(void) |
||||
{ |
||||
u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK); |
||||
|
||||
bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL); |
||||
bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL); |
||||
bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB); |
||||
bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF); |
||||
bfin_write_EPPI0_CLIP(EPPI_CLIP); |
||||
|
||||
bfin_write_EPPI0_FRAME(EPPI_FRAME); |
||||
bfin_write_EPPI0_LINE(EPPI_LINE); |
||||
|
||||
bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT); |
||||
bfin_write_EPPI0_HDELAY(EPPI_HDELAY); |
||||
bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT); |
||||
bfin_write_EPPI0_VDELAY(EPPI_VDELAY); |
||||
|
||||
bfin_write_EPPI0_CLKDIV(eppi_clkdiv); |
||||
|
||||
/*
|
||||
* DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) |
||||
* RGB Formatting Enabled for RGB666 output, disabled for RGB888 output |
||||
*/ |
||||
#if defined(CONFIG_VIDEO_RGB666) |
||||
bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 | |
||||
RGB_FMT_EN); |
||||
#else |
||||
bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) & |
||||
~RGB_FMT_EN); |
||||
#endif |
||||
|
||||
} |
||||
|
||||
#define DEB2_URGENT 0x2000 /* DEB2 Urgent */ |
||||
|
||||
void Init_DMA(void *dst) |
||||
{ |
||||
|
||||
#if defined(CONFIG_DEB_DMA_URGENT) |
||||
*pEBIU_DDRQUE |= DEB2_URGENT; |
||||
#endif |
||||
|
||||
*pDMA12_START_ADDR = dst; |
||||
|
||||
/* X count */ |
||||
*pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE; |
||||
*pDMA12_X_MODIFY = DMA_BUS_SIZE / 8; |
||||
|
||||
/* Y count */ |
||||
*pDMA12_Y_COUNT = LCD_Y_RES; |
||||
*pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8; |
||||
|
||||
/* DMA Config */ |
||||
*pDMA12_CONFIG = |
||||
WDSIZE_32 | /* 32 bit DMA */ |
||||
DMA2D | /* 2D DMA */ |
||||
FLOW_AUTO; /* autobuffer mode */ |
||||
} |
||||
|
||||
void Init_Ports(void) |
||||
{ |
||||
*pPORTF_MUX = 0x00000000; |
||||
*pPORTF_FER |= 0xFFFF; /* PPI0..15 */ |
||||
|
||||
*pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); |
||||
*pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ |
||||
|
||||
#if !defined(CONFIG_VIDEO_RGB666) |
||||
*pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); |
||||
*pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); |
||||
*pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ |
||||
#endif |
||||
|
||||
*pPORTE_FER &= ~PE3; /* DISP */ |
||||
*pPORTE_DIR_SET = PE3; |
||||
*pPORTE_SET = PE3; |
||||
|
||||
} |
||||
|
||||
void EnableDMA(void) |
||||
{ |
||||
*pDMA12_CONFIG |= DMAEN; |
||||
} |
||||
|
||||
void DisableDMA(void) |
||||
{ |
||||
*pDMA12_CONFIG &= ~DMAEN; |
||||
} |
||||
|
||||
/* enable and disable PPI functions */ |
||||
void EnablePPI(void) |
||||
{ |
||||
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN); |
||||
} |
||||
|
||||
void DisablePPI(void) |
||||
{ |
||||
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN); |
||||
} |
||||
|
||||
int video_init(void *dst) |
||||
{ |
||||
Init_Ports(); |
||||
Init_DMA(dst); |
||||
EnableDMA(); |
||||
Init_PPI(); |
||||
EnablePPI(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) |
||||
{ |
||||
if (dcache_status()) |
||||
blackfin_dcache_flush_range(logo->data, logo->data + logo->size); |
||||
|
||||
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
||||
|
||||
/* Setup destination start address */ |
||||
bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE) |
||||
+ (y * LCD_X_RES * LCD_PIXEL_SIZE)); |
||||
/* Setup destination xcount */ |
||||
bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); |
||||
/* Setup destination xmodify */ |
||||
bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16); |
||||
|
||||
/* Setup destination ycount */ |
||||
bfin_write_MDMA_D0_Y_COUNT(logo->height); |
||||
/* Setup destination ymodify */ |
||||
bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16); |
||||
|
||||
|
||||
/* Setup Source start address */ |
||||
bfin_write_MDMA_S0_START_ADDR(logo->data); |
||||
/* Setup Source xcount */ |
||||
bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); |
||||
/* Setup Source xmodify */ |
||||
bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16); |
||||
|
||||
/* Setup Source ycount */ |
||||
bfin_write_MDMA_S0_Y_COUNT(logo->height); |
||||
/* Setup Source ymodify */ |
||||
bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16); |
||||
|
||||
|
||||
/* Enable source DMA */ |
||||
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D); |
||||
SSYNC(); |
||||
bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D); |
||||
|
||||
while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN); |
||||
|
||||
bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR); |
||||
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR); |
||||
|
||||
} |
||||
|
||||
void video_putc(const char c) |
||||
{ |
||||
} |
||||
|
||||
void video_puts(const char *s) |
||||
{ |
||||
} |
||||
|
||||
int drv_video_init(void) |
||||
{ |
||||
int error, devices = 1; |
||||
device_t videodev; |
||||
|
||||
u8 *dst; |
||||
u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET; |
||||
|
||||
dst = malloc(fbmem_size); |
||||
|
||||
if (dst == NULL) { |
||||
printf("Failed to alloc FB memory\n"); |
||||
return -1; |
||||
} |
||||
|
||||
#ifdef EASYLOGO_ENABLE_GZIP |
||||
unsigned char *data = EASYLOGO_DECOMP_BUFFER; |
||||
unsigned long src_len = EASYLOGO_ENABLE_GZIP; |
||||
if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { |
||||
puts("Failed to decompress logo\n"); |
||||
free(dst); |
||||
return -1; |
||||
} |
||||
bfin_logo.data = data; |
||||
#endif |
||||
|
||||
memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); |
||||
|
||||
dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo, |
||||
(LCD_X_RES - bfin_logo.width) / 2, |
||||
(LCD_Y_RES - bfin_logo.height) / 2); |
||||
|
||||
video_init(dst); /* Video initialization */ |
||||
|
||||
memset(&videodev, 0, sizeof(videodev)); |
||||
|
||||
strcpy(videodev.name, "video"); |
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ |
||||
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ |
||||
videodev.putc = video_putc; /* 'putc' function */ |
||||
videodev.puts = video_puts; /* 'puts' function */ |
||||
|
||||
error = device_register(&videodev); |
||||
|
||||
return (error == 0) ? devices : error; |
||||
} |
||||
@ -0,0 +1,147 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF518F EZBrd board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BF518F_EZBRD_H__ |
||||
#define __CONFIG_BF518F_EZBRD_H__ |
||||
|
||||
#include <asm/blackfin-config-pre.h> |
||||
|
||||
|
||||
/*
|
||||
* Processor Settings |
||||
*/ |
||||
#define CONFIG_BFIN_CPU bf518-0.0 |
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
||||
|
||||
|
||||
/*
|
||||
* Clock Settings |
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||
*/ |
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 25000000 |
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||
/* 1 = CLKIN / 2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||
/* 1 = bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||
/* Values can range from 0-63 (where 0 means 64) */ |
||||
#define CONFIG_VCO_MULT 16 |
||||
/* CCLK_DIV controls the core clock divider */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* SCLK_DIV controls the system clock divider */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 5 |
||||
|
||||
|
||||
/*
|
||||
* Memory Settings |
||||
*/ |
||||
/* This board has a 64meg MT48H32M16 */ |
||||
#define CONFIG_MEM_ADD_WDTH 10 |
||||
#define CONFIG_MEM_SIZE 64 |
||||
|
||||
#define CONFIG_EBIU_SDRRC_VAL 0x0096 |
||||
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) |
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) |
||||
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) |
||||
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (384 * 1024) |
||||
|
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) |
||||
#define ADI_CMDS_NETWORK 1 |
||||
#define CONFIG_BFIN_MAC |
||||
#define CONFIG_NETCONSOLE 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
#define CONFIG_HOSTNAME bf518f-ezbrd |
||||
#define CONFIG_PHY_ADDR 3 |
||||
/* Uncomment next line to use fixed MAC address */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||
|
||||
|
||||
/*
|
||||
* Flash Settings |
||||
*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000 |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 |
||||
|
||||
|
||||
/*
|
||||
* SPI Settings |
||||
*/ |
||||
#define CONFIG_BFIN_SPI |
||||
#define CONFIG_ENV_SPI_MAX_HZ 30000000 |
||||
#define CONFIG_SF_DEFAULT_HZ 30000000 |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x10000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#endif |
||||
#define ENV_IS_EMBEDDED_CUSTOM |
||||
|
||||
|
||||
/*
|
||||
* I2C Settings |
||||
*/ |
||||
#define CONFIG_BFIN_TWI_I2C 1 |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0 |
||||
|
||||
|
||||
/*
|
||||
* SDH Settings |
||||
*/ |
||||
#if !defined(__ADSPBF512__) |
||||
#define CONFIG_MMC |
||||
#define CONFIG_BFIN_SDH |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Misc Settings |
||||
*/ |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_RTC_BFIN |
||||
#define CONFIG_UART_CONSOLE 0 |
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup |
||||
*/ |
||||
#include <configs/bfin_adi_common.h> |
||||
|
||||
#include <asm/blackfin-config-post.h> |
||||
|
||||
#endif |
||||
@ -0,0 +1,190 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF526 EZBrd board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BF526_EZBRD_H__ |
||||
#define __CONFIG_BF526_EZBRD_H__ |
||||
|
||||
#include <asm/blackfin-config-pre.h> |
||||
|
||||
|
||||
/*
|
||||
* Processor Settings |
||||
*/ |
||||
#define CONFIG_BFIN_CPU bf526-0.0 |
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
||||
|
||||
|
||||
/*
|
||||
* Clock Settings |
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||
*/ |
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 25000000 |
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||
/* 1 = CLKIN / 2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||
/* 1 = bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||
/* Values can range from 0-63 (where 0 means 64) */ |
||||
#define CONFIG_VCO_MULT 16 |
||||
/* CCLK_DIV controls the core clock divider */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* SCLK_DIV controls the system clock divider */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 5 |
||||
|
||||
|
||||
/*
|
||||
* Memory Settings |
||||
*/ |
||||
/* This board has a 64meg MT48H32M16 */ |
||||
#define CONFIG_MEM_ADD_WDTH 10 |
||||
#define CONFIG_MEM_SIZE 64 |
||||
|
||||
#define CONFIG_EBIU_SDRRC_VAL 0x0267 |
||||
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS) |
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) |
||||
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) |
||||
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
||||
|
||||
|
||||
/*
|
||||
* NAND Settings |
||||
* (can't be used same time as ethernet) |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
||||
#define CONFIG_BFIN_NFC |
||||
#endif |
||||
#ifdef CONFIG_BFIN_NFC |
||||
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 |
||||
#define CONFIG_DRIVER_NAND_BFIN |
||||
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CONFIG_CMD_NAND |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ |
||||
!defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) |
||||
#define ADI_CMDS_NETWORK 1 |
||||
#define CONFIG_BFIN_MAC |
||||
#define CONFIG_RMII |
||||
#define CONFIG_NETCONSOLE 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
#define CONFIG_HOSTNAME bf526-ezbrd |
||||
/* Uncomment next line to use fixed MAC address */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||
|
||||
|
||||
/*
|
||||
* Flash Settings |
||||
*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000 |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 |
||||
|
||||
|
||||
/*
|
||||
* SPI Settings |
||||
*/ |
||||
#define CONFIG_BFIN_SPI |
||||
#define CONFIG_ENV_SPI_MAX_HZ 30000000 |
||||
#define CONFIG_SF_DEFAULT_HZ 30000000 |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_SST |
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#endif |
||||
#define ENV_IS_EMBEDDED_CUSTOM |
||||
|
||||
|
||||
/*
|
||||
* I2C Settings |
||||
*/ |
||||
#define CONFIG_BFIN_TWI_I2C 1 |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0 |
||||
|
||||
|
||||
/*
|
||||
* USB Settings |
||||
*/ |
||||
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) |
||||
#define CONFIG_USB |
||||
#define CONFIG_MUSB_HCD |
||||
#define CONFIG_USB_BLACKFIN |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_MUSB_TIMEOUT 100000 |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Misc Settings |
||||
*/ |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_RTC_BFIN |
||||
#define CONFIG_UART_CONSOLE 1 |
||||
|
||||
/* define to enable run status via led */ |
||||
/* #define CONFIG_STATUS_LED */ |
||||
#ifdef CONFIG_STATUS_LED |
||||
#define CONFIG_BOARD_SPECIFIC_LED |
||||
#ifndef __ASSEMBLY__ |
||||
typedef unsigned int led_id_t; |
||||
void __led_init(led_id_t mask, int state); |
||||
void __led_set(led_id_t mask, int state); |
||||
void __led_toggle(led_id_t mask); |
||||
#endif |
||||
/* use LED0 to indicate booting/alive */ |
||||
#define STATUS_LED_BOOT 0 |
||||
#define STATUS_LED_BIT 1 |
||||
#define STATUS_LED_STATE STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) |
||||
/* use LED1 to indicate crash */ |
||||
#define STATUS_LED_CRASH 1 |
||||
#define STATUS_LED_BIT1 2 |
||||
#define STATUS_LED_STATE1 STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup |
||||
*/ |
||||
#include <configs/bfin_adi_common.h> |
||||
|
||||
#include <asm/blackfin-config-post.h> |
||||
|
||||
#endif |
||||
@ -0,0 +1,172 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF537 STAMP board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BF527_EZKIT_H__ |
||||
#define __CONFIG_BF527_EZKIT_H__ |
||||
|
||||
#include <asm/blackfin-config-pre.h> |
||||
|
||||
|
||||
/*
|
||||
* Processor Settings |
||||
*/ |
||||
#define CONFIG_BFIN_CPU bf527-0.0 |
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
||||
|
||||
|
||||
/*
|
||||
* Clock Settings |
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||
*/ |
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 25000000 |
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||
/* 1 = CLKIN / 2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||
/* 1 = bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||
/* Values can range from 0-63 (where 0 means 64) */ |
||||
#define CONFIG_VCO_MULT 21 |
||||
/* CCLK_DIV controls the core clock divider */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* SCLK_DIV controls the system clock divider */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 4 |
||||
|
||||
|
||||
/*
|
||||
* Memory Settings |
||||
*/ |
||||
#define CONFIG_MEM_ADD_WDTH 10 |
||||
#define CONFIG_MEM_SIZE 64 |
||||
|
||||
#define CONFIG_EBIU_SDRRC_VAL 0x03F6 |
||||
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) |
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) |
||||
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) |
||||
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (640 * 1024) |
||||
|
||||
|
||||
/*
|
||||
* NAND Settings |
||||
* (can't be used same time as ethernet) |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
||||
#define CONFIG_BFIN_NFC |
||||
#endif |
||||
#ifdef CONFIG_BFIN_NFC |
||||
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 |
||||
#define CONFIG_DRIVER_NAND_BFIN |
||||
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CONFIG_CMD_NAND |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ |
||||
!defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) |
||||
#define ADI_CMDS_NETWORK 1 |
||||
#define CONFIG_BFIN_MAC |
||||
#define CONFIG_RMII |
||||
#define CONFIG_NETCONSOLE 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
#define CONFIG_HOSTNAME bf527-ezkit |
||||
/* Uncomment next line to use fixed MAC address */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||
|
||||
|
||||
/*
|
||||
* Flash Settings |
||||
*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000 |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 259 |
||||
|
||||
|
||||
/*
|
||||
* SPI Settings |
||||
*/ |
||||
#define CONFIG_BFIN_SPI |
||||
#define CONFIG_ENV_SPI_MAX_HZ 30000000 |
||||
#define CONFIG_SF_DEFAULT_HZ 30000000 |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#endif |
||||
#define ENV_IS_EMBEDDED_CUSTOM |
||||
|
||||
|
||||
/*
|
||||
* I2C Settings |
||||
*/ |
||||
#define CONFIG_BFIN_TWI_I2C 1 |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0 |
||||
|
||||
|
||||
/*
|
||||
* USB Settings |
||||
*/ |
||||
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) |
||||
#define CONFIG_USB |
||||
#define CONFIG_MUSB_HCD |
||||
#define CONFIG_USB_BLACKFIN |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_MUSB_TIMEOUT 100000 |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Misc Settings |
||||
*/ |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_RTC_BFIN |
||||
#define CONFIG_UART_CONSOLE 1 |
||||
|
||||
/* Don't waste time transferring a logo over the UART */ |
||||
#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) |
||||
# define CONFIG_VIDEO |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup |
||||
*/ |
||||
#include <configs/bfin_adi_common.h> |
||||
|
||||
#include <asm/blackfin-config-post.h> |
||||
|
||||
#endif |
||||
@ -0,0 +1,139 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF538F EZ-Kit Lite board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BF538F_EZKIT_H__ |
||||
#define __CONFIG_BF538F_EZKIT_H__ |
||||
|
||||
#include <asm/blackfin-config-pre.h> |
||||
|
||||
|
||||
/*
|
||||
* Processor Settings |
||||
*/ |
||||
#define CONFIG_BFIN_CPU bf538-0.4 |
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
||||
|
||||
|
||||
/*
|
||||
* Clock Settings |
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||
*/ |
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 25000000 |
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||
/* 1 = CLKIN / 2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||
/* 1 = bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||
/* Values can range from 0-63 (where 0 means 64) */ |
||||
#define CONFIG_VCO_MULT 21 |
||||
/* CCLK_DIV controls the core clock divider */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* SCLK_DIV controls the system clock divider */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 4 |
||||
|
||||
|
||||
/*
|
||||
* Memory Settings |
||||
*/ |
||||
#define CONFIG_MEM_ADD_WDTH 10 |
||||
#define CONFIG_MEM_SIZE 64 |
||||
|
||||
#define CONFIG_EBIU_SDRRC_VAL (0x03F6) |
||||
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3) |
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN) |
||||
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) |
||||
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (384 * 1024) |
||||
|
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
#define ADI_CMDS_NETWORK 1 |
||||
#define CONFIG_DRIVER_SMC91111 1 |
||||
#define CONFIG_SMC91111_BASE 0x20310300 |
||||
#define CONFIG_HOSTNAME bf538f-ezkit |
||||
/* Uncomment next line to use fixed MAC address */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||
|
||||
|
||||
/*
|
||||
* Flash Settings |
||||
*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000 |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 |
||||
|
||||
|
||||
/*
|
||||
* SPI Settings |
||||
*/ |
||||
#define CONFIG_BFIN_SPI |
||||
#define CONFIG_ENV_SPI_MAX_HZ 30000000 |
||||
#define CONFIG_SF_DEFAULT_HZ 30000000 |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_ATMEL |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_SPI_FLASH_WINBOND |
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#endif |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
||||
#define ENV_IS_EMBEDDED |
||||
#else |
||||
#define ENV_IS_EMBEDDED_CUSTOM |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* I2C Settings |
||||
*/ |
||||
#define CONFIG_BFIN_TWI_I2C 1 |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0 |
||||
|
||||
|
||||
/*
|
||||
* Misc Settings |
||||
*/ |
||||
#define CONFIG_RTC_BFIN |
||||
#define CONFIG_UART_CONSOLE 0 |
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup |
||||
*/ |
||||
#include <configs/bfin_adi_common.h> |
||||
|
||||
#include <asm/blackfin-config-post.h> |
||||
|
||||
#endif |
||||
@ -0,0 +1,211 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF548 STAMP board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BF548_EZKIT_H__ |
||||
#define __CONFIG_BF548_EZKIT_H__ |
||||
|
||||
#include <asm/blackfin-config-pre.h> |
||||
|
||||
|
||||
/*
|
||||
* Processor Settings |
||||
*/ |
||||
#define CONFIG_BFIN_CPU bf548-0.0 |
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
||||
|
||||
|
||||
/*
|
||||
* Clock Settings |
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||
*/ |
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 25000000 |
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||
/* 1 = CLKIN / 2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||
/* 1 = bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||
/* Values can range from 0-63 (where 0 means 64) */ |
||||
#define CONFIG_VCO_MULT 21 |
||||
/* CCLK_DIV controls the core clock divider */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* SCLK_DIV controls the system clock divider */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 4 |
||||
|
||||
|
||||
/*
|
||||
* Memory Settings |
||||
*/ |
||||
#define CONFIG_MEM_ADD_WDTH 10 |
||||
#define CONFIG_MEM_SIZE 64 |
||||
|
||||
#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE |
||||
#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 |
||||
#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 |
||||
|
||||
/* Default EZ-Kit bank mapping:
|
||||
* Async Bank 0 - 32MB Burst Flash |
||||
* Async Bank 1 - Ethernet |
||||
* Async Bank 2 - Nothing |
||||
* Async Bank 3 - Nothing |
||||
*/ |
||||
#define CONFIG_EBIU_AMGCTL_VAL 0xFF |
||||
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 |
||||
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 |
||||
#define CONFIG_EBIU_FCTL_VAL (BCLK_4) |
||||
#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (768 * 1024) |
||||
|
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
#define ADI_CMDS_NETWORK 1 |
||||
#define CONFIG_DRIVER_SMC911X 1 |
||||
#define CONFIG_DRIVER_SMC911X_BASE 0x24000000 |
||||
#define CONFIG_DRIVER_SMC911X_16_BIT |
||||
#define CONFIG_HOSTNAME bf548-ezkit |
||||
/* Uncomment next line to use fixed MAC address */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||
|
||||
|
||||
/*
|
||||
* Flash Settings |
||||
*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000 |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 259 |
||||
|
||||
|
||||
/*
|
||||
* SPI Settings |
||||
*/ |
||||
#define CONFIG_BFIN_SPI |
||||
#define CONFIG_ENV_SPI_MAX_HZ 30000000 |
||||
#define CONFIG_SF_DEFAULT_HZ 30000000 |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x10000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#define ENV_IS_EMBEDDED_CUSTOM |
||||
#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
||||
#define CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_OFFSET 0x40000 |
||||
#define CONFIG_ENV_SIZE 0x20000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_ADDR 0x20002000 |
||||
#define CONFIG_ENV_OFFSET 0x2000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
||||
#define ENV_IS_EMBEDDED_CUSTOM |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* NAND Settings |
||||
*/ |
||||
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
||||
# define CONFIG_BFIN_NFC_BOOTROM_ECC |
||||
#endif |
||||
#define CONFIG_DRIVER_NAND_BFIN |
||||
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CONFIG_CMD_NAND |
||||
|
||||
|
||||
/*
|
||||
* I2C Settings |
||||
*/ |
||||
#define CONFIG_BFIN_TWI_I2C 1 |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0 |
||||
|
||||
|
||||
/*
|
||||
* SATA |
||||
*/ |
||||
#if !defined(__ADSPBF544__) |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1 |
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_PATA_BFIN |
||||
#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800 |
||||
#define CONFIG_BFIN_ATA_MODE XFER_PIO_4 |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* SDH Settings |
||||
*/ |
||||
#if !defined(__ADSPBF544__) |
||||
#define CONFIG_MMC |
||||
#define CONFIG_BFIN_SDH |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* USB Settings |
||||
*/ |
||||
#if !defined(__ADSPBF544__) |
||||
#define CONFIG_USB |
||||
#define CONFIG_MUSB_HCD |
||||
#define CONFIG_USB_BLACKFIN |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_MUSB_TIMEOUT 100000 |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Misc Settings |
||||
*/ |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_RTC_BFIN |
||||
#define CONFIG_UART_CONSOLE 1 |
||||
|
||||
#ifndef __ADSPBF542__ |
||||
/* Don't waste time transferring a logo over the UART */ |
||||
# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) |
||||
# define CONFIG_VIDEO |
||||
# endif |
||||
# define CONFIG_DEB_DMA_URGENT |
||||
#endif |
||||
|
||||
/* Define if want to do post memory test */ |
||||
#undef CONFIG_POST |
||||
#ifdef CONFIG_POST |
||||
#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ |
||||
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup |
||||
*/ |
||||
#include <configs/bfin_adi_common.h> |
||||
|
||||
#include <asm/blackfin-config-post.h> |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue