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@ -42,17 +42,10 @@ |
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
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#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
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#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ |
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#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */ |
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#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ |
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/* (it will be used if there is no */ |
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/* 'cpuclk' variable with valid value) */ |
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#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */ |
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/* (function measure_gclk() */ |
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/* will be called) */ |
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#ifdef CFG_MEASURE_CPUCLK |
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#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ |
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#endif |
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
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#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
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@ -83,9 +76,15 @@ |
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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"bootfile=/tftpboot/TQM866M/uImage\0" \
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"kernel_addr=40080000\0" \
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"ramdisk_addr=40180000\0" \
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"bootfile=/tftpboot/TQM885D/uImage\0" \
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"fdt_addr=400C0000\0" \
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"kernel_addr=40100000\0" \
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"ramdisk_addr=40280000\0" \
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"load=tftp 200000 ${u-boot}\0" \
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"update=protect off 40000000 +${filesize};" \
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"erase 40000000 +${filesize};" \
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"cp.b 200000 40000000 ${filesize};" \
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"protect on 40000000 +${filesize}\0" \
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"" |
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#define CONFIG_BOOTCOMMAND "run flash_self" |
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@ -144,7 +143,7 @@ |
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#define CONFIG_MAC_PARTITION |
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#define CONFIG_DOS_PARTITION |
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#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ |
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#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ |
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#define CONFIG_TIMESTAMP /* but print image timestmps */ |
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@ -230,7 +229,7 @@ |
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#define CFG_FLASH_BASE 0x40000000 |
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
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#define CFG_MONITOR_BASE CFG_FLASH_BASE |
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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@ -242,16 +241,20 @@ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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/* use CFI flash driver */ |
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#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
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#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
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#define CFG_FLASH_EMPTY_INFO |
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#define CFG_FLASH_USE_BUFFER_WRITE 1 |
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
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#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ |
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#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ |
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#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ |
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#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ |
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/* Address and size of Redundant Environment Sector */ |
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) |
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@ -434,26 +437,30 @@ |
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#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
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/*
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* Memory Periodic Timer Prescaler |
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* Periodic timer for refresh, start with refresh rate for 40 MHz clock |
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* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) |
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* Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
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* |
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* CPUclock(MHz) * 31.2 |
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* CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
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* 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
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* |
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* CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us |
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* CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us |
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* CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us |
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* CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us |
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* |
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* Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will |
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* be met also in the default configuration, i.e. if environment variable |
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* 'cpuclk' is not set. |
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*/ |
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#define CFG_MAMR_PTA 39 |
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#define CFG_MAMR_PTA 128 |
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/*
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* For 16 MBit, refresh rates could be 31.3 us |
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* (= 64 ms / 2K = 125 / quad bursts). |
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* For a simpler initialization, 15.6 us is used instead. |
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* |
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* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
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* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
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* Memory Periodic Timer Prescaler Register (MPTPR) values. |
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*/ |
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
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/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
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/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
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/*
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* MAMR settings for SDRAM |
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Wolfgang Denk
18 years ago