Also adds helper functions for DDR1/2 to verify the checksum. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>master
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285db74716
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/*
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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*/ |
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#include <common.h> |
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#include <ddr_spd.h> |
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/* used for ddr1 and ddr2 spd */ |
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static int |
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spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum) |
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{ |
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unsigned int cksum = 0; |
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unsigned int i; |
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/*
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* Check SPD revision supported |
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* Rev 1.2 or less supported by this code |
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*/ |
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if (spd_rev > 0x12) { |
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printf("SPD revision %02X not supported by this code\n", |
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spd_rev); |
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return 1; |
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} |
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/*
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* Calculate checksum |
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*/ |
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for (i = 0; i < 63; i++) { |
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cksum += *buf++; |
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} |
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cksum &= 0xFF; |
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if (cksum != spd_cksum) { |
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printf("SPD checksum unexpected. " |
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"Checksum in SPD = %02X, computed SPD = %02X\n", |
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spd_cksum, cksum); |
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return 1; |
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} |
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return 0; |
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} |
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unsigned int |
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ddr1_spd_check(const ddr1_spd_eeprom_t *spd) |
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{ |
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const u8 *p = (const u8 *)spd; |
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return spd_check(p, spd->spd_rev, spd->cksum); |
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} |
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unsigned int |
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ddr2_spd_check(const ddr2_spd_eeprom_t *spd) |
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{ |
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const u8 *p = (const u8 *)spd; |
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return spd_check(p, spd->spd_rev, spd->cksum); |
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} |
@ -0,0 +1,292 @@ |
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/*
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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*/ |
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#ifndef _DDR_SPD_H_ |
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#define _DDR_SPD_H_ |
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/*
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* Format from "JEDEC Standard No. 21-C, |
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* Appendix D: Rev 1.0: SPD's for DDR SDRAM |
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*/ |
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typedef struct ddr1_spd_eeprom_s { |
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unsigned char info_size; /* 0 # bytes written into serial memory */ |
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unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ |
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unsigned char mem_type; /* 2 Fundamental memory type */ |
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unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ |
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unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ |
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unsigned char nrows; /* 5 Number of DIMM Banks */ |
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unsigned char dataw_lsb; /* 6 Data Width of this assembly */ |
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unsigned char dataw_msb; /* 7 ... Data Width continuation */ |
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unsigned char voltage; /* 8 Voltage intf std of this assembly */ |
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unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ |
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unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ |
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unsigned char config; /* 11 DIMM Configuration type */ |
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unsigned char refresh; /* 12 Refresh Rate/Type */ |
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unsigned char primw; /* 13 Primary SDRAM Width */ |
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unsigned char ecw; /* 14 Error Checking SDRAM width */ |
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unsigned char min_delay; /* 15 for Back to Back Random Address */ |
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unsigned char burstl; /* 16 Burst Lengths Supported */ |
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unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ |
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unsigned char cas_lat; /* 18 CAS# Latencies Supported */ |
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unsigned char cs_lat; /* 19 CS# Latency */ |
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unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ |
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unsigned char mod_attr; /* 21 SDRAM Module Attributes */ |
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unsigned char dev_attr; /* 22 SDRAM Device Attributes */ |
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unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ |
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unsigned char clk_access2; /* 24 SDRAM Access from
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Clk @ CL=X-0.5 (tAC) */ |
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unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ |
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unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ |
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unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ |
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unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ |
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unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ |
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unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ |
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unsigned char bank_dens; /* 31 Density of each bank on module */ |
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unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */ |
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unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */ |
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unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ |
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unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ |
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unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ |
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unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ |
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unsigned char trfc; /* 42 Min Auto to Active period tRFC */ |
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unsigned char tckmax; /* 43 Max device cycle time tCKmax */ |
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unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ |
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unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ |
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unsigned char res_46; /* 46 Reserved */ |
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unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ |
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unsigned char res_48_61[14]; /* 48-61 Reserved */ |
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unsigned char spd_rev; /* 62 SPD Data Revision Code */ |
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unsigned char cksum; /* 63 Checksum for bytes 0-62 */ |
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unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ |
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unsigned char mloc; /* 72 Manufacturing Location */ |
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unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ |
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unsigned char rev[2]; /* 91 Revision Code */ |
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unsigned char mdate[2]; /* 93 Manufacturing Date */ |
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unsigned char sernum[4]; /* 95 Assembly Serial Number */ |
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unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ |
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} ddr1_spd_eeprom_t; |
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/*
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* Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", |
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* SPD Revision 1.2 |
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*/ |
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typedef struct ddr2_spd_eeprom_s { |
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unsigned char info_size; /* 0 # bytes written into serial memory */ |
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unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ |
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unsigned char mem_type; /* 2 Fundamental memory type */ |
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unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ |
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unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ |
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unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ |
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unsigned char dataw; /* 6 Module Data Width */ |
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unsigned char res_7; /* 7 Reserved */ |
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unsigned char voltage; /* 8 Voltage intf std of this assembly */ |
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unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ |
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unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ |
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unsigned char config; /* 11 DIMM Configuration type */ |
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unsigned char refresh; /* 12 Refresh Rate/Type */ |
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unsigned char primw; /* 13 Primary SDRAM Width */ |
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unsigned char ecw; /* 14 Error Checking SDRAM width */ |
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unsigned char res_15; /* 15 Reserved */ |
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unsigned char burstl; /* 16 Burst Lengths Supported */ |
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unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ |
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unsigned char cas_lat; /* 18 CAS# Latencies Supported */ |
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unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ |
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unsigned char dimm_type; /* 20 DIMM type information */ |
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unsigned char mod_attr; /* 21 SDRAM Module Attributes */ |
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unsigned char dev_attr; /* 22 SDRAM Device Attributes */ |
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unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ |
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unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ |
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unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ |
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unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ |
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unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ |
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unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ |
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unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ |
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unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ |
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unsigned char rank_dens; /* 31 Density of each rank on module */ |
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unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ |
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unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ |
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unsigned char data_setup; /* 34 Data Input Setup Time
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Before Strobe (tDS) */ |
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unsigned char data_hold; /* 35 Data Input Hold Time
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After Strobe (tDH) */ |
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unsigned char twr; /* 36 Write Recovery time tWR */ |
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unsigned char twtr; /* 37 Int write to read delay tWTR */ |
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unsigned char trtp; /* 38 Int read to precharge delay tRTP */ |
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unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ |
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unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ |
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unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ |
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unsigned char trfc; /* 42 Min Auto to Active period tRFC */ |
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unsigned char tckmax; /* 43 Max device cycle time tCKmax */ |
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unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ |
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unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ |
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unsigned char pll_relock; /* 46 PLL Relock time */ |
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unsigned char Tcasemax; /* 47 Tcasemax */ |
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unsigned char psiTAdram; /* 48 Thermal Resistance of DRAM Package from
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Top (Case) to Ambient (Psi T-A DRAM) */ |
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unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient
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due to Activate-Precharge/Mode Bits |
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(DT0/Mode Bits) */ |
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unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient
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due to Precharge/Quiet Standby |
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(DT2N/DT2Q) */ |
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unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient
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due to Precharge Power-Down (DT2P) */ |
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unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient
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due to Active Standby (DT3N) */ |
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unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient
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due to Active Power-Down with |
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Fast PDN Exit (DT3Pfast) */ |
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unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient
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due to Active Power-Down with Slow |
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PDN Exit (DT3Pslow) */ |
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unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
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due to Page Open Burst Read/DT4R4W |
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Mode Bit (DT4R/DT4R4W Mode Bit) */ |
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unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient
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due to Burst Refresh (DT5B) */ |
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unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient
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due to Bank Interleave Reads with |
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Auto-Precharge (DT7) */ |
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unsigned char psiTApll; /* 58 Thermal Resistance of PLL Package form
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Top (Case) to Ambient (Psi T-A PLL) */ |
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unsigned char psiTAreg; /* 59 Thermal Reisitance of Register Package
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from Top (Case) to Ambient |
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(Psi T-A Register) */ |
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unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
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due to PLL Active (DT PLL Active) */ |
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unsigned char dtregact; /* 61 Register Case Temperature Rise from
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Ambient due to Register Active/Mode Bit |
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(DT Register Active/Mode Bit) */ |
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unsigned char spd_rev; /* 62 SPD Data Revision Code */ |
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unsigned char cksum; /* 63 Checksum for bytes 0-62 */ |
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unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ |
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unsigned char mloc; /* 72 Manufacturing Location */ |
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unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ |
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unsigned char rev[2]; /* 91 Revision Code */ |
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unsigned char mdate[2]; /* 93 Manufacturing Date */ |
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unsigned char sernum[4]; /* 95 Assembly Serial Number */ |
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unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ |
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} ddr2_spd_eeprom_t; |
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typedef struct ddr3_spd_eeprom_s { |
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/* General Section: Bytes 0-59 */ |
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unsigned char info_size_crc; /* 0 # bytes written into serial memory,
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CRC coverage */ |
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unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */ |
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unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */ |
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unsigned char module_type; /* 3 Key Byte / Module Type */ |
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unsigned char density_banks; /* 4 SDRAM Density and Banks */ |
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unsigned char addressing; /* 5 SDRAM Addressing */ |
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unsigned char res_6; /* 6 Reserved */ |
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unsigned char organization; /* 7 Module Organization */ |
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unsigned char bus_width; /* 8 Module Memory Bus Width */ |
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unsigned char ftb_div; /* 9 Fine Timebase (FTB)
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Dividend / Divisor */ |
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unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ |
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unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ |
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unsigned char tCK_min; /* 12 SDRAM Minimum Cycle Time */ |
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unsigned char res_13; /* 13 Reserved */ |
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unsigned char caslat_lsb; /* 14 CAS Latencies Supported,
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Least Significant Byte */ |
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unsigned char caslat_msb; /* 15 CAS Latencies Supported,
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Most Significant Byte */ |
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unsigned char tAA_min; /* 16 Min CAS Latency Time */ |
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unsigned char tWR_min; /* 17 Min Write REcovery Time */ |
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unsigned char tRCD_min; /* 18 Min RAS# to CAS# Delay Time */ |
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unsigned char tRRD_min; /* 19 Min Row Active to
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Row Active Delay Time */ |
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unsigned char tRP_min; /* 20 Min Row Precharge Delay Time */ |
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unsigned char tRAS_tRC_ext; /* 21 Upper Nibbles for tRAS and tRC */ |
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unsigned char tRAS_min_lsb; /* 22 Min Active to Precharge
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Delay Time */ |
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unsigned char tRC_min_lsb; /* 23 Min Active to Active/Refresh
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Delay Time, LSB */ |
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unsigned char tRFC_min_lsb; /* 24 Min Refresh Recovery Delay Time */ |
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unsigned char tRFC_min_msb; /* 25 Min Refresh Recovery Delay Time */ |
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unsigned char tWTR_min; /* 26 Min Internal Write to
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Read Command Delay Time */ |
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unsigned char tRTP_min; /* 27 Min Internal Read to Precharge
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Command Delay Time */ |
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unsigned char tFAW_msb; /* 28 Upper Nibble for tFAW */ |
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unsigned char tFAW_min; /* 29 Min Four Activate Window
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Delay Time*/ |
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unsigned char opt_features; /* 30 SDRAM Optional Features */ |
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unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ |
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unsigned char res_32_59[28]; /* 32-59 Reserved, General Section */ |
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/* Module-Specific Section: Bytes 60-116 */ |
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union { |
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struct { |
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/* 60 (Unbuffered) Module Nominal Height */ |
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unsigned char mod_height; |
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/* 61 (Unbuffered) Module Maximum Thickness */ |
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unsigned char mod_thickness; |
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/* 62 (Unbuffered) Reference Raw Card Used */ |
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unsigned char ref_raw_card; |
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/* 63 (Unbuffered) Address Mapping from
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Edge Connector to DRAM */ |
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unsigned char addr_mapping; |
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/* 64-116 (Unbuffered) Reserved */ |
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unsigned char res_64_116[53]; |
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} unbuffered; |
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struct { |
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/* 60 (Registered) Module Nominal Height */ |
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unsigned char mod_height; |
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/* 61 (Registered) Module Maximum Thickness */ |
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unsigned char mod_thickness; |
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/* 62 (Registered) Reference Raw Card Used */ |
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unsigned char ref_raw_card; |
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} registered; |
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unsigned char uc[57]; /* 60-116 Module-Specific Section */ |
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} mod_section; |
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/* Unique Module ID: Bytes 117-125 */ |
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unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ |
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unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ |
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unsigned char mloc; /* 119 Mfg Location */ |
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unsigned char mdate[2]; /* 120-121 Mfg Date */ |
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unsigned char sernum[4]; /* 122-125 Module Serial Number */ |
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/* CRC: Bytes 126-127 */ |
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unsigned char crc[2]; /* 126-127 SPD CRC */ |
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/* Other Manufacturer Fields and User Space: Bytes 128-255 */ |
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unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */ |
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unsigned char mrev[2]; /* 146-147 Module Revision Code */ |
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unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ |
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unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ |
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unsigned char msd[26]; /* 150-175 Mfg's Specific Data */ |
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unsigned char cust[80]; /* 176-255 Open for Customer Use */ |
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} ddr3_spd_eeprom_t; |
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extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); |
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extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); |
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extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); |
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extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); |
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/*
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* Byte 2 Fundamental Memory Types. |
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*/ |
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#define SPD_MEMTYPE_FPM (0x01) |
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#define SPD_MEMTYPE_EDO (0x02) |
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#define SPD_MEMTYPE_PIPE_NIBBLE (0x03) |
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#define SPD_MEMTYPE_SDRAM (0x04) |
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#define SPD_MEMTYPE_ROM (0x05) |
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#define SPD_MEMTYPE_SGRAM (0x06) |
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#define SPD_MEMTYPE_DDR (0x07) |
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#define SPD_MEMTYPE_DDR2 (0x08) |
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#define SPD_MEMTYPE_DDR2_FBDIMM (0x09) |
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#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) |
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#define SPD_MEMTYPE_DDR3 (0x0B) |
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#endif /* _DDR_SPD_H_ */ |
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