ppc4xx: Add SDR0_SRST Mnemonics for the 405EX(r)

This patch adds bit field mnemonics for the 405EX(r) SDR0_SRST soft reset register.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>

include/ppc405.h

@@ -1254,6 +1254,42 @@
 #if defined(CONFIG_405EX)
 #define SDR0_SRST		0x0200
 
+/*
+ * Software Reset Register
+ */
+#define SDR0_SRST_BGO		PPC_REG_VAL(0, 1)
+#define SDR0_SRST_PLB4		PPC_REG_VAL(1, 1)
+#define SDR0_SRST_EBC		PPC_REG_VAL(2, 1)
+#define SDR0_SRST_OPB		PPC_REG_VAL(3, 1)
+#define SDR0_SRST_UART0		PPC_REG_VAL(4, 1)
+#define SDR0_SRST_UART1		PPC_REG_VAL(5, 1)
+#define SDR0_SRST_IIC0		PPC_REG_VAL(6, 1)
+#define SDR0_SRST_BGI		PPC_REG_VAL(7, 1)
+#define SDR0_SRST_GPIO		PPC_REG_VAL(8, 1)
+#define SDR0_SRST_GPT		PPC_REG_VAL(9, 1)
+#define SDR0_SRST_DMC		PPC_REG_VAL(10, 1)
+#define SDR0_SRST_RGMII		PPC_REG_VAL(11, 1)
+#define SDR0_SRST_EMAC0		PPC_REG_VAL(12, 1)
+#define SDR0_SRST_EMAC1		PPC_REG_VAL(13, 1)
+#define SDR0_SRST_CPM		PPC_REG_VAL(14, 1)
+#define SDR0_SRST_EPLL		PPC_REG_VAL(15, 1)
+#define SDR0_SRST_UIC		PPC_REG_VAL(16, 1)
+#define SDR0_SRST_UPRST		PPC_REG_VAL(17, 1)
+#define SDR0_SRST_IIC1		PPC_REG_VAL(18, 1)
+#define SDR0_SRST_SCP		PPC_REG_VAL(19, 1)
+#define SDR0_SRST_UHRST		PPC_REG_VAL(20, 1)
+#define SDR0_SRST_DMA		PPC_REG_VAL(21, 1)
+#define SDR0_SRST_DMAC		PPC_REG_VAL(22, 1)
+#define SDR0_SRST_MAL		PPC_REG_VAL(23, 1)
+#define SDR0_SRST_EBM		PPC_REG_VAL(24, 1)
+#define SDR0_SRST_GPTR		PPC_REG_VAL(25, 1)
+#define SDR0_SRST_PE0		PPC_REG_VAL(26, 1)
+#define SDR0_SRST_PE1		PPC_REG_VAL(27, 1)
+#define SDR0_SRST_CRYP		PPC_REG_VAL(28, 1)
+#define SDR0_SRST_PKP		PPC_REG_VAL(29, 1)
+#define SDR0_SRST_AHB		PPC_REG_VAL(30, 1)
+#define SDR0_SRST_NDFC		PPC_REG_VAL(31, 1)
+
 #define sdr_uart0	0x0120	/* UART0 Config */
 #define sdr_uart1	0x0121	/* UART1 Config */
 #define sdr_mfr		0x4300	/* SDR0_MFR reg */