diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 75e4317..b1a23b4 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -219,6 +219,11 @@ boot_warm:
 	sync
 #endif
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+	/* setup ccsrbar now while we're in real mode */
+	bl      setup_ccsrbar
+#endif
+
 	/*
 	 * Calculate absolute address in FLASH and jump there
 	 *------------------------------------------------------*/
@@ -281,10 +286,6 @@ in_flash:
 	bl      setup_bats
 	sync
 
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-	/* setup ccsrbar */
-	bl      setup_ccsrbar
-#endif
 
 	/* run low-level CPU init code	   (from Flash) */
 	bl	cpu_init_f
@@ -365,10 +366,28 @@ invalidate_bats:
  * early_bats:
  *
  * Set up bats needed early on - this is usually the BAT for the
- * stack-in-cache and the Flash
+ * stack-in-cache, the Flash, and CCSR space
  */
 	.globl  early_bats
 early_bats:
+	/* IBAT 3 */
+	lis	r4, CONFIG_SYS_IBAT3L@h
+	ori     r4, r4, CONFIG_SYS_IBAT3L@l
+	lis	r3, CONFIG_SYS_IBAT3U@h
+	ori     r3, r3, CONFIG_SYS_IBAT3U@l
+	mtspr   IBAT3L, r4
+	mtspr   IBAT3U, r3
+	isync
+
+	/* DBAT 3 */
+	lis	r4, CONFIG_SYS_DBAT3L@h
+	ori     r4, r4, CONFIG_SYS_DBAT3L@l
+	lis	r3, CONFIG_SYS_DBAT3U@h
+	ori     r3, r3, CONFIG_SYS_DBAT3U@l
+	mtspr   DBAT3L, r4
+	mtspr   DBAT3U, r3
+	isync
+
 	/* IBAT 5 */
 	lis	r4, CONFIG_SYS_IBAT5L@h
 	ori     r4, r4, CONFIG_SYS_IBAT5L@l
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 67b2764..6f04127 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -370,27 +370,29 @@
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 
 /*
- * BAT3		32M	Cache-inhibited, guarded
- * 0xe200_0000	1M	PCI-Express 2 I/O
- * 0xe300_0000	1M	PCI-Express 1 I/O
+ * BAT3		4M	Cache-inhibited, guarded
+ * 0xe000_0000	4M	CCSR
  */
 
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
 
 /*
- * BAT4		4M	Cache-inhibited, guarded
- * 0xe000_0000	4M	CCSR
+ * BAT4		32M	Cache-inhibited, guarded
+ * 0xe200_0000	1M	PCI-Express 2 I/O
+ * 0xe300_0000	1M	PCI-Express 1 I/O
  */
-#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
+
 /*
  * BAT5		128K	Cacheable, non-guarded
  * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)