Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options

Browse Source 
Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132
Kconfig options.

Also drop #ifdef in BSC9131RDB.h since it is redundant.

Signed-off-by: York Sun <york.sun@nxp.com>
master
York Sun 8 years ago
parent ae59dded8d
commit 115d60c0cf
8 changed files with 23 additions and 24 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 8
      arch/powerpc/cpu/mpc85xx/Kconfig
  2. 2
      arch/powerpc/cpu/mpc85xx/Makefile
  3. 4
      arch/powerpc/include/asm/config_mpc85xx.h
  4. 4
      arch/powerpc/include/asm/fsl_law.h
  5. 20
      arch/powerpc/include/asm/immap_85xx.h
  6. 3
      include/configs/BSC9131RDB.h
  7. 4
      include/configs/BSC9132QDS.h
  8. 2
      scripts/config_whitelist.txt

8
arch/powerpc/cpu/mpc85xx/Kconfig
Unescape View File

@ -23,10 +23,12 @@ config TARGET_B4860QDS
config TARGET_BSC9131RDB
bool "Support BSC9131RDB"
select ARCH_BSC9131
select SUPPORT_SPL
config TARGET_BSC9132QDS
bool "Support BSC9132QDS"
select ARCH_BSC9132
select SUPPORT_SPL
config TARGET_C29XPCIE
@ -177,6 +179,12 @@ config TARGET_CYRUS
endchoice
config ARCH_BSC9131
bool
config ARCH_BSC9132
bool
config ARCH_MPC8544
bool

2
arch/powerpc/cpu/mpc85xx/Makefile
Unescape View File

@ -96,7 +96,7 @@ obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
obj-$(CONFIG_PPC_T1020) += t1040_serdes.o

4
arch/powerpc/include/asm/config_mpc85xx.h
Unescape View File

@ -579,7 +579,7 @@
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_BSC9131)
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
@ -598,7 +598,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_BSC9132)
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3

4
arch/powerpc/include/asm/fsl_law.h
Unescape View File

@ -82,7 +82,7 @@ enum law_trgt_if {
#ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
@ -95,7 +95,7 @@ enum law_trgt_if {
LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
#if defined(CONFIG_BSC9132)
#if defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_CLASS_DSP = 0x0d,
#else
LAW_TRGT_IF_RIO_2 = 0x0d,

20
arch/powerpc/include/asm/immap_85xx.h
Unescape View File

@ -2129,7 +2129,7 @@ typedef struct ccsr_gur {
& MPC85xx_PORDEVSR2_DDR_SPD_0) \
>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
#else
#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
@ -2172,7 +2172,7 @@ typedef struct ccsr_gur {
#if defined(CONFIG_P1010)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#elif defined(CONFIG_BSC9132)
#elif defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
#elif defined(CONFIG_PPC_C29X)
@ -2296,7 +2296,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
#define MPC85xx_PMUXCR_SPI 0x00000000
#endif
#if defined(CONFIG_BSC9131)
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
@ -2340,7 +2340,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
#endif
#ifdef CONFIG_BSC9132
#ifdef CONFIG_ARCH_BSC9132
#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
#endif
@ -2379,8 +2379,8 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
#define MPC85xx_PMUXCR2_USB 0x00150000
#endif
#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
#if defined(CONFIG_BSC9131)
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
@ -2425,7 +2425,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
#endif
u32 pmuxcr3;
#if defined(CONFIG_BSC9131)
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
@ -2441,7 +2441,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
#endif
#ifdef CONFIG_BSC9132
#ifdef CONFIG_ARCH_BSC9132
#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
@ -2504,7 +2504,7 @@ typedef struct ccsr_gur {
u32 ddrdllcr; /* DDR DLL control */
u8 res14[12];
u32 lbcdllcr; /* LBC DLL control */
#if defined(CONFIG_BSC9131)
#if defined(CONFIG_ARCH_BSC9131)
u8 res15[12];
u32 halt_req_mask;
#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
@ -2988,7 +2988,7 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#if defined(CONFIG_BSC9132)
#if defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)

3
include/configs/BSC9131RDB.h
Unescape View File

@ -11,10 +11,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_BSC9131RDB
#define CONFIG_BSC9131
#define CONFIG_NAND_FSL_IFC
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH

4
include/configs/BSC9132QDS.h
Unescape View File

@ -11,10 +11,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_BSC9132QDS
#define CONFIG_BSC9132
#endif
#define CONFIG_MISC_INIT_R
#ifdef CONFIG_SDCARD

2
scripts/config_whitelist.txt
Unescape View File

@ -451,9 +451,7 @@ CONFIG_BOOT_RETRY_MIN
CONFIG_BOOT_RETRY_TIME
CONFIG_BOUNCE_BUFFER
CONFIG_BPTR_VIRT_ADDR
CONFIG_BSC9131
CONFIG_BSC9131RDB
CONFIG_BSC9132
CONFIG_BSC9132QDS
CONFIG_BSEIP
CONFIG_BS_ADDR_DEVICE

Write Preview
Loading…
Cancel
Save