* Add support for P3G4 board * Fix problem with MGT5100 FEC driver: add "early" MAC address initializationmaster
parent
326428cc8b
commit
12f34241cb
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,269 @@ |
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/*
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* (C) Copyright 2001-2003 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <command.h> |
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#include <malloc.h> |
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/* ------------------------------------------------------------------------- */ |
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#if 0 |
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#define FPGA_DEBUG |
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#endif |
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/* fpga configuration data - gzip compressed and generated by bin2c */ |
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const unsigned char fpgadata[] = |
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{ |
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#include "fpgadata.c" |
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}; |
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/*
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* include common fpga code (for esd boards) |
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*/ |
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#include "../common/fpga.c" |
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/* Prototypes */ |
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int gunzip(void *, int, unsigned char *, int *); |
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int board_pre_init (void) |
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{ |
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out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */ |
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out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */ |
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive |
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* IRQ 16 405GP internally generated; active low; level sensitive |
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* IRQ 17-24 RESERVED |
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
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*/ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(uicer, 0x00000000); /* disable all ints */ |
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ |
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ |
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mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
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*/ |
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#if 1 /* test-only */ |
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mtebc (epcr, 0xa8400000); /* ebc always driven */ |
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#else |
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mtebc (epcr, 0x28400000); /* ebc in high-z */ |
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#endif |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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int misc_init_f (void) |
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{ |
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return 0; /* dummy implementation */ |
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} |
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int misc_init_r (void) |
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{ |
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#if 0 /* test-only */
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DECLARE_GLOBAL_DATA_PTR; |
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#if 0 |
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volatile unsigned short *fpga_mode = |
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); |
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volatile unsigned char *duart0_mcr = |
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(unsigned char *)((ulong)DUART0_BA + 4); |
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volatile unsigned char *duart1_mcr = |
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(unsigned char *)((ulong)DUART1_BA + 4); |
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bd_t *bd = gd->bd; |
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char * tmp; /* Temporary char pointer */ |
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unsigned char *dst; |
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ulong len = sizeof(fpgadata); |
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int status; |
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int index; |
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int i; |
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unsigned long cntrl0Reg; |
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dst = malloc(CFG_FPGA_MAX_SIZE); |
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if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) { |
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printf ("GUNZIP ERROR - must RESET board to recover\n"); |
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do_reset (NULL, 0, 0, NULL); |
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} |
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status = fpga_boot(dst, len); |
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if (status != 0) { |
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printf("\nFPGA: Booting failed "); |
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switch (status) { |
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case ERROR_FPGA_PRG_INIT_LOW: |
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); |
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break; |
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case ERROR_FPGA_PRG_INIT_HIGH: |
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); |
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break; |
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case ERROR_FPGA_PRG_DONE: |
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printf("(Timeout: DONE not high after programming FPGA)\n "); |
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break; |
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} |
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/* display infos on fpgaimage */ |
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index = 15; |
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for (i=0; i<4; i++) { |
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len = dst[index]; |
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printf("FPGA: %s\n", &(dst[index+1])); |
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index += len+3; |
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} |
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putc ('\n'); |
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/* delayed reboot */ |
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for (i=20; i>0; i--) { |
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printf("Rebooting in %2d seconds \r",i); |
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for (index=0;index<1000;index++) |
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udelay(1000); |
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} |
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putc ('\n'); |
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do_reset(NULL, 0, 0, NULL); |
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} |
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puts("FPGA: "); |
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/* display infos on fpgaimage */ |
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index = 15; |
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for (i=0; i<4; i++) { |
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len = dst[index]; |
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printf("%s ", &(dst[index+1])); |
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index += len+3; |
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} |
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putc ('\n'); |
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free(dst); |
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/*
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* Reset FPGA via FPGA_DATA pin |
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*/ |
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SET_FPGA(FPGA_PRG | FPGA_CLK); |
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udelay(1000); /* wait 1ms */ |
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); |
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udelay(1000); /* wait 1ms */ |
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#endif |
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#if 0 |
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/*
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* Enable power on PS/2 interface |
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*/ |
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*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; |
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/*
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* Enable interrupts in exar duart mcr[3] |
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*/ |
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*duart0_mcr = 0x08; |
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*duart1_mcr = 0x08; |
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#endif |
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#endif |
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return (0); |
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} |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard (void) |
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{ |
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unsigned char str[64]; |
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int i = getenv_r ("serial#", str, sizeof(str)); |
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puts ("Board: "); |
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if (i == -1) { |
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puts ("### No HW ID - assuming PPChameleonEVB"); |
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} else { |
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puts(str); |
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} |
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putc ('\n'); |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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long int initdram (int board_type) |
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{ |
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unsigned long val; |
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mtdcr(memcfga, mem_mb0cf); |
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val = mfdcr(memcfgd); |
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#if 0 /* test-only */
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for (;;) { |
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NAND_DISABLE_CE(1); |
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udelay(100); |
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NAND_ENABLE_CE(1); |
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udelay(100); |
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} |
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#endif |
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#if 0 |
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printf("\nmb0cf=%x\n", val); /* test-only */ |
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printf("strap=%x\n", mfdcr(strap)); /* test-only */ |
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#endif |
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return (4*1024*1024 << ((val & 0x000e0000) >> 17)); |
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} |
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/* ------------------------------------------------------------------------- */ |
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int testdram (void) |
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{ |
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/* TODO: XXX XXX XXX */ |
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printf ("test: 16 MB - ok\n"); |
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return (0); |
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} |
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/* ------------------------------------------------------------------------- */ |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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extern void |
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nand_probe(ulong physadr); |
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void |
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nand_init(void) |
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{ |
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printf("Probing at 0x%.8x\n", CFG_NAND0_BASE); |
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nand_probe(CFG_NAND0_BASE); |
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printf("Probing at 0x%.8x\n", CFG_NAND1_BASE); |
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nand_probe(CFG_NAND1_BASE); |
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} |
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#endif |
@ -0,0 +1,24 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xFFFC0000
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@ -0,0 +1,105 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <ppc4xx.h> |
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#include <asm/processor.h> |
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/*
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* include common flash code (for esd boards) |
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*/ |
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#include "../common/flash.c" |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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#ifdef __DEBUG_START_FROM_SRAM__ |
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return CFG_DUMMY_FLASH_SIZE; |
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#else |
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unsigned long size_b0; |
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int i; |
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uint pbcr; |
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unsigned long base_b0; |
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int size_val = 0; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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} |
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/* Setup offsets */ |
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flash_get_offsets (-size_b0, &flash_info[0]); |
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/* Re-do sizing to get full correct info */ |
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mtdcr(ebccfga, pb0cr); |
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pbcr = mfdcr(ebccfgd); |
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mtdcr(ebccfga, pb0cr); |
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base_b0 = -size_b0; |
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switch (size_b0) { |
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case 1 << 20: |
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size_val = 0; |
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break; |
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case 2 << 20: |
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size_val = 1; |
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break; |
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case 4 << 20: |
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size_val = 2; |
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break; |
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case 8 << 20: |
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size_val = 3; |
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break; |
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case 16 << 20: |
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size_val = 4; |
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break; |
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} |
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); |
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mtdcr(ebccfgd, pbcr); |
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/* Monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, |
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-CFG_MONITOR_LEN, |
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0xffffffff, |
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&flash_info[0]); |
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flash_info[0].size = size_b0; |
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return (size_b0); |
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#endif |
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} |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,147 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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.resetvec 0xFFFFFFFC : |
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{ |
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*(.resetvec) |
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} = 0xffff |
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|
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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cpu/ppc4xx/start.o (.text) |
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cpu/ppc4xx/traps.o (.text) |
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cpu/ppc4xx/interrupts.o (.text) |
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cpu/ppc4xx/serial.o (.text) |
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cpu/ppc4xx/cpu_init.o (.text) |
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cpu/ppc4xx/speed.o (.text) |
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cpu/ppc4xx/405gp_enet.o (.text) |
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common/dlmalloc.o (.text) |
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lib_generic/crc32.o (.text) |
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lib_ppc/extable.o (.text) |
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lib_generic/zlib.o (.text) |
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/* . = env_offset;*/ |
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/* common/environment.o(.text)*/ |
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|
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*(.text) |
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*(.fixup) |
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*(.got1) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(.rodata) |
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*(.rodata1) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,681 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ppc4xx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_get_offsets (ulong base, flash_info_t *info) |
||||
{ |
||||
int i; |
||||
short n; |
||||
|
||||
/* set up sector start address table */ |
||||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { |
||||
for (i = 0; i < info->sector_count; i++) |
||||
info->start[i] = base + (i * 0x00010000); |
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ |
||||
info->start[i] = base; |
||||
base += 8 << 10; |
||||
} |
||||
while (i < info->sector_count) { /* 64k regular sectors */ |
||||
info->start[i] = base; |
||||
base += 64 << 10; |
||||
++i; |
||||
} |
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { |
||||
/* set sector offsets for top boot block type */ |
||||
base += info->size; |
||||
i = info->sector_count; |
||||
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ |
||||
base -= 8 << 10; |
||||
--i; |
||||
info->start[i] = base; |
||||
} |
||||
while (i > 0) { /* 64k regular sectors */ |
||||
base -= 64 << 10; |
||||
--i; |
||||
info->start[i] = base; |
||||
} |
||||
} else { |
||||
if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00004000; |
||||
info->start[2] = base + 0x00006000; |
||||
info->start[3] = base + 0x00008000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00004000; |
||||
info->start[i--] = base + info->size - 0x00006000; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00010000; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
int k; |
||||
int size; |
||||
int erased; |
||||
volatile unsigned long *flash; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: printf ("AMD "); break; |
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
||||
case FLASH_MAN_SST: printf ("SST "); break; |
||||
case FLASH_MAN_STM: printf ("ST "); break; |
||||
default: printf ("Unknown Vendor "); break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); |
||||
break; |
||||
case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); |
||||
break; |
||||
case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); |
||||
break; |
||||
case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); |
||||
break; |
||||
case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); |
||||
break; |
||||
case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); |
||||
break; |
||||
case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n"); |
||||
break; |
||||
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); |
||||
break; |
||||
case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); |
||||
break; |
||||
case FLASH_STMW320DT: printf ("M29W320DT (32 M, top sector)\n"); |
||||
break; |
||||
default: printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i=0; i<info->sector_count; ++i) { |
||||
#ifdef CFG_FLASH_EMPTY_INFO |
||||
/*
|
||||
* Check if whole sector is erased |
||||
*/ |
||||
if (i != (info->sector_count-1)) |
||||
size = info->start[i+1] - info->start[i]; |
||||
else |
||||
size = info->start[0] + info->size - info->start[i]; |
||||
erased = 1; |
||||
flash = (volatile unsigned long *)info->start[i]; |
||||
size = size >> 2; /* divide by 4 for longword access */ |
||||
for (k=0; k<size; k++) |
||||
{ |
||||
if (*flash++ != 0xffffffff) |
||||
{ |
||||
erased = 0; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
/* print empty and read-only info */ |
||||
printf (" %08lX%s%s", |
||||
info->start[i], |
||||
erased ? " E" : " ", |
||||
info->protect[i] ? "RO " : " "); |
||||
#else |
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " "); |
||||
#endif |
||||
|
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
||||
{ |
||||
short i; |
||||
short n; |
||||
CFG_FLASH_WORD_SIZE value; |
||||
ulong base = (ulong)addr; |
||||
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; |
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; |
||||
|
||||
value = addr2[CFG_FLASH_READ0]; |
||||
|
||||
switch (value) { |
||||
case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: |
||||
info->flash_id = FLASH_MAN_FUJ; |
||||
break; |
||||
case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: |
||||
info->flash_id = FLASH_MAN_SST; |
||||
break; |
||||
case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: |
||||
info->flash_id = FLASH_MAN_STM; |
||||
break; |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
value = addr2[CFG_FLASH_READ1]; /* device ID */ |
||||
|
||||
switch (value) { |
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: |
||||
info->flash_id += FLASH_AM400T; |
||||
info->sector_count = 11; |
||||
info->size = 0x00080000; |
||||
break; /* => 0.5 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: |
||||
info->flash_id += FLASH_AM400B; |
||||
info->sector_count = 11; |
||||
info->size = 0x00080000; |
||||
break; /* => 0.5 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: |
||||
info->flash_id += FLASH_AM800T; |
||||
info->sector_count = 19; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: |
||||
info->flash_id += FLASH_AM800B; |
||||
info->sector_count = 19; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: |
||||
info->flash_id += FLASH_AM160T; |
||||
info->sector_count = 35; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: |
||||
info->flash_id += FLASH_AM160B; |
||||
info->sector_count = 35; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: |
||||
info->flash_id += FLASH_STMW320DT; |
||||
info->sector_count = 67; |
||||
info->size = 0x00400000; break; /* => 4 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: |
||||
info->flash_id += FLASH_AM320T; |
||||
info->sector_count = 71; |
||||
info->size = 0x00400000; break; /* => 4 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: |
||||
info->flash_id += FLASH_AM320B; |
||||
info->sector_count = 71; |
||||
info->size = 0x00400000; break; /* => 4 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: |
||||
info->flash_id += FLASH_AMDL322T; |
||||
info->sector_count = 71; |
||||
info->size = 0x00400000; break; /* => 4 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: |
||||
info->flash_id += FLASH_AMDL322B; |
||||
info->sector_count = 71; |
||||
info->size = 0x00400000; break; /* => 4 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: |
||||
info->flash_id += FLASH_AMDL323T; |
||||
info->sector_count = 71; |
||||
info->size = 0x00400000; break; /* => 4 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: |
||||
info->flash_id += FLASH_AMDL323B; |
||||
info->sector_count = 71; |
||||
info->size = 0x00400000; break; /* => 4 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U: |
||||
info->flash_id += FLASH_AM640U; |
||||
info->sector_count = 128; |
||||
info->size = 0x00800000; break; /* => 8 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A: |
||||
info->flash_id += FLASH_SST800A; |
||||
info->sector_count = 16; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A: |
||||
info->flash_id += FLASH_SST160A; |
||||
info->sector_count = 32; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
return (0); /* => no or unknown flash */ |
||||
|
||||
} |
||||
|
||||
/* set up sector start address table */ |
||||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { |
||||
for (i = 0; i < info->sector_count; i++) |
||||
info->start[i] = base + (i * 0x00010000); |
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ |
||||
info->start[i] = base; |
||||
base += 8 << 10; |
||||
} |
||||
while (i < info->sector_count) { /* 64k regular sectors */ |
||||
info->start[i] = base; |
||||
base += 64 << 10; |
||||
++i; |
||||
} |
||||
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || |
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { |
||||
/* set sector offsets for top boot block type */ |
||||
base += info->size; |
||||
i = info->sector_count; |
||||
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ |
||||
base -= 8 << 10; |
||||
--i; |
||||
info->start[i] = base; |
||||
} |
||||
while (i > 0) { /* 64k regular sectors */ |
||||
base -= 64 << 10; |
||||
--i; |
||||
info->start[i] = base; |
||||
} |
||||
} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { |
||||
/* set sector offsets for top boot block type */ |
||||
base += info->size; |
||||
i = info->sector_count; |
||||
/* 1 x 16k boot sector */ |
||||
base -= 16 << 10; |
||||
--i; |
||||
info->start[i] = base; |
||||
/* 2 x 8k boot sectors */ |
||||
for (n=0; n<2; ++n) { |
||||
base -= 8 << 10; |
||||
--i; |
||||
info->start[i] = base; |
||||
} |
||||
/* 1 x 32k boot sector */ |
||||
base -= 32 << 10; |
||||
--i; |
||||
info->start[i] = base; |
||||
|
||||
while (i > 0) { /* 64k regular sectors */ |
||||
base -= 64 << 10; |
||||
--i; |
||||
info->start[i] = base; |
||||
} |
||||
} else { |
||||
if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00004000; |
||||
info->start[2] = base + 0x00006000; |
||||
info->start[3] = base + 0x00008000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00004000; |
||||
info->start[i--] = base + info->size - 0x00006000; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00010000; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
||||
/* D0 = 1 if protected */ |
||||
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); |
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) |
||||
info->protect[i] = 0; |
||||
else |
||||
info->protect[i] = addr2[CFG_FLASH_READ2] & 1; |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if (info->flash_id != FLASH_UNKNOWN) { |
||||
addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; |
||||
*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); |
||||
volatile CFG_FLASH_WORD_SIZE *addr2; |
||||
int flag, prot, sect, l_sect; |
||||
ulong start, now, last; |
||||
int i; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("Can't erase unknown flash type - aborted\n"); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); |
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { |
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; |
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; |
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; |
||||
addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ |
||||
for (i=0; i<50; i++) |
||||
udelay(1000); /* wait 1 ms */ |
||||
} else { |
||||
if (sect == s_first) { |
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; |
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; |
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; |
||||
} |
||||
addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ |
||||
} |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); |
||||
while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { |
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
DONE: |
||||
/* reset to read mode */ |
||||
addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; |
||||
addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ |
||||
|
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); |
||||
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; |
||||
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; |
||||
ulong start; |
||||
int flag; |
||||
int i; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) & |
||||
(CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) |
||||
{ |
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; |
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; |
||||
|
||||
dest2[i] = data2[i]; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != |
||||
(data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
@ -0,0 +1,256 @@ |
||||
/*
|
||||
* (C) Copyright 2001-2003 |
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <command.h> |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#ifdef FPGA_DEBUG |
||||
#define DBG(x...) printf(x) |
||||
#else |
||||
#define DBG(x...) |
||||
#endif /* DEBUG */ |
||||
|
||||
#define MAX_ONES 226 |
||||
|
||||
#ifdef CFG_FPGA_PRG |
||||
# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/ |
||||
# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ |
||||
# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ |
||||
# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ |
||||
# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ |
||||
#else |
||||
# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
||||
# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ |
||||
# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ |
||||
# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ |
||||
# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ |
||||
#endif |
||||
|
||||
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ |
||||
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ |
||||
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ |
||||
|
||||
#define SET_FPGA(data) out32(GPIO0_OR, data) |
||||
|
||||
#define FPGA_WRITE_1 { \ |
||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ |
||||
|
||||
#define FPGA_WRITE_0 { \ |
||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
|
||||
SET_FPGA(FPGA_PRG); /* set data to 0 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ |
||||
|
||||
#if 0 |
||||
static int fpga_boot (unsigned char *fpgadata, int size) |
||||
{ |
||||
int i, index, len; |
||||
int count; |
||||
|
||||
#ifdef CFG_FPGA_SPARTAN2 |
||||
int j; |
||||
#else |
||||
unsigned char b; |
||||
int bit; |
||||
#endif |
||||
|
||||
/* display infos on fpgaimage */ |
||||
index = 15; |
||||
for (i = 0; i < 4; i++) { |
||||
len = fpgadata[index]; |
||||
DBG ("FPGA: %s\n", &(fpgadata[index + 1])); |
||||
index += len + 3; |
||||
} |
||||
|
||||
#ifdef CFG_FPGA_SPARTAN2 |
||||
/* search for preamble 0xFFFFFFFF */ |
||||
while (1) { |
||||
if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) |
||||
&& (fpgadata[index + 2] == 0xff) |
||||
&& (fpgadata[index + 3] == 0xff)) |
||||
break; /* preamble found */ |
||||
else |
||||
index++; |
||||
} |
||||
#else |
||||
/* search for preamble 0xFF2X */ |
||||
for (index = 0; index < size - 1; index++) { |
||||
if ((fpgadata[index] == 0xff) |
||||
&& ((fpgadata[index + 1] & 0xf0) == 0x30)) |
||||
break; |
||||
} |
||||
index += 2; |
||||
#endif |
||||
|
||||
DBG ("FPGA: configdata starts at position 0x%x\n", index); |
||||
DBG ("FPGA: length of fpga-data %d\n", size - index); |
||||
|
||||
/*
|
||||
* Setup port pins for fpga programming |
||||
*/ |
||||
out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ |
||||
out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ |
||||
out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */ |
||||
|
||||
DBG ("%s, ", |
||||
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); |
||||
DBG ("%s\n", |
||||
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); |
||||
|
||||
/*
|
||||
* Init fpga by asserting and deasserting PROGRAM* |
||||
*/ |
||||
SET_FPGA (FPGA_CLK | FPGA_DATA); |
||||
|
||||
/* Wait for FPGA init line low */ |
||||
count = 0; |
||||
while (in32 (GPIO0_IR) & FPGA_INIT) { |
||||
udelay (1000); /* wait 1ms */ |
||||
/* Check for timeout - 100us max, so use 3ms */ |
||||
if (count++ > 3) { |
||||
DBG ("FPGA: Booting failed!\n"); |
||||
return ERROR_FPGA_PRG_INIT_LOW; |
||||
} |
||||
} |
||||
|
||||
DBG ("%s, ", |
||||
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); |
||||
DBG ("%s\n", |
||||
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); |
||||
|
||||
/* deassert PROGRAM* */ |
||||
SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); |
||||
|
||||
/* Wait for FPGA end of init period . */ |
||||
count = 0; |
||||
while (!(in32 (GPIO0_IR) & FPGA_INIT)) { |
||||
udelay (1000); /* wait 1ms */ |
||||
/* Check for timeout */ |
||||
if (count++ > 3) { |
||||
DBG ("FPGA: Booting failed!\n"); |
||||
return ERROR_FPGA_PRG_INIT_HIGH; |
||||
} |
||||
} |
||||
|
||||
DBG ("%s, ", |
||||
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); |
||||
DBG ("%s\n", |
||||
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); |
||||
|
||||
DBG ("write configuration data into fpga\n"); |
||||
/* write configuration-data into fpga... */ |
||||
|
||||
#ifdef CFG_FPGA_SPARTAN2 |
||||
/*
|
||||
* Load uncompressed image into fpga |
||||
*/ |
||||
for (i = index; i < size; i++) { |
||||
for (j = 0; j < 8; j++) { |
||||
if ((fpgadata[i] & 0x80) == 0x80) { |
||||
FPGA_WRITE_1; |
||||
} else { |
||||
FPGA_WRITE_0; |
||||
} |
||||
fpgadata[i] <<= 1; |
||||
} |
||||
} |
||||
#else /* ! CFG_FPGA_SPARTAN2 */ |
||||
/* send 0xff 0x20 */ |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_0; |
||||
FPGA_WRITE_0; |
||||
FPGA_WRITE_1; |
||||
FPGA_WRITE_0; |
||||
FPGA_WRITE_0; |
||||
FPGA_WRITE_0; |
||||
FPGA_WRITE_0; |
||||
FPGA_WRITE_0; |
||||
|
||||
/*
|
||||
** Bit_DeCompression |
||||
** Code 1 .. maxOnes : n '1's followed by '0' |
||||
** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' |
||||
** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' |
||||
** 255 : '1' |
||||
*/ |
||||
|
||||
for (i = index; i < size; i++) { |
||||
b = fpgadata[i]; |
||||
if ((b >= 1) && (b <= MAX_ONES)) { |
||||
for (bit = 0; bit < b; bit++) { |
||||
FPGA_WRITE_1; |
||||
} |
||||
FPGA_WRITE_0; |
||||
} else if (b == (MAX_ONES + 1)) { |
||||
for (bit = 1; bit < b; bit++) { |
||||
FPGA_WRITE_1; |
||||
} |
||||
} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { |
||||
for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { |
||||
FPGA_WRITE_0; |
||||
} |
||||
FPGA_WRITE_1; |
||||
} else if (b == 255) { |
||||
FPGA_WRITE_1; |
||||
} |
||||
} |
||||
#endif /* CFG_FPGA_SPARTAN2 */ |
||||
|
||||
DBG ("%s, ", |
||||
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); |
||||
DBG ("%s\n", |
||||
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); |
||||
|
||||
/*
|
||||
* Check if fpga's DONE signal - correctly booted ? |
||||
*/ |
||||
|
||||
/* Wait for FPGA end of programming period . */ |
||||
count = 0; |
||||
while (!(in32 (GPIO0_IR) & FPGA_DONE)) { |
||||
udelay (1000); /* wait 1ms */ |
||||
/* Check for timeout */ |
||||
if (count++ > 3) { |
||||
DBG ("FPGA: Booting failed!\n"); |
||||
return ERROR_FPGA_PRG_DONE; |
||||
} |
||||
} |
||||
|
||||
DBG ("FPGA: Booting successful!\n"); |
||||
return 0; |
||||
} |
||||
#endif /* 0 */ |
@ -0,0 +1,202 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ppc4xx.h> |
||||
#include <asm/processor.h> |
||||
#include <pci.h> |
||||
|
||||
|
||||
u_long pci9054_iobase; |
||||
|
||||
|
||||
#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ |
||||
#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Subroutine: pci9054_read_config_dword |
||||
| Description: Read a PCI configuration register |
||||
| Inputs: |
||||
| hose PCI Controller |
||||
| dev PCI Bus+Device+Function number |
||||
| offset Configuration register number |
||||
| value Address of the configuration register value |
||||
| Return value: |
||||
| 0 Successful |
||||
+-----------------------------------------------------------------------------*/ |
||||
int pci9054_read_config_dword(struct pci_controller *hose, |
||||
pci_dev_t dev, int offset, u32* value) |
||||
{ |
||||
unsigned long conAdrVal; |
||||
unsigned long val; |
||||
|
||||
/* generate coded value for CON_ADR register */ |
||||
conAdrVal = dev | (offset & 0xfc) | 0x80000000; |
||||
|
||||
/* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ |
||||
*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; |
||||
|
||||
/* Note: *pResult comes back as -1 if machine check happened */ |
||||
val = in32r(PCI_PRIMARY_CDR); |
||||
|
||||
*value = (unsigned long) val; |
||||
|
||||
out32r(PCI_PRIMARY_CAR, 0); |
||||
|
||||
if ((*(unsigned long *)0x50000304) & 0x60000000) |
||||
{ |
||||
/* clear pci master/target abort bits */ |
||||
*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Subroutine: pci9054_write_config_dword |
||||
| Description: Write a PCI configuration register. |
||||
| Inputs: |
||||
| hose PCI Controller |
||||
| dev PCI Bus+Device+Function number |
||||
| offset Configuration register number |
||||
| Value Configuration register value |
||||
| Return value: |
||||
| 0 Successful |
||||
| Updated for pass2 errata #6. Need to disable interrupts and clear the |
||||
| PCICFGADR reg after writing the PCICFGDATA reg. |
||||
+-----------------------------------------------------------------------------*/ |
||||
int pci9054_write_config_dword(struct pci_controller *hose, |
||||
pci_dev_t dev, int offset, u32 value) |
||||
{ |
||||
unsigned long conAdrVal; |
||||
|
||||
conAdrVal = dev | (offset & 0xfc) | 0x80000000; |
||||
|
||||
*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; |
||||
|
||||
out32r(PCI_PRIMARY_CDR, value); |
||||
|
||||
out32r(PCI_PRIMARY_CAR, 0); |
||||
|
||||
/* clear pci master/target abort bits */ |
||||
*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
#ifdef CONFIG_DASA_SIM |
||||
static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, |
||||
struct pci_config_table *_) |
||||
{ |
||||
unsigned int iobase; |
||||
unsigned short status = 0; |
||||
unsigned char timer; |
||||
|
||||
/*
|
||||
* Configure PLX PCI9054 |
||||
*/ |
||||
pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); |
||||
status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
||||
pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); |
||||
|
||||
/* Check the latency timer for values >= 0x60.
|
||||
*/ |
||||
pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); |
||||
if (timer < 0x60) |
||||
{ |
||||
pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); |
||||
} |
||||
|
||||
/* Set I/O base register.
|
||||
*/ |
||||
pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); |
||||
pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); |
||||
|
||||
pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); |
||||
|
||||
if (pci9054_iobase == 0xffffffff) |
||||
{ |
||||
printf("Error: Can not set I/O base register.\n"); |
||||
return; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
static struct pci_config_table pci9054_config_table[] = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), |
||||
pci_cfgfunc_config_device, { CFG_ETH_IOBASE, |
||||
CFG_ETH_IOBASE, |
||||
PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, |
||||
#ifdef CONFIG_DASA_SIM |
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), |
||||
pci_dasa_sim_config_pci9054 }, |
||||
#endif |
||||
#endif |
||||
{ } |
||||
}; |
||||
|
||||
static struct pci_controller pci9054_hose = { |
||||
config_table: pci9054_config_table, |
||||
}; |
||||
|
||||
void pci_init(void) |
||||
{ |
||||
struct pci_controller *hose = &pci9054_hose; |
||||
|
||||
/*
|
||||
* Register the hose |
||||
*/ |
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0xff; |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose->regions + 0, |
||||
0x00000000, 0x00000000, 0x01000000, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
/* PCI Memory space */ |
||||
pci_set_region(hose->regions + 1, |
||||
0x00000000, 0xc0000000, 0x10000000, |
||||
PCI_REGION_MEM); |
||||
|
||||
pci_set_ops(hose, |
||||
pci_hose_read_config_byte_via_dword, |
||||
pci_hose_read_config_word_via_dword, |
||||
pci9054_read_config_dword, |
||||
pci_hose_write_config_byte_via_dword, |
||||
pci_hose_write_config_word_via_dword, |
||||
pci9054_write_config_dword); |
||||
|
||||
hose->region_count = 2; |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
hose->last_busno = pci_hose_scan(hose); |
||||
} |
@ -0,0 +1,394 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/processor.h> |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
#include <galileo/core.h> |
||||
#endif |
||||
|
||||
#include "../board/evb64260/local.h" |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_P3G4 1 /* this is a P3G4 board */ |
||||
#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ |
||||
|
||||
#undef CONFIG_ECC /* enable ECC support */ |
||||
/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ |
||||
|
||||
/* which initialization functions to call for this board */ |
||||
#define CONFIG_MISC_INIT_R 1 |
||||
#define CONFIG_BOARD_PRE_INIT 1 |
||||
|
||||
#define CFG_BOARD_NAME "P3G4" |
||||
|
||||
#undef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/*
|
||||
* The following defines let you select what serial you want to use |
||||
* for your console driver. |
||||
* |
||||
* to use the MPSC, #define CONFIG_MPSC. If you have wired up another |
||||
* mpsc channel, change CONFIG_MPSC_PORT to the desired value. |
||||
*/ |
||||
#define CONFIG_MPSC |
||||
#define CONFIG_MPSC_PORT 1 |
||||
|
||||
#define CONFIG_NET_MULTI /* attempt all available adapters */ |
||||
|
||||
/* define this if you want to enable GT MAC filtering */ |
||||
#define CONFIG_GT_USE_MAC_HASH_TABLE |
||||
|
||||
#undef CONFIG_ETHER_PORT_MII /* use RMII */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp && " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:" \
|
||||
"$netmask:$hostname:eth0:none; && " \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#undef CONFIG_ALTIVEC /* undef to disable */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ |
||||
CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00300000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decr freq: 1ms ticks */ |
||||
#define CFG_BUS_HZ 133000000 /* 133 MHz */ |
||||
#define CFG_BUS_CLK CFG_BUS_HZ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x40000000 |
||||
#define CFG_INIT_RAM_END 0x1000 |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_RAM_LOCK |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xff800000 |
||||
#define CFG_RESET_ADDRESS 0xfff00100 |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ |
||||
|
||||
/* areas to map different things with the GT in physical space */ |
||||
#define CFG_DRAM_BANKS 1 |
||||
#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ |
||||
|
||||
/* What to put in the bats. */ |
||||
#define CFG_MISC_REGION_BASE 0xf0000000 |
||||
|
||||
/* Peripheral Device section */ |
||||
#define CFG_GT_REGS 0xf8000000 |
||||
#define CFG_DEV_BASE 0xff000000 |
||||
|
||||
#define CFG_DEV0_SPACE CFG_DEV_BASE |
||||
#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) |
||||
#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) |
||||
#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) |
||||
|
||||
#define CFG_DEV0_SIZE _8M /* Flash bank */ |
||||
#define CFG_DEV1_SIZE 0 /* unused */ |
||||
#define CFG_DEV2_SIZE 0 /* unused */ |
||||
#define CFG_DEV3_SIZE 0 /* unused */ |
||||
|
||||
#define CFG_16BIT_BOOT_PAR 0xc01b5e7c |
||||
#define CFG_DEV0_PAR CFG_16BIT_BOOT_PAR |
||||
|
||||
#if 0 /* Wrong?? NTL */
|
||||
#define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ |
||||
/* DMAAck[1:0] GNT0[1:0] */ |
||||
#else |
||||
#define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ |
||||
/* REQ0[1:0] GNT0[1:0] */ |
||||
#endif |
||||
#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ |
||||
/* DMAReq[4] DMAAck[4] WDNMI WDE */ |
||||
#if 0 /* Wrong?? NTL */
|
||||
#define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ |
||||
/* DMAAck[1:0] GNT1[1:0] */ |
||||
#else |
||||
#define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ |
||||
/* GPP[22] (RS232IntB or PCI1Int) */ |
||||
/* GPP[21] (RS323IntA) */ |
||||
/* BClkIn */ |
||||
/* REQ1[1:0] GNT1[1:0] */ |
||||
#endif |
||||
|
||||
#if 0 /* Wrong?? NTL */
|
||||
# define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ |
||||
/* GPP[27:26] Int[1:0] */ |
||||
#else |
||||
# define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ |
||||
/* GPP[29] (PCI1Int) */ |
||||
/* BClkOut0 */ |
||||
/* GPP[27] (PCI0Int) */ |
||||
/* GPP[26] (RtcInt or PCI1Int) */ |
||||
/* CPUInt[25:24] */ |
||||
#endif |
||||
|
||||
#define CFG_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ |
||||
|
||||
#if 0 /* Wrong?? - NTL */
|
||||
# define CFG_GPP_LEVEL_CONTROL 0x000002c6 |
||||
#else |
||||
# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ |
||||
/* gpp[29] */ |
||||
/* gpp[27:26] */ |
||||
/* gpp[22:21] */ |
||||
|
||||
# define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ |
||||
/* idmas use buffer 1,1
|
||||
comm use buffer 0 |
||||
pci use buffer 1,1 |
||||
cpu use buffer 0 |
||||
normal load (see also ifdef HVL) |
||||
standard SDRAM (see also ifdef REG) |
||||
non staggered refresh */ |
||||
/* 31:26 25 23 20 19 18 16 */ |
||||
/* 110110 00 111 0 0 00 1 */ |
||||
/* refresh_count=0x200
|
||||
phisical interleaving disable |
||||
virtual interleaving enable */ |
||||
/* 15 14 13:0 */ |
||||
/* 1 0 0x200 */ |
||||
#endif |
||||
|
||||
#if 0 |
||||
#define CFG_DUART_IO CFG_DEV2_SPACE |
||||
#define CFG_DUART_CHAN 1 /* channel to use for console */ |
||||
#endif |
||||
#undef CFG_INIT_CHAN1 |
||||
#undef CFG_INIT_CHAN2 |
||||
#if 0 |
||||
#define SRAM_BASE CFG_DEV0_SPACE |
||||
#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ |
||||
#endif |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
/* PCI MEMORY MAP section */ |
||||
#define CFG_PCI0_MEM_BASE 0x80000000 |
||||
#define CFG_PCI0_MEM_SIZE _128M |
||||
#define CFG_PCI1_MEM_BASE 0x88000000 |
||||
#define CFG_PCI1_MEM_SIZE _128M |
||||
|
||||
#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) |
||||
#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) |
||||
|
||||
|
||||
/* PCI I/O MAP section */ |
||||
#define CFG_PCI0_IO_BASE 0xfa000000 |
||||
#define CFG_PCI0_IO_SIZE _16M |
||||
#define CFG_PCI1_IO_BASE 0xfb000000 |
||||
#define CFG_PCI1_IO_SIZE _16M |
||||
|
||||
#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) |
||||
#define CFG_PCI0_IO_SPACE_PCI 0x00000000 |
||||
#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) |
||||
#define CFG_PCI1_IO_SPACE_PCI 0x00000000 |
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* Initial BAT mappings |
||||
*/ |
||||
|
||||
/* NOTES:
|
||||
* 1) GUARDED and WRITE_THRU not allowed in IBATS |
||||
* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT |
||||
*/ |
||||
|
||||
/* SDRAM */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
|
||||
/* init ram */ |
||||
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
/* PCI0, PCI1 in one BAT */ |
||||
#define CFG_IBAT2L BATL_NO_ACCESS |
||||
#define CFG_IBAT2U CFG_DBAT2U |
||||
#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* GT regs, bootrom, all the devices, PCI I/O */ |
||||
#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) |
||||
#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) |
||||
#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
/* I2C speed and slave address (for compatability) defaults */ |
||||
#define CFG_I2C_SPEED 400000 |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/* I2C addresses for the two DIMM SPD chips */ |
||||
#ifndef CONFIG_EVB64260_750CX |
||||
#define DIMM0_I2C_ADDR 0x56 |
||||
#define DIMM1_I2C_ADDR 0x54 |
||||
#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ |
||||
#define DIMM0_I2C_ADDR 0x54 |
||||
#define DIMM1_I2C_ADDR 0x54 |
||||
#endif |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ |
||||
#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ |
||||
#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
#define CFG_FLASH_CFI 1 |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
||||
#define CFG_ENV_SECT_SIZE 0x20000 |
||||
#define CFG_ENV_ADDR 0xFFFE0000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* L2CR setup -- make sure this is right for your board! |
||||
* look in include/74xx_7xx.h for the defines used here |
||||
*/ |
||||
|
||||
#define CFG_L2 |
||||
|
||||
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
||||
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
||||
|
||||
#define L2_ENABLE (L2_INIT | L2CR_L2E) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_BOARD_ASM_INIT 1 |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,734 @@ |
||||
/*
|
||||
* (C) Copyright 2001-2003 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* Debug stuff |
||||
*/ |
||||
#undef __DEBUG_START_FROM_SRAM__ |
||||
#define __DISABLE_MACHINE_EXCEPTION__ |
||||
|
||||
#ifdef __DEBUG_START_FROM_SRAM__ |
||||
#define CFG_DUMMY_FLASH_SIZE 1024*1024*4 |
||||
#endif |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
||||
#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */ |
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#else |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#endif |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#if 0 |
||||
#define CONFIG_PREBOOT \ |
||||
"crc32 f0207004 ffc 0;" \
|
||||
"if cmp 0 f0207000 1;" \
|
||||
"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
|
||||
"else;echo Old CRC is bad;fi" |
||||
#endif |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
|
||||
"bootm ffc00000 ffca0000" |
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
|
||||
"bootm ffc00000" |
||||
|
||||
#define CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND \ |
||||
"setenv ipaddr 192.168.10.203;" \
|
||||
"setenv serverip 192.168.10.6;" \
|
||||
"setenv netmask 255.255.255.0;" \
|
||||
"setenv bootargs root=/dev/ram rw console=ttyS0,9600;" \
|
||||
"setenv autostart yes;" \
|
||||
"bootm ffc00000 ffd00000" |
||||
/*
|
||||
"setenv ethaddr 00:50:c2:1e:af:fe;" \
|
||||
"setenv eth1addr 00:50:c2:1e:af:fd;" \
|
||||
*/ |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
|
||||
/* EThernet stuff */ |
||||
#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ |
||||
#define CONFIG_ETHADDR 00:50:c2:1e:af:fe |
||||
#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd |
||||
|
||||
#undef CONFIG_EXT_PHY |
||||
/*#define CONFIG_EXT_PHY*/ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#ifndef CONFIG_EXT_PHY |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */ |
||||
#else |
||||
#define CONFIG_PHY_ADDR 2 /* PHY address */ |
||||
#endif |
||||
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ |
||||
|
||||
#if 0 /* test-only */
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM ) |
||||
#else |
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM ) |
||||
#endif |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
||||
#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#undef CFG_HUSH_PARSER /* use "hush" command parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ |
||||
|
||||
#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ |
||||
#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ |
||||
#define CFG_BASE_BAUD 691200 |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 } |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND-FLASH stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_NAND0_BASE 0xFF400000 |
||||
#define CFG_NAND1_BASE 0xFF000000 |
||||
|
||||
#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ |
||||
#define SECTORSIZE 512 |
||||
|
||||
#define ADDR_COLUMN 1 |
||||
#define ADDR_PAGE 2 |
||||
#define ADDR_COLUMN_PAGE 3 |
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00 |
||||
#define NAND_MAX_FLOORS 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
|
||||
#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
||||
#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ |
||||
#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ |
||||
#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ |
||||
|
||||
#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ |
||||
#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ |
||||
#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ |
||||
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ |
||||
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do \ |
||||
{ \
|
||||
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
|
||||
{ \
|
||||
case CFG_NAND0_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
|
||||
break; \
|
||||
case CFG_NAND1_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
|
||||
break; \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
#define NAND_ENABLE_CE(nand) do \ |
||||
{ \
|
||||
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
|
||||
{ \
|
||||
case CFG_NAND0_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
|
||||
break; \
|
||||
case CFG_NAND1_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
|
||||
break; \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
|
||||
|
||||
#define NAND_CTL_CLRALE(nandptr) do \ |
||||
{ \
|
||||
switch((unsigned long)nandptr) \
|
||||
{ \
|
||||
case CFG_NAND0_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
|
||||
break; \
|
||||
case CFG_NAND1_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
|
||||
break; \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
#define NAND_CTL_SETALE(nandptr) do \ |
||||
{ \
|
||||
switch((unsigned long)nandptr) \
|
||||
{ \
|
||||
case CFG_NAND0_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
|
||||
break; \
|
||||
case CFG_NAND1_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
|
||||
break; \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
#define NAND_CTL_CLRCLE(nandptr) do \ |
||||
{ \
|
||||
switch((unsigned long)nandptr) \
|
||||
{ \
|
||||
case CFG_NAND0_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
|
||||
break; \
|
||||
case CFG_NAND1_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
|
||||
break; \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
#define NAND_CTL_SETCLE(nandptr) do { \ |
||||
switch((unsigned long)nandptr) { \
|
||||
case CFG_NAND0_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
|
||||
break; \
|
||||
case CFG_NAND1_BASE: \
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
|
||||
break; \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
#define NAND_WAIT_READY(nand) do { \ |
||||
ulong mask = 0; \
|
||||
switch ((ulong)(((struct nand_chip *)nand)->IO_ADDR)) { \
|
||||
case CFG_NAND0_BASE: \
|
||||
mask = CFG_NAND0_RDY; \
|
||||
break; \
|
||||
case CFG_NAND1_BASE: \
|
||||
mask = CFG_NAND1_RDY; \
|
||||
break; \
|
||||
} \
|
||||
while (!(in32(GPIO0_IR) & mask)) \
|
||||
; \
|
||||
} while (0) |
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) |
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) |
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) |
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ |
||||
#undef CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
/* resource configuration */ |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ |
||||
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ |
||||
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ |
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFFC0000 |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
||||
#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
||||
#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface. |
||||
* All other boards should use the standard values (CPCI405 etc.) |
||||
*/ |
||||
#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ |
||||
#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ |
||||
#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ |
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
#if 0 /* test-only */
|
||||
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
||||
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment Variable setup |
||||
*/ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
||||
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ |
||||
/* total size of a CAT24WC16 is 2048 bytes */ |
||||
|
||||
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
||||
#define CFG_NVRAM_SIZE 242 /* NVRAM size */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC16) for environment |
||||
*/ |
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ |
||||
/* have only 8kB, 16kB is save here */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
||||
#define CFG_EBC_PB0AP 0x92015480 |
||||
#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 1 (External SRAM) initialization */ |
||||
/* Since this must replace NOR Flash, we use the same settings for CS0 */ |
||||
#define CFG_EBC_PB1AP 0x92015480 |
||||
#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ |
||||
#define CFG_EBC_PB2AP 0x92015480 |
||||
#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ |
||||
#define CFG_EBC_PB3AP 0x92015480 |
||||
#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ |
||||
|
||||
|
||||
#if 0 /* Roese */
|
||||
/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
||||
#define CFG_EBC_PB1AP 0x92015480 |
||||
#define CFG_EBC_PB1CR 0xFF858000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 2 (CAN0, 1) initialization */ |
||||
#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
||||
#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 3 (CompactFlash IDE) initialization */ |
||||
#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
||||
#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 4 (NVRAM/RTC) initialization */ |
||||
#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ |
||||
#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff |
||||
*/ |
||||
/* FPGA internal regs */ |
||||
#define CFG_FPGA_MODE 0x00 |
||||
#define CFG_FPGA_STATUS 0x02 |
||||
#define CFG_FPGA_TS 0x04 |
||||
#define CFG_FPGA_TS_LOW 0x06 |
||||
#define CFG_FPGA_TS_CAP0 0x10 |
||||
#define CFG_FPGA_TS_CAP0_LOW 0x12 |
||||
#define CFG_FPGA_TS_CAP1 0x14 |
||||
#define CFG_FPGA_TS_CAP1_LOW 0x16 |
||||
#define CFG_FPGA_TS_CAP2 0x18 |
||||
#define CFG_FPGA_TS_CAP2_LOW 0x1a |
||||
#define CFG_FPGA_TS_CAP3 0x1c |
||||
#define CFG_FPGA_TS_CAP3_LOW 0x1e |
||||
|
||||
/* FPGA Mode Reg */ |
||||
#define CFG_FPGA_MODE_CF_RESET 0x0001 |
||||
#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 |
||||
#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 |
||||
#define CFG_FPGA_MODE_TS_CLEAR 0x2000 |
||||
|
||||
/* FPGA Status Reg */ |
||||
#define CFG_FPGA_STATUS_DIP0 0x0001 |
||||
#define CFG_FPGA_STATUS_DIP1 0x0002 |
||||
#define CFG_FPGA_STATUS_DIP2 0x0004 |
||||
#define CFG_FPGA_STATUS_FLASH 0x0008 |
||||
#define CFG_FPGA_STATUS_TS_IRQ 0x1000 |
||||
|
||||
#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
||||
#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ |
||||
|
||||
/* FPGA program pin configuration */ |
||||
#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
||||
#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ |
||||
#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ |
||||
#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ |
||||
#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
#if 0 /* test-only */
|
||||
#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ |
||||
|
||||
#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#else |
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CFG_OCM_DATA_ADDR 0xF8000000 |
||||
#define CFG_OCM_DATA_SIZE 0x1000 |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ |
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
||||
#endif |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific) |
||||
* |
||||
* GPIO0[0] - External Bus Controller BLAST output |
||||
* GPIO0[1-9] - Instruction trace outputs -> GPIO |
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO |
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs |
||||
* GPIO0[28-29] - UART1 data signal input/output |
||||
* GPIO0[30] - EMAC0 input |
||||
* GPIO0[31] - EMAC1 reject packet as output |
||||
*/ |
||||
#define CFG_GPIO0_OSRH 0x40000550 |
||||
#define CFG_GPIO0_OSRL 0x00000110 |
||||
#define CFG_GPIO0_ISR1H 0x00000000 |
||||
/*#define CFG_GPIO0_ISR1L 0x15555445*/ |
||||
#define CFG_GPIO0_ISR1L 0x15555444 |
||||
#define CFG_GPIO0_TSRH 0x00000000 |
||||
#define CFG_GPIO0_TSRL 0x00000000 |
||||
#define CFG_GPIO0_TCR 0xF7FF8014 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if 1 /* test-only */ |
||||
#define CONFIG_NO_SERIAL_EEPROM |
||||
/*#undef CONFIG_NO_SERIAL_EEPROM*/ |
||||
/*----------------------------------------------------------------------------*/ |
||||
/*----------------------------------------------------------------------------*/ |
||||
/*----------------------------------------------------------------------------*/ |
||||
#ifdef CONFIG_NO_SERIAL_EEPROM |
||||
|
||||
|
||||
/*
|
||||
!------------------------------------------------------------------------------- |
||||
! Defines for entry options. |
||||
! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that |
||||
! are plugged in the board will be utilized as non-ECC DIMMs. |
||||
!------------------------------------------------------------------------------- |
||||
*/ |
||||
#undef AUTO_MEMORY_CONFIG |
||||
#define DIMM_READ_ADDR 0xAB |
||||
#define DIMM_WRITE_ADDR 0xAA |
||||
|
||||
|
||||
#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ |
||||
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ |
||||
#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ |
||||
#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ |
||||
#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ |
||||
#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ |
||||
#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ |
||||
#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ |
||||
#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ |
||||
#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ |
||||
|
||||
/* Defines for CPC0_PLLMR1 Register fields */ |
||||
#define PLL_ACTIVE 0x80000000 |
||||
#define CPC0_PLLMR1_SSCS 0x80000000 |
||||
#define PLL_RESET 0x40000000 |
||||
#define CPC0_PLLMR1_PLLR 0x40000000 |
||||
/* Feedback multiplier */ |
||||
#define PLL_FBKDIV 0x00F00000 |
||||
#define CPC0_PLLMR1_FBDV 0x00F00000 |
||||
#define PLL_FBKDIV_16 0x00000000 |
||||
#define PLL_FBKDIV_1 0x00100000 |
||||
#define PLL_FBKDIV_2 0x00200000 |
||||
#define PLL_FBKDIV_3 0x00300000 |
||||
#define PLL_FBKDIV_4 0x00400000 |
||||
#define PLL_FBKDIV_5 0x00500000 |
||||
#define PLL_FBKDIV_6 0x00600000 |
||||
#define PLL_FBKDIV_7 0x00700000 |
||||
#define PLL_FBKDIV_8 0x00800000 |
||||
#define PLL_FBKDIV_9 0x00900000 |
||||
#define PLL_FBKDIV_10 0x00A00000 |
||||
#define PLL_FBKDIV_11 0x00B00000 |
||||
#define PLL_FBKDIV_12 0x00C00000 |
||||
#define PLL_FBKDIV_13 0x00D00000 |
||||
#define PLL_FBKDIV_14 0x00E00000 |
||||
#define PLL_FBKDIV_15 0x00F00000 |
||||
/* Forward A divisor */ |
||||
#define PLL_FWDDIVA 0x00070000 |
||||
#define CPC0_PLLMR1_FWDVA 0x00070000 |
||||
#define PLL_FWDDIVA_8 0x00000000 |
||||
#define PLL_FWDDIVA_7 0x00010000 |
||||
#define PLL_FWDDIVA_6 0x00020000 |
||||
#define PLL_FWDDIVA_5 0x00030000 |
||||
#define PLL_FWDDIVA_4 0x00040000 |
||||
#define PLL_FWDDIVA_3 0x00050000 |
||||
#define PLL_FWDDIVA_2 0x00060000 |
||||
#define PLL_FWDDIVA_1 0x00070000 |
||||
/* Forward B divisor */ |
||||
#define PLL_FWDDIVB 0x00007000 |
||||
#define CPC0_PLLMR1_FWDVB 0x00007000 |
||||
#define PLL_FWDDIVB_8 0x00000000 |
||||
#define PLL_FWDDIVB_7 0x00001000 |
||||
#define PLL_FWDDIVB_6 0x00002000 |
||||
#define PLL_FWDDIVB_5 0x00003000 |
||||
#define PLL_FWDDIVB_4 0x00004000 |
||||
#define PLL_FWDDIVB_3 0x00005000 |
||||
#define PLL_FWDDIVB_2 0x00006000 |
||||
#define PLL_FWDDIVB_1 0x00007000 |
||||
/* PLL tune bits */ |
||||
#define PLL_TUNE_MASK 0x000003FF |
||||
#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ |
||||
#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ |
||||
#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ |
||||
#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ |
||||
#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ |
||||
#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ |
||||
#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ |
||||
|
||||
/* Defines for CPC0_PLLMR0 Register fields */ |
||||
/* CPU divisor */ |
||||
#define PLL_CPUDIV 0x00300000 |
||||
#define CPC0_PLLMR0_CCDV 0x00300000 |
||||
#define PLL_CPUDIV_1 0x00000000 |
||||
#define PLL_CPUDIV_2 0x00100000 |
||||
#define PLL_CPUDIV_3 0x00200000 |
||||
#define PLL_CPUDIV_4 0x00300000 |
||||
/* PLB divisor */ |
||||
#define PLL_PLBDIV 0x00030000 |
||||
#define CPC0_PLLMR0_CBDV 0x00030000 |
||||
#define PLL_PLBDIV_1 0x00000000 |
||||
#define PLL_PLBDIV_2 0x00010000 |
||||
#define PLL_PLBDIV_3 0x00020000 |
||||
#define PLL_PLBDIV_4 0x00030000 |
||||
/* OPB divisor */ |
||||
#define PLL_OPBDIV 0x00003000 |
||||
#define CPC0_PLLMR0_OPDV 0x00003000 |
||||
#define PLL_OPBDIV_1 0x00000000 |
||||
#define PLL_OPBDIV_2 0x00001000 |
||||
#define PLL_OPBDIV_3 0x00002000 |
||||
#define PLL_OPBDIV_4 0x00003000 |
||||
/* EBC divisor */ |
||||
#define PLL_EXTBUSDIV 0x00000300 |
||||
#define CPC0_PLLMR0_EPDV 0x00000300 |
||||
#define PLL_EXTBUSDIV_2 0x00000000 |
||||
#define PLL_EXTBUSDIV_3 0x00000100 |
||||
#define PLL_EXTBUSDIV_4 0x00000200 |
||||
#define PLL_EXTBUSDIV_5 0x00000300 |
||||
/* MAL divisor */ |
||||
#define PLL_MALDIV 0x00000030 |
||||
#define CPC0_PLLMR0_MPDV 0x00000030 |
||||
#define PLL_MALDIV_1 0x00000000 |
||||
#define PLL_MALDIV_2 0x00000010 |
||||
#define PLL_MALDIV_3 0x00000020 |
||||
#define PLL_MALDIV_4 0x00000030 |
||||
/* PCI divisor */ |
||||
#define PLL_PCIDIV 0x00000003 |
||||
#define CPC0_PLLMR0_PPFD 0x00000003 |
||||
#define PLL_PCIDIV_1 0x00000000 |
||||
#define PLL_PCIDIV_2 0x00000001 |
||||
#define PLL_PCIDIV_3 0x00000002 |
||||
#define PLL_PCIDIV_4 0x00000003 |
||||
|
||||
/*
|
||||
!------------------------------------------------------------------------------- |
||||
! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, |
||||
! assuming a 33.3MHz input clock to the 405EP. |
||||
!------------------------------------------------------------------------------- |
||||
*/ |
||||
#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ |
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4) |
||||
#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ |
||||
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
||||
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4) |
||||
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ |
||||
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
||||
#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4) |
||||
#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ |
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
||||
#if 0 /* test-only */
|
||||
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
||||
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 |
||||
#endif |
||||
#if 0 /* test-only */
|
||||
#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
||||
#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 |
||||
#endif |
||||
#if 1 /* test-only */ |
||||
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
||||
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 |
||||
#endif |
||||
|
||||
#endif |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue