Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>master
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_FSL_ERRATA_H |
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#define _ASM_FSL_ERRATA_H |
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#include <common.h> |
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#include <asm/processor.h> |
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 |
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static inline bool has_erratum_a006379(void) |
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{ |
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u32 svr = get_svr(); |
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if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || |
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((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2)) |
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return true; |
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return false; |
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} |
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#endif |
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#endif |
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