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@ -3,6 +3,11 @@ |
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* |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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* |
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* Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
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* Changed: |
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* Made board specific defines such as DDR timing and PLL |
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* dividers. These should be set in the board config file |
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* |
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* Partially based on TI sources, original copyrights follow: |
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*/ |
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@ -156,17 +161,17 @@ WaitPPL2Loop: |
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/* Program the PLL Multiplier */ |
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ldr r6, PLL2_PLLM |
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mov r2, $0x17 /* 162 MHz */ |
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mov r2, $CFG_DAVINCI_PLL2_PLLM |
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str r2, [r6] |
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/* Program the PLL2 Divisor Value */ |
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ldr r6, PLL2_DIV2 |
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mov r3, $0x01 |
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mov r3, $CFG_DAVINCI_PLL2_DIV2 |
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str r3, [r6] |
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/* Program the PLL2 Divisor Value */ |
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ldr r6, PLL2_DIV1 |
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mov r4, $0x0b /* 54 MHz */ |
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mov r4, $CFG_DAVINCI_PLL2_DIV1 |
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str r4, [r6] |
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/* PLL2 DIV2 MMR */ |
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@ -273,7 +278,7 @@ checkDDRStatClkStop: |
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bne checkDDRStatClkStop |
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/*------------------------------------------------------* |
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* Program DDR2 MMRs for 162MHz Setting * |
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* Program DDR2 MMRs * |
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*------------------------------------------------------*/ |
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/* Program PHY Control Register */ |
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@ -288,12 +293,12 @@ checkDDRStatClkStop: |
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/* Program SDRAM TIM-0 Config Register */ |
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ldr r6, SDTIM0 |
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ldr r7, SDTIM0_VAL_162MHz |
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ldr r7, SDTIM0_VAL |
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str r7, [r6] |
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/* Program SDRAM TIM-1 Config Register */ |
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ldr r6, SDTIM1 |
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ldr r7, SDTIM1_VAL_162MHz |
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ldr r7, SDTIM1_VAL |
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str r7, [r6] |
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/* Program the SDRAM Bank Config Control Register */ |
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@ -435,7 +440,7 @@ WaitLoop: |
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/* Program the PLL Multiplier */ |
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ldr r6, PLL1_PLLM |
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mov r3, $0x15 /* For 594MHz */ |
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mov r3, $CFG_DAVINCI_PLL1_PLLM |
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str r3, [r6] |
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/* Wait for PLL to Reset Properly */ |
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@ -467,7 +472,7 @@ PLL1Lock: |
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nop |
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/*------------------------------------------------------* |
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* AEMIF configuration for NOR Flash (double check) * |
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* AEMIF configuration for NAND/NOR Flash * |
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*------------------------------------------------------*/ |
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ldr r0, _PINMUX0 |
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ldr r1, _DEV_SETTING |
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@ -479,6 +484,12 @@ PLL1Lock: |
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orr r2, r2, r1 |
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str r2, [r0] |
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ldr r0, ACFG2 |
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ldr r1, ACFG2_VAL |
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ldr r2, [r0] |
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and r1, r2, r1 |
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str r1, [r0] |
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ldr r0, ACFG3 |
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ldr r1, ACFG3_VAL |
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ldr r2, [r0] |
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@ -497,6 +508,12 @@ PLL1Lock: |
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and r1, r2, r1 |
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str r1, [r0] |
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ldr r0, NANDFCR |
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ldr r1, NANDFCR_VAL |
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ldr r2, [r0] |
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and r1, r2, r1 |
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str r1, [r0] |
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/*--------------------------------------* |
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* VTP manual Calibration * |
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*--------------------------------------*/ |
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@ -560,24 +577,36 @@ _PINMUX1: |
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.word 0x01c40004 /* Device Configuration Registers */ |
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_DEV_SETTING: |
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.word 0x00000c1f
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.word CFG_DAVINCI_PINMUX_0
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WAITCFG: |
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.word 0x01e00004
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WAITCFG_VAL: |
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.word 0
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.word CFG_DAVINCI_WAITCFG
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ACFG2: |
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.word 0x01e00010
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ACFG2_VAL: |
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.word CFG_DAVINCI_ACFG2
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ACFG3: |
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.word 0x01e00014
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ACFG3_VAL: |
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.word 0x3ffffffd
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.word CFG_DAVINCI_ACFG3
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ACFG4: |
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.word 0x01e00018
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ACFG4_VAL: |
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.word 0x3ffffffd
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.word CFG_DAVINCI_ACFG4
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ACFG5: |
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.word 0x01e0001c
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ACFG5_VAL: |
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.word 0x3ffffffd
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.word CFG_DAVINCI_ACFG5
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NANDFCR: |
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.word 0x01e00060
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NANDFCR_VAL: |
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#ifdef CFG_DAVINCI_NANDCE |
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.word (1 << (CFG_DAVINCI_NANDCE - 2)) |
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#else |
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.word 0x00000000
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#endif |
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MDCTL_DDR2: |
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.word 0x01c41a34
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@ -599,33 +628,27 @@ PSC_FLAG_CLEAR: |
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PSC_GEM_FLAG_CLEAR: |
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.word 0xfffffeff
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/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */ |
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/* DDR2 MMR & CONFIGURATION VALUES */ |
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DDRCTL: |
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.word 0x200000e4
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DDRCTL_VAL: |
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.word 0x50006405
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.word CFG_DAVINCI_DDRCTL
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SDREF: |
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.word 0x2000000c
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SDREF_VAL: |
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.word 0x000005c3
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.word CFG_DAVINCI_SDREF
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SDCFG: |
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.word 0x20000008
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SDCFG_VAL: |
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#ifdef DDR_4BANKS |
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.word 0x00178622
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#elif defined DDR_8BANKS |
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.word 0x00178632
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#else |
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#error "Unknown DDR configuration!!!" |
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#endif |
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.word CFG_DAVINCI_SDCFG
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SDTIM0: |
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.word 0x20000010
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SDTIM0_VAL_162MHz: |
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.word 0x28923211
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SDTIM0_VAL: |
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.word CFG_DAVINCI_SDTIM0
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SDTIM1: |
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.word 0x20000014
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SDTIM1_VAL_162MHz: |
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.word 0x0016c722
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SDTIM1_VAL: |
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.word CFG_DAVINCI_SDTIM1
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VTPIOCR: |
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.word 0x200000f0 /* VTP IO Control register */ |
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DDRVTPR: |
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@ -699,7 +722,7 @@ PLL2_DIV_MASK: |
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MMARG_BRF0: |
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.word 0x01c42010 /* BRF margin mode 0 (R/W)*/ |
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MMARG_BRF0_VAL: |
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.word 0x00444400
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.word CFG_DAVINCI_MMARG_BRF0
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DDR2_START_ADDR: |
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.word 0x80000000
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