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@ -32,6 +32,32 @@ |
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u32 s_first_boot = 1; |
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void init_pllx(void) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 reg; |
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/* If PLLX is already enabled, just return */ |
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reg = readl(&clkrst->crc_pllx_base); |
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if (reg & PLL_ENABLE) |
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return; |
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/* Set PLLX_MISC */ |
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reg = CPCON; /* CPCON[11:8] = 0001 */ |
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writel(reg, &clkrst->crc_pllx_misc); |
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/* Use 12MHz clock here */ |
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reg = (PLL_BYPASS | PLL_DIVM); |
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reg |= (1000 << 8); /* DIVN = 0x3E8 */ |
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writel(reg, &clkrst->crc_pllx_base); |
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reg |= PLL_ENABLE; |
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writel(reg, &clkrst->crc_pllx_base); |
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reg &= ~PLL_BYPASS; |
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writel(reg, &clkrst->crc_pllx_base); |
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} |
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static void enable_cpu_clock(int enable) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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@ -47,6 +73,9 @@ static void enable_cpu_clock(int enable) |
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*/ |
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if (enable) { |
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/* Initialize PLLX */ |
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init_pllx(); |
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/* Wait until all clocks are stable */ |
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udelay(PLL_STABILIZATION_DELAY); |
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