- Re-sync DT files for am33xx with Linux Kernel v4.1 - Include DT file now for the "AM335x GP EVM" and build target for it, via device tree and DM. - We only need to provide platform data for UART when OF_CONTROL isn't also enabled really. We can just push GPIO to coming from DT Signed-off-by: Tom Rini <trini@konsulko.com>master
Tom Rini
10 years ago
parent
8883ddafde
commit
1480fdf8a6
@ -0,0 +1,29 @@ |
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/* |
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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/dts-v1/; |
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|
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#include "am33xx.dtsi" |
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#include "am335x-bone-common.dtsi" |
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|
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/ { |
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model = "TI AM335x BeagleBone"; |
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compatible = "ti,am335x-bone", "ti,am33xx"; |
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chosen { |
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stdout-path = &uart0; |
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}; |
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}; |
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|
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&ldo3_reg { |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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|
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&mmc1 { |
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vmmc-supply = <&ldo3_reg>; |
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}; |
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@ -0,0 +1,765 @@ |
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/* |
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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/dts-v1/; |
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|
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#include "am33xx.dtsi" |
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#include <dt-bindings/interrupt-controller/irq.h> |
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/ { |
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model = "TI AM335x EVM"; |
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compatible = "ti,am335x-evm", "ti,am33xx"; |
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|
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chosen { |
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stdout-path = &uart0; |
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}; |
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|
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cpus { |
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cpu@0 { |
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cpu0-supply = <&vdd1_reg>; |
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}; |
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}; |
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|
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memory { |
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device_type = "memory"; |
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reg = <0x80000000 0x10000000>; /* 256 MB */ |
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}; |
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|
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vbat: fixedregulator@0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "vbat"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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regulator-boot-on; |
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}; |
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|
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lis3_reg: fixedregulator@1 { |
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compatible = "regulator-fixed"; |
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regulator-name = "lis3_reg"; |
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regulator-boot-on; |
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}; |
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|
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wlan_en_reg: fixedregulator@2 { |
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compatible = "regulator-fixed"; |
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regulator-name = "wlan-en-regulator"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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|
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/* WLAN_EN GPIO for this board - Bank1, pin16 */ |
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gpio = <&gpio1 16 0>; |
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|
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/* WLAN card specific delay */ |
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startup-delay-us = <70000>; |
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enable-active-high; |
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}; |
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|
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matrix_keypad: matrix_keypad@0 { |
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compatible = "gpio-matrix-keypad"; |
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debounce-delay-ms = <5>; |
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col-scan-delay-us = <2>; |
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row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ |
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&gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ |
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&gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ |
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col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ |
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&gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ |
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linux,keymap = <0x0000008b /* MENU */ |
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0x0100009e /* BACK */ |
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0x02000069 /* LEFT */ |
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0x0001006a /* RIGHT */ |
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0x0101001c /* ENTER */ |
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0x0201006c>; /* DOWN */ |
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}; |
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gpio_keys: volume_keys@0 { |
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compatible = "gpio-keys"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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autorepeat; |
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switch@9 { |
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label = "volume-up"; |
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linux,code = <115>; |
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; |
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gpio-key,wakeup; |
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}; |
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switch@10 { |
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label = "volume-down"; |
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linux,code = <114>; |
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gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; |
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gpio-key,wakeup; |
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}; |
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}; |
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|
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backlight { |
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compatible = "pwm-backlight"; |
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pwms = <&ecap0 0 50000 0>; |
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brightness-levels = <0 51 53 56 62 75 101 152 255>; |
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default-brightness-level = <8>; |
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}; |
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panel { |
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compatible = "ti,tilcdc,panel"; |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&lcd_pins_s0>; |
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panel-info { |
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ac-bias = <255>; |
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ac-bias-intrpt = <0>; |
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dma-burst-sz = <16>; |
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bpp = <32>; |
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fdd = <0x80>; |
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sync-edge = <0>; |
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sync-ctrl = <1>; |
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raster-order = <0>; |
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fifo-th = <0>; |
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}; |
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display-timings { |
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800x480p62 { |
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clock-frequency = <30000000>; |
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hactive = <800>; |
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vactive = <480>; |
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hfront-porch = <39>; |
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hback-porch = <39>; |
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hsync-len = <47>; |
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vback-porch = <29>; |
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vfront-porch = <13>; |
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vsync-len = <2>; |
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hsync-active = <1>; |
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vsync-active = <1>; |
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}; |
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}; |
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}; |
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sound { |
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compatible = "ti,da830-evm-audio"; |
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ti,model = "AM335x-EVM"; |
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ti,audio-codec = <&tlv320aic3106>; |
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ti,mcasp-controller = <&mcasp1>; |
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ti,codec-clock-rate = <12000000>; |
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ti,audio-routing = |
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"Headphone Jack", "HPLOUT", |
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"Headphone Jack", "HPROUT", |
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"LINE1L", "Line In", |
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"LINE1R", "Line In"; |
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}; |
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}; |
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&am33xx_pinmux { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; |
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matrix_keypad_s0: matrix_keypad_s0 { |
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pinctrl-single,pins = < |
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0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ |
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0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ |
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0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ |
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0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ |
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0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ |
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>; |
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}; |
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volume_keys_s0: volume_keys_s0 { |
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pinctrl-single,pins = < |
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0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ |
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0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ |
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>; |
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}; |
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i2c0_pins: pinmux_i2c0_pins { |
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pinctrl-single,pins = < |
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0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
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0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
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>; |
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}; |
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i2c1_pins: pinmux_i2c1_pins { |
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pinctrl-single,pins = < |
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0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ |
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0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ |
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>; |
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}; |
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uart0_pins: pinmux_uart0_pins { |
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pinctrl-single,pins = < |
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0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
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0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
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>; |
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}; |
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uart1_pins: pinmux_uart1_pins { |
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pinctrl-single,pins = < |
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0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ |
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0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ |
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0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ |
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0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ |
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>; |
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}; |
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clkout2_pin: pinmux_clkout2_pin { |
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pinctrl-single,pins = < |
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0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ |
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>; |
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}; |
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nandflash_pins_s0: nandflash_pins_s0 { |
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pinctrl-single,pins = < |
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0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ |
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0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ |
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0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ |
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0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ |
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0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ |
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0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ |
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0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ |
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0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ |
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0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ |
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0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ |
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0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ |
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0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ |
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0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ |
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0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ |
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0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ |
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>; |
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}; |
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ecap0_pins: backlight_pins { |
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pinctrl-single,pins = < |
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0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ |
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>; |
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}; |
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cpsw_default: cpsw_default { |
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pinctrl-single,pins = < |
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/* Slave 1 */ |
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0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ |
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ |
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0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ |
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0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ |
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0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ |
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0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ |
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0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ |
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0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ |
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0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ |
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0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ |
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ |
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ |
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>; |
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}; |
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cpsw_sleep: cpsw_sleep { |
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pinctrl-single,pins = < |
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/* Slave 1 reset value */ |
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0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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>; |
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}; |
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davinci_mdio_default: davinci_mdio_default { |
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pinctrl-single,pins = < |
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/* MDIO */ |
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0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
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0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
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>; |
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}; |
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davinci_mdio_sleep: davinci_mdio_sleep { |
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pinctrl-single,pins = < |
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/* MDIO reset value */ |
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0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
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>; |
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}; |
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mmc1_pins: pinmux_mmc1_pins { |
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pinctrl-single,pins = < |
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0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
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>; |
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}; |
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mmc3_pins: pinmux_mmc3_pins { |
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pinctrl-single,pins = < |
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0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ |
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0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ |
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0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ |
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0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ |
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0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ |
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0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ |
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>; |
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}; |
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|
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wlan_pins: pinmux_wlan_pins { |
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pinctrl-single,pins = < |
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0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ |
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0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ |
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0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ |
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>; |
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}; |
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|
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lcd_pins_s0: lcd_pins_s0 { |
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pinctrl-single,pins = < |
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0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ |
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0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ |
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0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ |
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0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ |
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0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ |
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0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ |
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0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ |
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0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ |
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0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ |
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0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ |
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0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ |
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0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ |
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0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ |
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0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ |
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0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ |
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0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ |
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0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ |
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0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ |
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0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ |
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0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ |
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0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ |
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0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ |
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0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ |
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0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ |
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0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ |
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0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ |
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0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ |
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0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ |
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>; |
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}; |
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|
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am335x_evm_audio_pins: am335x_evm_audio_pins { |
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pinctrl-single,pins = < |
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ |
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ |
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0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ |
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0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ |
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>; |
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}; |
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|
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dcan1_pins_default: dcan1_pins_default { |
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pinctrl-single,pins = < |
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0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ |
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0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ |
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>; |
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}; |
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}; |
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|
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&uart0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&uart0_pins>; |
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|
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status = "okay"; |
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}; |
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|
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&uart1 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&uart1_pins>; |
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|
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status = "okay"; |
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}; |
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|
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&i2c0 { |
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pinctrl-names = "default"; |
||||
pinctrl-0 = <&i2c0_pins>; |
||||
|
||||
status = "okay"; |
||||
clock-frequency = <400000>; |
||||
|
||||
tps: tps@2d { |
||||
reg = <0x2d>; |
||||
}; |
||||
}; |
||||
|
||||
&usb { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb_ctrl_mod { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb0_phy { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb1_phy { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb1 { |
||||
status = "okay"; |
||||
dr_mode = "host"; |
||||
}; |
||||
|
||||
&cppi41dma { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&i2c1_pins>; |
||||
|
||||
status = "okay"; |
||||
clock-frequency = <100000>; |
||||
|
||||
lis331dlh: lis331dlh@18 { |
||||
compatible = "st,lis331dlh", "st,lis3lv02d"; |
||||
reg = <0x18>; |
||||
Vdd-supply = <&lis3_reg>; |
||||
Vdd_IO-supply = <&lis3_reg>; |
||||
|
||||
st,click-single-x; |
||||
st,click-single-y; |
||||
st,click-single-z; |
||||
st,click-thresh-x = <10>; |
||||
st,click-thresh-y = <10>; |
||||
st,click-thresh-z = <10>; |
||||
st,irq1-click; |
||||
st,irq2-click; |
||||
st,wakeup-x-lo; |
||||
st,wakeup-x-hi; |
||||
st,wakeup-y-lo; |
||||
st,wakeup-y-hi; |
||||
st,wakeup-z-lo; |
||||
st,wakeup-z-hi; |
||||
st,min-limit-x = <120>; |
||||
st,min-limit-y = <120>; |
||||
st,min-limit-z = <140>; |
||||
st,max-limit-x = <550>; |
||||
st,max-limit-y = <550>; |
||||
st,max-limit-z = <750>; |
||||
}; |
||||
|
||||
tsl2550: tsl2550@39 { |
||||
compatible = "taos,tsl2550"; |
||||
reg = <0x39>; |
||||
}; |
||||
|
||||
tmp275: tmp275@48 { |
||||
compatible = "ti,tmp275"; |
||||
reg = <0x48>; |
||||
}; |
||||
|
||||
tlv320aic3106: tlv320aic3106@1b { |
||||
compatible = "ti,tlv320aic3106"; |
||||
reg = <0x1b>; |
||||
status = "okay"; |
||||
|
||||
/* Regulators */ |
||||
AVDD-supply = <&vaux2_reg>; |
||||
IOVDD-supply = <&vaux2_reg>; |
||||
DRVDD-supply = <&vaux2_reg>; |
||||
DVDD-supply = <&vbat>; |
||||
}; |
||||
}; |
||||
|
||||
&lcdc { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&elm { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&epwmss0 { |
||||
status = "okay"; |
||||
|
||||
ecap0: ecap@48300100 { |
||||
status = "okay"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&ecap0_pins>; |
||||
}; |
||||
}; |
||||
|
||||
&gpmc { |
||||
status = "okay"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&nandflash_pins_s0>; |
||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ |
||||
nand@0,0 { |
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
||||
ti,nand-ecc-opt = "bch8"; |
||||
ti,elm-id = <&elm>; |
||||
nand-bus-width = <8>; |
||||
gpmc,device-width = <1>; |
||||
gpmc,sync-clk-ps = <0>; |
||||
gpmc,cs-on-ns = <0>; |
||||
gpmc,cs-rd-off-ns = <44>; |
||||
gpmc,cs-wr-off-ns = <44>; |
||||
gpmc,adv-on-ns = <6>; |
||||
gpmc,adv-rd-off-ns = <34>; |
||||
gpmc,adv-wr-off-ns = <44>; |
||||
gpmc,we-on-ns = <0>; |
||||
gpmc,we-off-ns = <40>; |
||||
gpmc,oe-on-ns = <0>; |
||||
gpmc,oe-off-ns = <54>; |
||||
gpmc,access-ns = <64>; |
||||
gpmc,rd-cycle-ns = <82>; |
||||
gpmc,wr-cycle-ns = <82>; |
||||
gpmc,wait-on-read = "true"; |
||||
gpmc,wait-on-write = "true"; |
||||
gpmc,bus-turnaround-ns = <0>; |
||||
gpmc,cycle2cycle-delay-ns = <0>; |
||||
gpmc,clk-activation-ns = <0>; |
||||
gpmc,wait-monitoring-ns = <0>; |
||||
gpmc,wr-access-ns = <40>; |
||||
gpmc,wr-data-mux-bus-ns = <0>; |
||||
/* MTD partition table */ |
||||
/* All SPL-* partitions are sized to minimal length |
||||
* which can be independently programmable. For |
||||
* NAND flash this is equal to size of erase-block */ |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
partition@0 { |
||||
label = "NAND.SPL"; |
||||
reg = <0x00000000 0x000020000>; |
||||
}; |
||||
partition@1 { |
||||
label = "NAND.SPL.backup1"; |
||||
reg = <0x00020000 0x00020000>; |
||||
}; |
||||
partition@2 { |
||||
label = "NAND.SPL.backup2"; |
||||
reg = <0x00040000 0x00020000>; |
||||
}; |
||||
partition@3 { |
||||
label = "NAND.SPL.backup3"; |
||||
reg = <0x00060000 0x00020000>; |
||||
}; |
||||
partition@4 { |
||||
label = "NAND.u-boot-spl-os"; |
||||
reg = <0x00080000 0x00040000>; |
||||
}; |
||||
partition@5 { |
||||
label = "NAND.u-boot"; |
||||
reg = <0x000C0000 0x00100000>; |
||||
}; |
||||
partition@6 { |
||||
label = "NAND.u-boot-env"; |
||||
reg = <0x001C0000 0x00020000>; |
||||
}; |
||||
partition@7 { |
||||
label = "NAND.u-boot-env.backup1"; |
||||
reg = <0x001E0000 0x00020000>; |
||||
}; |
||||
partition@8 { |
||||
label = "NAND.kernel"; |
||||
reg = <0x00200000 0x00800000>; |
||||
}; |
||||
partition@9 { |
||||
label = "NAND.file-system"; |
||||
reg = <0x00A00000 0x0F600000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
#include "tps65910.dtsi" |
||||
|
||||
&mcasp1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&am335x_evm_audio_pins>; |
||||
|
||||
status = "okay"; |
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */ |
||||
tdm-slots = <2>; |
||||
/* 4 serializers */ |
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
||||
0 0 1 2 |
||||
>; |
||||
tx-num-evt = <32>; |
||||
rx-num-evt = <32>; |
||||
}; |
||||
|
||||
&tps { |
||||
vcc1-supply = <&vbat>; |
||||
vcc2-supply = <&vbat>; |
||||
vcc3-supply = <&vbat>; |
||||
vcc4-supply = <&vbat>; |
||||
vcc5-supply = <&vbat>; |
||||
vcc6-supply = <&vbat>; |
||||
vcc7-supply = <&vbat>; |
||||
vccio-supply = <&vbat>; |
||||
|
||||
regulators { |
||||
vrtc_reg: regulator@0 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vio_reg: regulator@1 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vdd1_reg: regulator@2 { |
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
||||
regulator-name = "vdd_mpu"; |
||||
regulator-min-microvolt = <912500>; |
||||
regulator-max-microvolt = <1312500>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vdd2_reg: regulator@3 { |
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
||||
regulator-name = "vdd_core"; |
||||
regulator-min-microvolt = <912500>; |
||||
regulator-max-microvolt = <1150000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vdd3_reg: regulator@4 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vdig1_reg: regulator@5 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vdig2_reg: regulator@6 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vpll_reg: regulator@7 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vdac_reg: regulator@8 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vaux1_reg: regulator@9 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vaux2_reg: regulator@10 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vaux33_reg: regulator@11 { |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vmmc_reg: regulator@12 { |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-always-on; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&mac { |
||||
pinctrl-names = "default", "sleep"; |
||||
pinctrl-0 = <&cpsw_default>; |
||||
pinctrl-1 = <&cpsw_sleep>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&davinci_mdio { |
||||
pinctrl-names = "default", "sleep"; |
||||
pinctrl-0 = <&davinci_mdio_default>; |
||||
pinctrl-1 = <&davinci_mdio_sleep>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&cpsw_emac0 { |
||||
phy_id = <&davinci_mdio>, <0>; |
||||
phy-mode = "rgmii-txid"; |
||||
}; |
||||
|
||||
&cpsw_emac1 { |
||||
phy_id = <&davinci_mdio>, <1>; |
||||
phy-mode = "rgmii-txid"; |
||||
}; |
||||
|
||||
&tscadc { |
||||
status = "okay"; |
||||
tsc { |
||||
ti,wires = <4>; |
||||
ti,x-plate-resistance = <200>; |
||||
ti,coordinate-readouts = <5>; |
||||
ti,wire-config = <0x00 0x11 0x22 0x33>; |
||||
ti,charge-delay = <0x400>; |
||||
}; |
||||
|
||||
adc { |
||||
ti,adc-channels = <4 5 6 7>; |
||||
}; |
||||
}; |
||||
|
||||
&mmc1 { |
||||
status = "okay"; |
||||
vmmc-supply = <&vmmc_reg>; |
||||
bus-width = <4>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&mmc1_pins>; |
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
|
||||
&mmc3 { |
||||
/* these are on the crossbar and are outlined in the |
||||
xbar-event-map element */ |
||||
dmas = <&edma 12 |
||||
&edma 13>; |
||||
dma-names = "tx", "rx"; |
||||
status = "okay"; |
||||
vmmc-supply = <&wlan_en_reg>; |
||||
bus-width = <4>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&mmc3_pins &wlan_pins>; |
||||
ti,non-removable; |
||||
ti,needs-special-hs-handling; |
||||
cap-power-off-card; |
||||
keep-power-in-suspend; |
||||
|
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
wlcore: wlcore@0 { |
||||
compatible = "ti,wl1835"; |
||||
reg = <2>; |
||||
interrupt-parent = <&gpio3>; |
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
}; |
||||
|
||||
&edma { |
||||
ti,edma-xbar-event-map = /bits/ 16 <1 12 |
||||
2 13>; |
||||
}; |
||||
|
||||
&sham { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&aes { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&dcan1 { |
||||
status = "disabled"; /* Enable only if Profile 1 is selected */ |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&dcan1_pins_default>; |
||||
}; |
||||
@ -0,0 +1,646 @@ |
||||
/* |
||||
* Device Tree Source for AM33xx clock data |
||||
* |
||||
* Copyright (C) 2013 Texas Instruments, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
&scm_clocks { |
||||
sys_clkin_ck: sys_clkin_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; |
||||
ti,bit-shift = <22>; |
||||
reg = <0x0040>; |
||||
}; |
||||
|
||||
adc_tsc_fck: adc_tsc_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
dcan0_fck: dcan0_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
dcan1_fck: dcan1_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
mcasp0_fck: mcasp0_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
mcasp1_fck: mcasp1_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
smartreflex0_fck: smartreflex0_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
smartreflex1_fck: smartreflex1_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
sha0_fck: sha0_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
aes0_fck: aes0_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
rng_fck: rng_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&l4ls_gclk>; |
||||
ti,bit-shift = <0>; |
||||
reg = <0x0664>; |
||||
}; |
||||
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&l4ls_gclk>; |
||||
ti,bit-shift = <1>; |
||||
reg = <0x0664>; |
||||
}; |
||||
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&l4ls_gclk>; |
||||
ti,bit-shift = <2>; |
||||
reg = <0x0664>; |
||||
}; |
||||
}; |
||||
&prcm_clocks { |
||||
clk_32768_ck: clk_32768_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <32768>; |
||||
}; |
||||
|
||||
clk_rc32k_ck: clk_rc32k_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <32000>; |
||||
}; |
||||
|
||||
virt_19200000_ck: virt_19200000_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <19200000>; |
||||
}; |
||||
|
||||
virt_24000000_ck: virt_24000000_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <24000000>; |
||||
}; |
||||
|
||||
virt_25000000_ck: virt_25000000_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <25000000>; |
||||
}; |
||||
|
||||
virt_26000000_ck: virt_26000000_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <26000000>; |
||||
}; |
||||
|
||||
tclkin_ck: tclkin_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <12000000>; |
||||
}; |
||||
|
||||
dpll_core_ck: dpll_core_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,am3-dpll-core-clock"; |
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; |
||||
reg = <0x0490>, <0x045c>, <0x0468>; |
||||
}; |
||||
|
||||
dpll_core_x2_ck: dpll_core_x2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,am3-dpll-x2-clock"; |
||||
clocks = <&dpll_core_ck>; |
||||
}; |
||||
|
||||
dpll_core_m4_ck: dpll_core_m4_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&dpll_core_x2_ck>; |
||||
ti,max-div = <31>; |
||||
reg = <0x0480>; |
||||
ti,index-starts-at-one; |
||||
}; |
||||
|
||||
dpll_core_m5_ck: dpll_core_m5_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&dpll_core_x2_ck>; |
||||
ti,max-div = <31>; |
||||
reg = <0x0484>; |
||||
ti,index-starts-at-one; |
||||
}; |
||||
|
||||
dpll_core_m6_ck: dpll_core_m6_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&dpll_core_x2_ck>; |
||||
ti,max-div = <31>; |
||||
reg = <0x04d8>; |
||||
ti,index-starts-at-one; |
||||
}; |
||||
|
||||
dpll_mpu_ck: dpll_mpu_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,am3-dpll-clock"; |
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; |
||||
reg = <0x0488>, <0x0420>, <0x042c>; |
||||
}; |
||||
|
||||
dpll_mpu_m2_ck: dpll_mpu_m2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&dpll_mpu_ck>; |
||||
ti,max-div = <31>; |
||||
reg = <0x04a8>; |
||||
ti,index-starts-at-one; |
||||
}; |
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,am3-dpll-no-gate-clock"; |
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; |
||||
reg = <0x0494>, <0x0434>, <0x0440>; |
||||
}; |
||||
|
||||
dpll_ddr_m2_ck: dpll_ddr_m2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&dpll_ddr_ck>; |
||||
ti,max-div = <31>; |
||||
reg = <0x04a0>; |
||||
ti,index-starts-at-one; |
||||
}; |
||||
|
||||
dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_ddr_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <2>; |
||||
}; |
||||
|
||||
dpll_disp_ck: dpll_disp_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,am3-dpll-no-gate-clock"; |
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; |
||||
reg = <0x0498>, <0x0448>, <0x0454>; |
||||
}; |
||||
|
||||
dpll_disp_m2_ck: dpll_disp_m2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&dpll_disp_ck>; |
||||
ti,max-div = <31>; |
||||
reg = <0x04a4>; |
||||
ti,index-starts-at-one; |
||||
ti,set-rate-parent; |
||||
}; |
||||
|
||||
dpll_per_ck: dpll_per_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,am3-dpll-no-gate-j-type-clock"; |
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; |
||||
reg = <0x048c>, <0x0470>, <0x049c>; |
||||
}; |
||||
|
||||
dpll_per_m2_ck: dpll_per_m2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&dpll_per_ck>; |
||||
ti,max-div = <31>; |
||||
reg = <0x04ac>; |
||||
ti,index-starts-at-one; |
||||
}; |
||||
|
||||
dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_per_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <4>; |
||||
}; |
||||
|
||||
dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_per_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <4>; |
||||
}; |
||||
|
||||
cefuse_fck: cefuse_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
ti,bit-shift = <1>; |
||||
reg = <0x0a20>; |
||||
}; |
||||
|
||||
clk_24mhz: clk_24mhz { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_per_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <8>; |
||||
}; |
||||
|
||||
clkdiv32k_ck: clkdiv32k_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&clk_24mhz>; |
||||
clock-mult = <1>; |
||||
clock-div = <732>; |
||||
}; |
||||
|
||||
clkdiv32k_ick: clkdiv32k_ick { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&clkdiv32k_ck>; |
||||
ti,bit-shift = <1>; |
||||
reg = <0x014c>; |
||||
}; |
||||
|
||||
l3_gclk: l3_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m4_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
pruss_ocp_gclk: pruss_ocp_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; |
||||
reg = <0x0530>; |
||||
}; |
||||
|
||||
mmu_fck: mmu_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&dpll_core_m4_ck>; |
||||
ti,bit-shift = <1>; |
||||
reg = <0x0914>; |
||||
}; |
||||
|
||||
timer1_fck: timer1_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; |
||||
reg = <0x0528>; |
||||
}; |
||||
|
||||
timer2_fck: timer2_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; |
||||
reg = <0x0508>; |
||||
}; |
||||
|
||||
timer3_fck: timer3_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; |
||||
reg = <0x050c>; |
||||
}; |
||||
|
||||
timer4_fck: timer4_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; |
||||
reg = <0x0510>; |
||||
}; |
||||
|
||||
timer5_fck: timer5_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; |
||||
reg = <0x0518>; |
||||
}; |
||||
|
||||
timer6_fck: timer6_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; |
||||
reg = <0x051c>; |
||||
}; |
||||
|
||||
timer7_fck: timer7_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; |
||||
reg = <0x0504>; |
||||
}; |
||||
|
||||
usbotg_fck: usbotg_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&dpll_per_ck>; |
||||
ti,bit-shift = <8>; |
||||
reg = <0x047c>; |
||||
}; |
||||
|
||||
dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m4_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <2>; |
||||
}; |
||||
|
||||
ieee5000_fck: ieee5000_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&dpll_core_m4_div2_ck>; |
||||
ti,bit-shift = <1>; |
||||
reg = <0x00e4>; |
||||
}; |
||||
|
||||
wdt1_fck: wdt1_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; |
||||
reg = <0x0538>; |
||||
}; |
||||
|
||||
l4_rtc_gclk: l4_rtc_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m4_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <2>; |
||||
}; |
||||
|
||||
l4hs_gclk: l4hs_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m4_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
l3s_gclk: l3s_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m4_div2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
l4fw_gclk: l4fw_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m4_div2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
l4ls_gclk: l4ls_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m4_div2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
sysclk_div_ck: sysclk_div_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m4_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_core_m5_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <2>; |
||||
}; |
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; |
||||
reg = <0x0520>; |
||||
}; |
||||
|
||||
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; |
||||
reg = <0x053c>; |
||||
}; |
||||
|
||||
gpio0_dbclk: gpio0_dbclk { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&gpio0_dbclk_mux_ck>; |
||||
ti,bit-shift = <18>; |
||||
reg = <0x0408>; |
||||
}; |
||||
|
||||
gpio1_dbclk: gpio1_dbclk { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&clkdiv32k_ick>; |
||||
ti,bit-shift = <18>; |
||||
reg = <0x00ac>; |
||||
}; |
||||
|
||||
gpio2_dbclk: gpio2_dbclk { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&clkdiv32k_ick>; |
||||
ti,bit-shift = <18>; |
||||
reg = <0x00b0>; |
||||
}; |
||||
|
||||
gpio3_dbclk: gpio3_dbclk { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&clkdiv32k_ick>; |
||||
ti,bit-shift = <18>; |
||||
reg = <0x00b4>; |
||||
}; |
||||
|
||||
lcd_gclk: lcd_gclk { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; |
||||
reg = <0x0534>; |
||||
ti,set-rate-parent; |
||||
}; |
||||
|
||||
mmc_clk: mmc_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll_per_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <2>; |
||||
}; |
||||
|
||||
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; |
||||
ti,bit-shift = <1>; |
||||
reg = <0x052c>; |
||||
}; |
||||
|
||||
gfx_fck_div_ck: gfx_fck_div_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&gfx_fclk_clksel_ck>; |
||||
reg = <0x052c>; |
||||
ti,max-div = <2>; |
||||
}; |
||||
|
||||
sysclkout_pre_ck: sysclkout_pre_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; |
||||
reg = <0x0700>; |
||||
}; |
||||
|
||||
clkout2_div_ck: clkout2_div_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&sysclkout_pre_ck>; |
||||
ti,bit-shift = <3>; |
||||
ti,max-div = <8>; |
||||
reg = <0x0700>; |
||||
}; |
||||
|
||||
dbg_sysclk_ck: dbg_sysclk_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&sys_clkin_ck>; |
||||
ti,bit-shift = <19>; |
||||
reg = <0x0414>; |
||||
}; |
||||
|
||||
dbg_clka_ck: dbg_clka_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&dpll_core_m4_ck>; |
||||
ti,bit-shift = <30>; |
||||
reg = <0x0414>; |
||||
}; |
||||
|
||||
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; |
||||
ti,bit-shift = <22>; |
||||
reg = <0x0414>; |
||||
}; |
||||
|
||||
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,mux-clock"; |
||||
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; |
||||
ti,bit-shift = <20>; |
||||
reg = <0x0414>; |
||||
}; |
||||
|
||||
stm_clk_div_ck: stm_clk_div_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&stm_pmd_clock_mux_ck>; |
||||
ti,bit-shift = <27>; |
||||
ti,max-div = <64>; |
||||
reg = <0x0414>; |
||||
ti,index-power-of-two; |
||||
}; |
||||
|
||||
trace_clk_div_ck: trace_clk_div_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,divider-clock"; |
||||
clocks = <&trace_pmd_clk_mux_ck>; |
||||
ti,bit-shift = <24>; |
||||
ti,max-div = <64>; |
||||
reg = <0x0414>; |
||||
ti,index-power-of-two; |
||||
}; |
||||
|
||||
clkout2_ck: clkout2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,gate-clock"; |
||||
clocks = <&clkout2_div_ck>; |
||||
ti,bit-shift = <7>; |
||||
reg = <0x0700>; |
||||
}; |
||||
}; |
||||
|
||||
&prcm_clockdomains { |
||||
clk_24mhz_clkdm: clk_24mhz_clkdm { |
||||
compatible = "ti,clockdomain"; |
||||
clocks = <&clkdiv32k_ick>; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,91 @@ |
||||
/* |
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
/* |
||||
* Integrated Power Management Chip |
||||
* http://www.ti.com/lit/ds/symlink/tps65910.pdf |
||||
*/ |
||||
|
||||
&tps { |
||||
compatible = "ti,tps65910"; |
||||
|
||||
regulators { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
vrtc_reg: regulator@0 { |
||||
reg = <0>; |
||||
regulator-compatible = "vrtc"; |
||||
}; |
||||
|
||||
vio_reg: regulator@1 { |
||||
reg = <1>; |
||||
regulator-compatible = "vio"; |
||||
}; |
||||
|
||||
vdd1_reg: regulator@2 { |
||||
reg = <2>; |
||||
regulator-compatible = "vdd1"; |
||||
}; |
||||
|
||||
vdd2_reg: regulator@3 { |
||||
reg = <3>; |
||||
regulator-compatible = "vdd2"; |
||||
}; |
||||
|
||||
vdd3_reg: regulator@4 { |
||||
reg = <4>; |
||||
regulator-compatible = "vdd3"; |
||||
}; |
||||
|
||||
vdig1_reg: regulator@5 { |
||||
reg = <5>; |
||||
regulator-compatible = "vdig1"; |
||||
}; |
||||
|
||||
vdig2_reg: regulator@6 { |
||||
reg = <6>; |
||||
regulator-compatible = "vdig2"; |
||||
}; |
||||
|
||||
vpll_reg: regulator@7 { |
||||
reg = <7>; |
||||
regulator-compatible = "vpll"; |
||||
}; |
||||
|
||||
vdac_reg: regulator@8 { |
||||
reg = <8>; |
||||
regulator-compatible = "vdac"; |
||||
}; |
||||
|
||||
vaux1_reg: regulator@9 { |
||||
reg = <9>; |
||||
regulator-compatible = "vaux1"; |
||||
}; |
||||
|
||||
vaux2_reg: regulator@10 { |
||||
reg = <10>; |
||||
regulator-compatible = "vaux2"; |
||||
}; |
||||
|
||||
vaux33_reg: regulator@11 { |
||||
reg = <11>; |
||||
regulator-compatible = "vaux33"; |
||||
}; |
||||
|
||||
vmmc_reg: regulator@12 { |
||||
reg = <12>; |
||||
regulator-compatible = "vmmc"; |
||||
}; |
||||
|
||||
vbb_reg: regulator@13 { |
||||
reg = <13>; |
||||
regulator-compatible = "vbb"; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,14 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_AM335X_EVM=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_STACK_R=y |
||||
CONFIG_SPL_STACK_R_ADDR=0x82000000 |
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND" |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_SPL_DISABLE_OF_CONTROL=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_RSA=y |
||||
Loading…
Reference in new issue