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@ -101,106 +101,6 @@ int board_mmc_get_env_dev(int devno) |
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#ifdef CONFIG_SPL_BUILD |
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#include <spl.h> |
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/* MMC board initialization is needed till adding DM support in SPL */ |
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#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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static iomux_v3_cfg_t const usdhc1_pads[] = { |
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IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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/* VSELECT */ |
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IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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/* CD */ |
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IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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/* RST_B */ |
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IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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}; |
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static iomux_v3_cfg_t const usdhc2_pads[] = { |
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IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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}; |
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) |
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#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) |
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struct fsl_esdhc_cfg usdhc_cfg[2] = { |
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{USDHC1_BASE_ADDR, 0, 4}, |
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{USDHC2_BASE_ADDR, 0, 8}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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int ret = 0; |
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switch (cfg->esdhc_base) { |
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case USDHC1_BASE_ADDR: |
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ret = !gpio_get_value(USDHC1_CD_GPIO); |
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break; |
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case USDHC2_BASE_ADDR: |
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ret = !gpio_get_value(USDHC2_CD_GPIO); |
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break; |
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} |
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return ret; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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int i, ret; |
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/*
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* According to the board_mmc_init() the following map is done: |
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* (U-boot device node) (Physical Port) |
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* mmc0 USDHC1 |
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* mmc1 USDHC2 |
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*/ |
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
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switch (i) { |
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case 0: |
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SETUP_IOMUX_PADS(usdhc1_pads); |
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gpio_direction_input(USDHC1_CD_GPIO); |
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
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break; |
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case 1: |
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SETUP_IOMUX_PADS(usdhc2_pads); |
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gpio_direction_input(USDHC2_CD_GPIO); |
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
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break; |
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default: |
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printf("Warning - USDHC%d controller not supporting\n", |
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i + 1); |
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return 0; |
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} |
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
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if (ret) { |
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printf("Warning: failed to initialize mmc dev %d\n", i); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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#ifdef CONFIG_ENV_IS_IN_MMC |
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void board_boot_order(u32 *spl_boot_list) |
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{ |
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@ -226,5 +126,4 @@ void board_boot_order(u32 *spl_boot_list) |
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spl_boot_list[0] = boot_dev; |
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} |
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#endif |
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#endif /* CONFIG_FSL_ESDHC */ |
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#endif /* CONFIG_SPL_BUILD */ |
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