Add the initial support for pico-imx7d board based on Wig Cheng's source code. Add support for eMMC, USB gadget, I2C, PMIC and Ethernet. For more information about this board, please visit: http://www.technexion.org/products/pico/pico-som/pico-imx7-emmc Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>master
Vanessa Maegima
8 years ago
committed by
Stefano Babic
parent
ccbbada0a5
commit
1541d7a63d
@ -0,0 +1,15 @@ |
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if TARGET_PICO_IMX7D |
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config SYS_BOARD |
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default "pico-imx7d" |
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config SYS_VENDOR |
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default "technexion" |
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config SYS_SOC |
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default "mx7" |
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config SYS_CONFIG_NAME |
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default "pico-imx7d" |
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endif |
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@ -0,0 +1,7 @@ |
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Technexion PICO-IMX7D board |
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M: Wig Cheng <wig.cheng@technexion.com> |
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M: Vanessa Maegima <vanessa.maegima@nxp.com> |
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S: Maintained |
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F: board/technexion/pico-imx7d/ |
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F: include/configs/pico-imx7d.h |
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F: configs/pico-imx7d_defconfig |
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@ -0,0 +1,6 @@ |
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# (C) Copyright 2017 NXP Semiconductors
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := pico-imx7d.o
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@ -0,0 +1,49 @@ |
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How to update U-Boot on pico-imx7d board |
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---------------------------------------- |
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Required software on the host PC: |
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- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader |
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Build U-Boot for pico: |
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$ make mrproper |
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$ make pico-imx7d_defconfig |
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$ make |
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This generates the U-Boot binary called u-boot.imx. |
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Put pico board in USB download mode (refer to the PICO-iMX7D Quick Start Guide |
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page 3) |
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Connect a USB to serial adapter between the host PC and pico. |
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Connect a USB cable between the OTG pico port and the host PC. |
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Open a terminal program such as minicom. |
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Copy u-boot.imx to the imx_usb_loader folder. |
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Load u-boot.imx via USB: |
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$ sudo ./imx_usb u-boot.imx |
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Then U-Boot starts and its messages appear in the console program. |
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Use the default environment variables: |
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=> env default -f -a |
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=> saveenv |
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Run the UMS command: |
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=> ums 0 mmc 0 |
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Transfer u-boot.imx to be flashed into the eMMC: |
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$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1; sync |
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Remove power from the pico board. |
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Put pico board into normal boot mode. |
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Power up the board and the new updated U-Boot should boot from eMMC. |
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@ -0,0 +1,98 @@ |
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/* |
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* Copyright (C) 2017 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer docs/README.imxmage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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#define __ASSEMBLY__ |
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#include <config.h> |
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/* image version */ |
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IMAGE_VERSION 2 |
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BOOT_FROM sd |
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/* Secure boot support */ |
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#ifdef CONFIG_SECURE_BOOT |
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CSF CONFIG_CSF_SIZE |
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#endif |
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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DATA 4 0x30340004 0x4F400005 |
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/* Clear then set bit30 to ensure exit from DDR retention */ |
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DATA 4 0x30360388 0x40000000 |
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DATA 4 0x30360384 0x40000000 |
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DATA 4 0x30391000 0x00000002 |
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DATA 4 0x307a0000 0x01040001 |
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DATA 4 0x307a01a0 0x80400003 |
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DATA 4 0x307a01a4 0x00100020 |
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DATA 4 0x307a01a8 0x80100004 |
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DATA 4 0x307a0064 0x00400046 |
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DATA 4 0x307a0490 0x00000001 |
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DATA 4 0x307a00d0 0x00020083 |
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DATA 4 0x307a00d4 0x00690000 |
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DATA 4 0x307a00dc 0x09300004 |
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DATA 4 0x307a00e0 0x04080000 |
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DATA 4 0x307a00e4 0x00100004 |
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DATA 4 0x307a00f4 0x0000033f |
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DATA 4 0x307a0100 0x09081109 |
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DATA 4 0x307a0104 0x0007020d |
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DATA 4 0x307a0108 0x03040407 |
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DATA 4 0x307a010c 0x00002006 |
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DATA 4 0x307a0110 0x04020205 |
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DATA 4 0x307a0114 0x03030202 |
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DATA 4 0x307a0120 0x00000803 |
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DATA 4 0x307a0180 0x00800020 |
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DATA 4 0x307a0184 0x02000100 |
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DATA 4 0x307a0190 0x02098204 |
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DATA 4 0x307a0194 0x00030303 |
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DATA 4 0x307a0200 0x00000016 |
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DATA 4 0x307a0204 0x00080808 |
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DATA 4 0x307a0210 0x00000f0f |
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DATA 4 0x307a0214 0x07070707 |
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DATA 4 0x307a0218 0x0f070707 |
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DATA 4 0x307a0240 0x06000604 |
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DATA 4 0x307a0244 0x00000001 |
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DATA 4 0x30391000 0x00000000 |
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DATA 4 0x30790000 0x17420f40 |
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DATA 4 0x30790004 0x10210100 |
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DATA 4 0x30790010 0x00060807 |
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DATA 4 0x307900b0 0x1010007e |
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DATA 4 0x3079009c 0x00000b24 |
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DATA 4 0x30790020 0x08080808 |
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DATA 4 0x30790030 0x08080808 |
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DATA 4 0x30790050 0x01000010 |
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DATA 4 0x30790050 0x00000010 |
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DATA 4 0x307900c0 0x0e407304 |
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DATA 4 0x307900c0 0x0e447304 |
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DATA 4 0x307900c0 0x0e447306 |
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CHECK_BITS_SET 4 0x307900c4 0x1 |
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DATA 4 0x307900c0 0x0e407304 |
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DATA 4 0x30384130 0x00000000 |
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DATA 4 0x30340020 0x00000178 |
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DATA 4 0x30384130 0x00000002 |
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DATA 4 0x30790018 0x0000000f |
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CHECK_BITS_SET 4 0x307a0004 0x1 |
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@ -0,0 +1,289 @@ |
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/*
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* Copyright (C) 2017 NXP Semiconductors |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/clock.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/mx7-pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/mxc_i2c.h> |
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#include <asm/io.h> |
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#include <common.h> |
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#include <fsl_esdhc.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <mmc.h> |
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#include <netdev.h> |
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#include <usb.h> |
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#include <power/pmic.h> |
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#include <power/pfuze3000_pmic.h> |
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#include "../../freescale/common/pfuze.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ |
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) |
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ |
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) |
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) |
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) |
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) |
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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ |
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) |
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#ifdef CONFIG_SYS_I2C_MXC |
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
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/* I2C4 for PMIC */ |
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static struct i2c_pads_info i2c_pad_info4 = { |
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.scl = { |
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.i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC, |
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.gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC, |
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.gp = IMX_GPIO_NR(6, 16), |
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}, |
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.sda = { |
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.i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC, |
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.gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC, |
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.gp = IMX_GPIO_NR(6, 17), |
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}, |
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}; |
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#endif |
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int dram_init(void) |
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{ |
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gd->ram_size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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#ifdef CONFIG_POWER |
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#define I2C_PMIC 3 |
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int power_init_board(void) |
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{ |
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struct pmic *p; |
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int ret; |
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unsigned int reg, rev_id; |
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ret = power_pfuze3000_init(I2C_PMIC); |
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if (ret) |
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return ret; |
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p = pmic_get("PFUZE3000"); |
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ret = pmic_probe(p); |
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if (ret) |
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return ret; |
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pmic_reg_read(p, PFUZE3000_DEVICEID, ®); |
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pmic_reg_read(p, PFUZE3000_REVID, &rev_id); |
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); |
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/* disable Low Power Mode during standby mode */ |
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pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); |
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reg |= 0x1; |
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pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); |
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/* SW1A/1B mode set to APS/APS */ |
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reg = 0x8; |
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pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); |
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pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); |
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/* SW1A/1B standby voltage set to 1.025V */ |
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reg = 0xd; |
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pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); |
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pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); |
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/* decrease SW1B normal voltage to 0.975V */ |
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pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); |
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reg &= ~0x1f; |
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reg |= PFUZE3000_SW1AB_SETP(975); |
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pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); |
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return 0; |
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} |
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#endif |
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static iomux_v3_cfg_t const wdog_pads[] = { |
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const uart5_pads[] = { |
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MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { |
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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#ifdef CONFIG_FEC_MXC |
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static iomux_v3_cfg_t const fec1_pads[] = { |
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MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), |
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MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), |
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11) |
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static void setup_iomux_fec(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); |
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gpio_direction_output(FEC1_RST_GPIO, 0); |
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udelay(500); |
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gpio_set_value(FEC1_RST_GPIO, 1); |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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setup_iomux_fec(); |
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return fecmxc_initialize_multi(bis, 0, |
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CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); |
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} |
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static int setup_fec(void) |
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{ |
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struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs |
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= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
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/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */ |
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], |
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(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | |
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IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); |
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return set_clk_enet(ENET_125MHz); |
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} |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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unsigned short val; |
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/* To enable AR8035 ouput a 125MHz clk from CLK_25M */ |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); |
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); |
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val &= 0xffe7; |
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val |= 0x18; |
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); |
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/* introduce tx clock delay */ |
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); |
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); |
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val |= 0x0100; |
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); |
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if (phydev->drv->config) |
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phydev->drv->config(phydev); |
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return 0; |
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} |
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#endif |
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); |
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} |
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static struct fsl_esdhc_cfg usdhc_cfg[1] = { |
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{USDHC3_BASE_ADDR}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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/* Assume uSDHC3 emmc is always present */ |
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return 1; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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} |
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int board_early_init_f(void) |
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{ |
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setup_iomux_uart(); |
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#ifdef CONFIG_SYS_I2C_MXC |
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setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); |
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#endif |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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#ifdef CONFIG_FEC_MXC |
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setup_fec(); |
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#endif |
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return 0; |
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} |
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int board_late_init(void) |
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{ |
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
||||
|
||||
set_wdog_reset(wdog); |
||||
|
||||
/*
|
||||
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), |
||||
* since we use PMIC_PWRON to reset the board. |
||||
*/ |
||||
clrsetbits_le16(&wdog->wcr, 0, 0x10); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: i.MX7D PICOSOM\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_usb_phy_mode(int port) |
||||
{ |
||||
return USB_INIT_DEVICE; |
||||
} |
||||
@ -0,0 +1,35 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX7=y |
||||
CONFIG_TARGET_PICO_IMX7D=y |
||||
CONFIG_IMX_RDC=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage.cfg" |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_BOOTD is not set |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_PART=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_MXC_USB_OTG_HACTIVE=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_CI_UDC=y |
||||
CONFIG_USB_GADGET_DOWNLOAD=y |
||||
CONFIG_G_DNL_MANUFACTURER="FSL" |
||||
CONFIG_G_DNL_VENDOR_NUM=0x0525 |
||||
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 |
||||
CONFIG_OF_LIBFDT=y |
||||
@ -0,0 +1,143 @@ |
||||
/*
|
||||
* Copyright (C) 2017 NXP Semiconductors |
||||
* |
||||
* Configuration settings for the i.MX7D Pico board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __PICO_IMX7D_CONFIG_H |
||||
#define __PICO_IMX7D_CONFIG_H |
||||
|
||||
#include "mx7_common.h" |
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_1G |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) |
||||
|
||||
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR |
||||
|
||||
/* Network */ |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_MII |
||||
#define CONFIG_FEC_XCV_TYPE RGMII |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
#define CONFIG_FEC_MXC_PHYADDR 1 |
||||
|
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_ATHEROS |
||||
|
||||
/* ENET1 */ |
||||
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR |
||||
|
||||
/* MMC Config */ |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ |
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc4\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx7d-pico.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"finduuid=part uuid mmc 0:2 uuid\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=PARTUUID=${uuid} rootwait rw\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run finduuid; " \
|
||||
"run mmcargs; " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi;\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"if mmc rescan; then " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi" |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* I2C configs */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_MXC_I2C1 |
||||
#define CONFIG_SYS_I2C_MXC_I2C2 |
||||
#define CONFIG_SYS_I2C_MXC_I2C3 |
||||
#define CONFIG_SYS_I2C_MXC_I2C4 |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
/* PMIC */ |
||||
#define CONFIG_POWER |
||||
#define CONFIG_POWER_I2C |
||||
#define CONFIG_POWER_PFUZE3000 |
||||
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_ENV_SIZE SZ_8K |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
|
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K) |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2 |
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_SYS_MMC_ENV_PART 0 |
||||
|
||||
/* USB Configs */ |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
|
||||
#define CONFIG_IMX_THERMAL |
||||
|
||||
#define CONFIG_USB_FUNCTION_MASS_STORAGE |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue