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@ -26,10 +26,15 @@ |
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#include <pci.h> |
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#include <asm/processor.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/immap_fsl_pci.h> |
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#include <spd.h> |
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#include <i2c.h> |
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#include <ioports.h> |
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#if defined(CONFIG_OF_FLAT_TREE) |
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#include <ft_build.h> |
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#endif |
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#include "bcsr.h" |
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const qe_iop_conf_t qe_iop_conf_tab[] = { |
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@ -336,16 +341,19 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = { |
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}; |
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#endif |
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static struct pci_controller hose[] = { |
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{ |
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static struct pci_controller pci1_hose = { |
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#ifndef CONFIG_PCI_PNP |
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config_table: pci_mpc8568mds_config_table, |
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#endif |
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} |
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}; |
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#endif /* CONFIG_PCI */ |
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#ifdef CONFIG_PCIE1 |
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static struct pci_controller pcie1_hose; |
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#endif /* CONFIG_PCIE1 */ |
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int first_free_busno = 0; |
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/*
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* pib_init() -- Initialize the PCA9555 IO expander on the PIB board |
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*/ |
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@ -388,11 +396,170 @@ pib_init(void) |
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asm("eieio"); |
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} |
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#ifdef CONFIG_PCI |
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void |
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pci_init_board(void) |
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{ |
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#ifdef CONFIG_PCI |
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; |
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
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#ifdef CONFIG_PCI1 |
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{ |
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pib_init(); |
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pci_mpc85xx_init(hose); |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; |
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extern void fsl_pci_init(struct pci_controller *hose); |
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struct pci_controller *hose = &pci1_hose; |
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uint pci_32 = 1; /* PORDEVSR[15] */ |
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ |
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ |
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uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); |
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uint pci_speed = 66666000; |
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if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { |
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printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", |
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(pci_32) ? 32 : 64, |
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(pci_speed == 33333000) ? "33" : |
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(pci_speed == 66666000) ? "66" : "unknown", |
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pci_clk_sel ? "sync" : "async", |
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pci_agent ? "agent" : "host", |
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pci_arb ? "arbiter" : "external-arbiter" |
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); |
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/* inbound */ |
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pci_set_region(hose->regions + 0, |
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CFG_PCI_MEMORY_BUS, |
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CFG_PCI_MEMORY_PHYS, |
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CFG_PCI_MEMORY_SIZE, |
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PCI_REGION_MEM | PCI_REGION_MEMORY); |
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/* outbound memory */ |
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pci_set_region(hose->regions + 1, |
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CFG_PCI1_MEM_BASE, |
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CFG_PCI1_MEM_PHYS, |
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CFG_PCI1_MEM_SIZE, |
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PCI_REGION_MEM); |
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/* outbound io */ |
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pci_set_region(hose->regions + 2, |
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CFG_PCI1_IO_BASE, |
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CFG_PCI1_IO_PHYS, |
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CFG_PCI1_IO_SIZE, |
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PCI_REGION_IO); |
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hose->region_count = 3; |
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hose->first_busno = first_free_busno; |
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
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fsl_pci_init(hose); |
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first_free_busno = hose->last_busno+1; |
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printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); |
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} else { |
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printf (" PCI: disabled\n"); |
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} |
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} |
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#else |
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ |
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#endif |
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#ifdef CONFIG_PCIE1 |
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{ |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; |
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extern void fsl_pci_init(struct pci_controller *hose); |
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struct pci_controller *hose = &pcie1_hose; |
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int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); |
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int pcie_configured = io_sel >= 1; |
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if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ |
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printf ("\n PCIE connected to slot as %s (base address %x)", |
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pcie_ep ? "End Point" : "Root Complex", |
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(uint)pci); |
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if (pci->pme_msg_det) { |
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pci->pme_msg_det = 0xffffffff; |
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); |
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} |
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printf ("\n"); |
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/* inbound */ |
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pci_set_region(hose->regions + 0, |
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CFG_PCI_MEMORY_BUS, |
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CFG_PCI_MEMORY_PHYS, |
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CFG_PCI_MEMORY_SIZE, |
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PCI_REGION_MEM | PCI_REGION_MEMORY); |
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/* outbound memory */ |
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pci_set_region(hose->regions + 1, |
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CFG_PCIE1_MEM_BASE, |
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CFG_PCIE1_MEM_PHYS, |
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CFG_PCIE1_MEM_SIZE, |
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PCI_REGION_MEM); |
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/* outbound io */ |
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pci_set_region(hose->regions + 2, |
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CFG_PCIE1_IO_BASE, |
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CFG_PCIE1_IO_PHYS, |
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CFG_PCIE1_IO_SIZE, |
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PCI_REGION_IO); |
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hose->region_count = 3; |
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hose->first_busno=first_free_busno; |
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
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fsl_pci_init(hose); |
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printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); |
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first_free_busno=hose->last_busno+1; |
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} else { |
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printf (" PCIE: disabled\n"); |
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} |
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} |
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#else |
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
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#endif |
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} |
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#endif /* CONFIG_PCI */ |
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#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) |
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void |
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ft_board_setup(void *blob, bd_t *bd) |
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{ |
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u32 *p; |
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int len; |
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ft_cpu_setup(blob, bd); |
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p = ft_get_prop(blob, "/memory/reg", &len); |
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if (p != NULL) { |
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*p++ = cpu_to_be32(bd->bi_memstart); |
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*p = cpu_to_be32(bd->bi_memsize); |
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} |
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#ifdef CONFIG_PCI1 |
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); |
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if (p != NULL) { |
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p[0] = 0; |
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p[1] = pci1_hose.last_busno - pci1_hose.first_busno; |
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debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); |
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} |
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#endif |
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#ifdef CONFIG_PCIE1 |
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); |
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if (p != NULL) { |
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p[0] = 0; |
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p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; |
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debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); |
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} |
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#endif |
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} |
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#endif |
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