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@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc) |
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int board_mmc_init(bd_t *bis) |
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{ |
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#ifndef CONFIG_SPL_BUILD |
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int i, ret; |
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/*
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@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis) |
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} |
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return 0; |
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#else |
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struct src *src_regs = (struct src *)SRC_BASE_ADDR; |
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u32 val; |
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u32 port; |
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val = readl(&src_regs->sbmr1); |
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if ((val & 0xc0) != 0x40) { |
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printf("Not boot from USDHC!\n"); |
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return -EINVAL; |
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} |
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port = (val >> 11) & 0x3; |
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printf("port %d\n", port); |
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switch (port) { |
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case 1: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
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usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; |
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break; |
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case 2: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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gpio_direction_input(USDHC3_CD_GPIO); |
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gpio_direction_output(USDHC3_PWR_GPIO, 1); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
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break; |
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case 3: |
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imx_iomux_v3_setup_multiple_pads( |
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
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gpio_direction_input(USDHC4_CD_GPIO); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
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usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; |
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break; |
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} |
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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#endif |
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} |
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#ifdef CONFIG_FSL_QSPI |
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@ -429,3 +471,129 @@ int checkboard(void) |
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return 0; |
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} |
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#ifdef CONFIG_SPL_BUILD |
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#include <libfdt.h> |
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#include <spl.h> |
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#include <asm/arch/mx6-ddr.h> |
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const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { |
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.dram_dqm0 = 0x00000028, |
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.dram_dqm1 = 0x00000028, |
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.dram_dqm2 = 0x00000028, |
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.dram_dqm3 = 0x00000028, |
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.dram_ras = 0x00000020, |
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.dram_cas = 0x00000020, |
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.dram_odt0 = 0x00000020, |
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.dram_odt1 = 0x00000020, |
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.dram_sdba2 = 0x00000000, |
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.dram_sdcke0 = 0x00003000, |
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.dram_sdcke1 = 0x00003000, |
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.dram_sdclk_0 = 0x00000030, |
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.dram_sdqs0 = 0x00000028, |
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.dram_sdqs1 = 0x00000028, |
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.dram_sdqs2 = 0x00000028, |
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.dram_sdqs3 = 0x00000028, |
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.dram_reset = 0x00000020, |
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}; |
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const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { |
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.grp_addds = 0x00000020, |
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.grp_ddrmode_ctl = 0x00020000, |
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.grp_ddrpke = 0x00000000, |
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.grp_ddrmode = 0x00020000, |
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.grp_b0ds = 0x00000028, |
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.grp_b1ds = 0x00000028, |
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.grp_ctlds = 0x00000020, |
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.grp_ddr_type = 0x000c0000, |
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.grp_b2ds = 0x00000028, |
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.grp_b3ds = 0x00000028, |
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}; |
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const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
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.p0_mpwldectrl0 = 0x00290025, |
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.p0_mpwldectrl1 = 0x00220022, |
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.p0_mpdgctrl0 = 0x41480144, |
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.p0_mpdgctrl1 = 0x01340130, |
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.p0_mprddlctl = 0x3C3E4244, |
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.p0_mpwrdlctl = 0x34363638, |
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}; |
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static struct mx6_ddr3_cfg mem_ddr = { |
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.mem_speed = 1600, |
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.density = 4, |
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.width = 32, |
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.banks = 8, |
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.rowaddr = 15, |
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.coladdr = 10, |
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.pagesz = 2, |
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.trcd = 1375, |
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.trcmin = 4875, |
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.trasmin = 3500, |
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}; |
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static void ccgr_init(void) |
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{ |
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
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writel(0xFFFFFFFF, &ccm->CCGR0); |
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writel(0xFFFFFFFF, &ccm->CCGR1); |
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writel(0xFFFFFFFF, &ccm->CCGR2); |
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writel(0xFFFFFFFF, &ccm->CCGR3); |
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writel(0xFFFFFFFF, &ccm->CCGR4); |
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writel(0xFFFFFFFF, &ccm->CCGR5); |
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writel(0xFFFFFFFF, &ccm->CCGR6); |
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writel(0xFFFFFFFF, &ccm->CCGR7); |
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} |
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static void spl_dram_init(void) |
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{ |
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struct mx6_ddr_sysinfo sysinfo = { |
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.dsize = mem_ddr.width/32, |
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.cs_density = 24, |
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.ncs = 1, |
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.cs1_mirror = 0, |
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.rtt_wr = 2, |
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.rtt_nom = 2, /* RTT_Nom = RZQ/2 */ |
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.walat = 1, /* Write additional latency */ |
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.ralat = 5, /* Read additional latency */ |
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.mif3_mode = 3, /* Command prediction working mode */ |
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.bi_on = 1, /* Bank interleaving enabled */ |
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
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}; |
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mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
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} |
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void board_init_f(ulong dummy) |
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{ |
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/* setup AIPS and disable watchdog */ |
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arch_cpu_init(); |
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ccgr_init(); |
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/* iomux and setup of i2c */ |
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board_early_init_f(); |
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/* setup GP timer */ |
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timer_init(); |
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/* UART clocks enabled and gd valid - init serial console */ |
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preloader_console_init(); |
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/* DDR initialization */ |
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spl_dram_init(); |
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/* Clear the BSS. */ |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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/* load/boot image from boot device */ |
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board_init_r(NULL, 0); |
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} |
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void reset_cpu(ulong addr) |
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{ |
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} |
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#endif |
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