Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

ppc4xx: Change DDR2 CL from 4 to 5 for intip

Browse Source 
Some intip boards don't seem to run stable with CL4, datasheets suggest that
CL5 is the safe value.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
master
Dirk Eibach 14 years ago committed by Stefan Roese
parent 97ca7b3b8e
commit 15cc385e68
1 changed files with 6 additions and 6 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 12
      include/configs/intip.h

12
include/configs/intip.h
Unescape View File

@ -37,10 +37,10 @@
#define CONFIG_460EX 1 /* Specific PPC460EX */
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_HOSTNAME devconcenter
#define CONFIG_IDENT_STRING " devconcenter 0.03"
#define CONFIG_IDENT_STRING " devconcenter 0.05"
#else
#define CONFIG_HOSTNAME intip
#define CONFIG_IDENT_STRING " intip 0.03"
#define CONFIG_IDENT_STRING " intip 0.05"
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
@ -200,13 +200,13 @@
#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002
#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542
#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552
#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452
#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382
#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002
#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
@ -216,11 +216,11 @@
#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
#define CONFIG_SYS_SDRAM0_WRDTR 0x84000823
#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823
#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15
#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
#define CONFIG_SYS_SDRAM0_MMODE 0x00000452
#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002
#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */

Write Preview
Loading…
Cancel
Save