The LCDC controller on the lcdk board has high memory throughput requirements. Even with the kernel-side tweaks to master peripheral and peripheral bus burst priorities, the default PLL0 frquency of 300 MHz is not enough to service the LCD controller and causes DMA FIFO underflows. Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of 456 MHz - the same value that downstream reference u-boot from Texas Instruments uses. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>master
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