@ -28,14 +28,11 @@
# define USBCTRL_OTGBASE_OFFSET 0x600
# ifdef CONFIG_MX25
# define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
# define MX25_USB_CTRL_HSTD_BIT (1<<5)
# define MX25_USB_CTRL_USBTE_BIT (1<<4)
# define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
# endif
# ifdef CONFIG_MX31
# define MX31_OTG_SIC_SHIFT 29
# define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
# define MX31_OTG_PM_BIT (1 << 24)
@ -49,59 +46,56 @@
# define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
# define MX31_H1_PM_BIT (1 << 8)
# define MX31_H1_DT_BIT (1 << 4)
# endif
static int mxc_set_usbcontrol ( int port , unsigned int flags )
{
unsigned int v ;
# ifdef CONFIG_MX25
# if defined(CONFIG_MX25)
v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT ;
# endif
# elif defined(CONFIG_MX31)
v = readl ( IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET ) ;
# ifdef CONFIG_MX31
v = readl ( IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET ) ;
switch ( port ) {
case 0 : /* OTG port */
v & = ~ ( MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT ) ;
v | = ( flags & MXC_EHCI_INTERFACE_MASK )
< < MX31_OTG_SIC_SHIFT ;
if ( ! ( flags & MXC_EHCI_POWER_PINS_ENABLED ) )
v | = MX31_OTG_PM_BIT ;
break ;
case 1 : /* H1 port */
v & = ~ ( MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
MX31_H1_DT_BIT ) ;
v | = ( flags & MXC_EHCI_INTERFACE_MASK )
< < MX31_H1_SIC_SHIFT ;
if ( ! ( flags & MXC_EHCI_POWER_PINS_ENABLED ) )
v | = MX31_H1_PM_BIT ;
if ( ! ( flags & MXC_EHCI_TTL_ENABLED ) )
v | = MX31_H1_DT_BIT ;
break ;
case 2 : /* H2 port */
v & = ~ ( MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
MX31_H2_DT_BIT ) ;
v | = ( flags & MXC_EHCI_INTERFACE_MASK )
< < MX31_H2_SIC_SHIFT ;
if ( ! ( flags & MXC_EHCI_POWER_PINS_ENABLED ) )
v | = MX31_H2_PM_BIT ;
if ( ! ( flags & MXC_EHCI_TTL_ENABLED ) )
v | = MX31_H2_DT_BIT ;
break ;
default :
return - EINVAL ;
}
# endif
switch ( port ) {
case 0 : /* OTG port */
v & = ~ ( MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT ) ;
v | = ( flags & MXC_EHCI_INTERFACE_MASK ) < < MX31_OTG_SIC_SHIFT ;
if ( ! ( flags & MXC_EHCI_POWER_PINS_ENABLED ) )
v | = MX31_OTG_PM_BIT ;
break ;
case 1 : /* H1 port */
v & = ~ ( MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT ) ;
v | = ( flags & MXC_EHCI_INTERFACE_MASK ) < < MX31_H1_SIC_SHIFT ;
if ( ! ( flags & MXC_EHCI_POWER_PINS_ENABLED ) )
v | = MX31_H1_PM_BIT ;
if ( ! ( flags & MXC_EHCI_TTL_ENABLED ) )
v | = MX31_H1_DT_BIT ;
break ;
case 2 : /* H2 port */
v & = ~ ( MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT ) ;
v | = ( flags & MXC_EHCI_INTERFACE_MASK ) < < MX31_H2_SIC_SHIFT ;
if ( ! ( flags & MXC_EHCI_POWER_PINS_ENABLED ) )
v | = MX31_H2_PM_BIT ;
if ( ! ( flags & MXC_EHCI_TTL_ENABLED ) )
v | = MX31_H2_DT_BIT ;
break ;
default :
return - EINVAL ;
}
# else
# error MXC EHCI USB driver not supported on this platform
# endif
writel ( v , IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET ) ;
return 0 ;
}