Wolfgang Denk
15 years ago
commit
16909f34b7
@ -0,0 +1,324 @@ |
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/*
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* arch/arm/include/asm/arch-pxa/macro.h |
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* |
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#ifndef __ASM_ARCH_PXA_MACRO_H__ |
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#define __ASM_ARCH_PXA_MACRO_H__ |
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#ifdef __ASSEMBLY__ |
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#include <asm/macro.h> |
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#include <asm/arch/pxa-regs.h> |
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|
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/*
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* This macro performs a 32bit write to a memory location and makes sure the |
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* write operation really happened by performing a read back. |
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* |
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* Clobbered regs: r4, r5 |
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*/ |
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.macro write32rb addr, data |
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ldr r4, =\addr |
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ldr r5, =\data |
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str r5, [r4] |
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ldr r5, [r4] |
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.endm |
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|
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/*
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* This macro waits according to OSCR incrementation |
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* |
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* Clobbered regs: r4, r5, r6 |
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*/ |
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.macro pxa_wait_ticks ticks |
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ldr r4, =OSCR |
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mov r5, #0 |
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str r5, [r4] |
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ldr r5, =\ticks |
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1: |
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ldr r6, [r4] |
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cmp r5, r6 |
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bgt 1b |
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.endm |
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|
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/*
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* This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU |
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* |
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* Clobbered regs: r4, r5 |
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*/ |
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.macro pxa_gpio_setup |
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write32 GPSR0, CONFIG_SYS_GPSR0_VAL |
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write32 GPSR1, CONFIG_SYS_GPSR1_VAL |
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write32 GPSR2, CONFIG_SYS_GPSR2_VAL |
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) |
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write32 GPSR3, CONFIG_SYS_GPSR3_VAL |
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#endif |
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write32 GPCR0, CONFIG_SYS_GPCR0_VAL |
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write32 GPCR1, CONFIG_SYS_GPCR1_VAL |
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write32 GPCR2, CONFIG_SYS_GPCR2_VAL |
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) |
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write32 GPCR3, CONFIG_SYS_GPCR3_VAL |
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#endif |
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|
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write32 GPDR0, CONFIG_SYS_GPDR0_VAL |
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write32 GPDR1, CONFIG_SYS_GPDR1_VAL |
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write32 GPDR2, CONFIG_SYS_GPDR2_VAL |
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) |
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write32 GPDR3, CONFIG_SYS_GPDR3_VAL |
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#endif |
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write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL |
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write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL |
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write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL |
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write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL |
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write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL |
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write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL |
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) |
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write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL |
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write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL |
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#endif |
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write32 PSSR, CONFIG_SYS_PSSR_VAL |
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.endm |
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/*
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* This macro sets up the Memory controller of the PXA2xx CPU |
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* |
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* Clobbered regs: r3, r4, r5 |
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*/ |
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.macro pxa_mem_setup |
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/* This comes handy when setting MDREFR */ |
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ldr r3, =MEMC_BASE |
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/*
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* 1) Initialize Asynchronous static memory controller |
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*/ |
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/* MSC0: nCS(0,1) */ |
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write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL |
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/* MSC1: nCS(2,3) */ |
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write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL |
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/* MSC2: nCS(4,5) */ |
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write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL |
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/*
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* 2) Initialize Card Interface |
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*/ |
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/* MECR: Memory Expansion Card Register */ |
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write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL |
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/* MCMEM0: Card Interface slot 0 timing */ |
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write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL |
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/* MCMEM1: Card Interface slot 1 timing */ |
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write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL |
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */ |
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write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL |
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */ |
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write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL |
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */ |
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write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL |
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */ |
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write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL |
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/*
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* 3) Configure Fly-By DMA register |
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*/ |
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write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL |
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/*
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* 4) Initialize Timing for Sync Memory (SDCLK0) |
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*/ |
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/*
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* Before accessing MDREFR we need a valid DRI field, so we set |
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* this to power on defaults + DRI field. |
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*/ |
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ldr r5, [r3, #MDREFR_OFFSET] |
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bic r5, r5, #0x0ff |
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bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ |
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ldr r4, =CONFIG_SYS_MDREFR_VAL |
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mov r6, r4 |
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lsl r4, #20 |
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lsr r4, #20 /* Get a valid DRI field */ |
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orr r5, r5, r4 /* MDREFR user config with correct DRI */ |
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orr r5, #MDREFR_K0RUN |
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orr r5, #MDREFR_SLFRSH |
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bic r5, #MDREFR_APD |
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bic r5, #MDREFR_E1PIN |
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str r5, [r3, #MDREFR_OFFSET] |
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ldr r4, [r3, #MDREFR_OFFSET] |
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/*
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* 5) Initialize Synchronous Static Memory (Flash/Peripherals) |
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*/ |
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/* Initialize SXCNFG register. Assert the enable bits.
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* |
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* Write SXMRS to cause an MRS command to all enabled banks of |
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* synchronous static memory. Note that SXLCR need not be written |
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* at this time. |
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*/ |
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write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL |
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/*
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* 6) Initialize SDRAM |
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*/ |
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bic r6, #MDREFR_SLFRSH |
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str r6, [r3, #MDREFR_OFFSET] |
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ldr r4, [r3, #MDREFR_OFFSET] |
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orr r6, #MDREFR_E1PIN |
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str r6, [r3, #MDREFR_OFFSET] |
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ldr r4, [r3, #MDREFR_OFFSET] |
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/*
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* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure |
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* but not enable each SDRAM partition pair. |
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*/ |
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/* Fetch platform value of MDCNFG */ |
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ldr r4, =CONFIG_SYS_MDCNFG_VAL |
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/* Disable all sdram banks */ |
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bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) |
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bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) |
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/* Write initial value of MDCNFG, w/o enabling sdram banks */ |
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str r4, [r3, #MDCNFG_OFFSET] |
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ldr r4, [r3, #MDCNFG_OFFSET] |
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/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ |
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pxa_wait_ticks 0x300 |
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/*
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* 8) Trigger a number (usually 8) refresh cycles by attempting |
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* non-burst read or write accesses to disabled SDRAM, as commonly |
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* specified in the power up sequence documented in SDRAM data |
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* sheets. The address(es) used for this purpose must not be |
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* cacheable. |
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*/ |
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ldr r4, =CONFIG_SYS_DRAM_BASE |
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.rept 9 |
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str r5, [r4] |
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.endr |
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/*
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* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). |
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*/ |
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ldr r5, =CONFIG_SYS_MDCNFG_VAL |
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ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3) |
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and r5, r5, r4 |
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ldr r4, [r3, #MDCNFG_OFFSET] |
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orr r4, r4, r5 |
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str r4, [r3, #MDCNFG_OFFSET] |
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ldr r4, [r3, #MDCNFG_OFFSET] |
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/*
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* 10) Write MDMRS. |
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*/ |
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ldr r4, =CONFIG_SYS_MDMRS_VAL |
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str r4, [r3, #MDMRS_OFFSET] |
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ldr r4, [r3, #MDMRS_OFFSET] |
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/*
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* 11) Enable APD |
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*/ |
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ldr r4, [r3, #MDREFR_OFFSET] |
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and r6, r6, #MDREFR_APD |
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orr r4, r4, r6 |
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str r4, [r3, #MDREFR_OFFSET] |
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ldr r4, [r3, #MDREFR_OFFSET] |
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.endm |
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/*
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* This macro tests if the CPU woke up from sleep and eventually resumes |
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* |
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* Clobbered regs: r4, r5 |
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*/ |
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.macro pxa_wakeup |
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ldr r4, =RCSR |
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ldr r5, [r4] |
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and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) |
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str r5, [r4] |
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teq r5, #RCSR_SMR |
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bne pxa_wakeup_exit |
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ldr r4, =PSSR |
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mov r5, #PSSR_PH |
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str r5, [r4] |
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ldr r4, =PSPR |
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ldr pc, [r4] |
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pxa_wakeup_exit: |
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.endm |
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/*
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* This macro disables all interupts on PXA2xx/PXA3xx CPU |
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* |
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* Clobbered regs: r4, r5 |
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*/ |
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.macro pxa_intr_setup |
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write32 ICLR, 0 |
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write32 ICMR, 0 |
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) |
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write32 ICLR2, 0 |
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write32 ICMR2, 0 |
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#endif |
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.endm |
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/*
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* This macro configures clock on PXA2xx/PXA3xx CPU |
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* |
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* Clobbered regs: r4, r5 |
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*/ |
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.macro pxa_clock_setup |
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/* Disable the peripheral clocks, and set the core clock frequency */ |
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/* Turn Off ALL on-chip peripheral clocks for re-configuration */ |
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write32 CKEN, CONFIG_SYS_CKEN |
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/* Write CCCR */ |
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write32 CCCR, CONFIG_SYS_CCCR |
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#ifdef CONFIG_RTC |
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/* enable the 32Khz oscillator for RTC and PowerManager */ |
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write32 OSCC, #OSCC_OON |
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ldr r4, =OSCC |
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/* Spin here until OSCC.OOK get set, meaning the PLL has settled. */ |
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2: |
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ldr r5, [r4] |
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ands r5, r5, #1 |
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beq 2b |
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#endif |
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.endm |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __ASM_ARCH_PXA_MACRO_H__ */ |
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@ -0,0 +1,45 @@ |
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#
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# Toradex Colibri PXA270 Support
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#
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# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := colibri_pxa270.o
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SOBJS := lowlevel_init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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|
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-include .depend |
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#########################################################################
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@ -0,0 +1,118 @@ |
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/*
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* Toradex Colibri PXA270 Support |
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* |
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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/* ------------------------------------------------------------------------- */ |
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|
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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extern struct serial_device serial_ffuart_device; |
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extern struct serial_device serial_btuart_device; |
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extern struct serial_device serial_stuart_device; |
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|
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struct serial_device *default_serial_console (void) |
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{ |
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return &serial_ffuart_device; |
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} |
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|
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int board_init (void) |
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{ |
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/* memory and cpu-speed are setup before relocation */ |
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/* so we do _nothing_ here */ |
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|
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/* arch number of vpac270 */ |
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gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; |
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|
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = 0xa0000100; |
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return 0; |
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} |
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int dram_init (void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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return 0; |
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} |
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|
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#ifdef CONFIG_CMD_USB |
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int usb_board_init(void) |
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{ |
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UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); |
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|
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UHCHR |= UHCHR_FSBIR; |
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|
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while (UHCHR & UHCHR_FSBIR); |
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|
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UHCHR &= ~UHCHR_SSE; |
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UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); |
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|
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/* Clear any OTG Pin Hold */ |
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if (PSSR & PSSR_OTGPH) |
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PSSR |= PSSR_OTGPH; |
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|
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UHCRHDA &= ~(0x200); |
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UHCRHDA |= 0x100; |
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|
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/* Set port power control mask bits, only 3 ports. */ |
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UHCRHDB |= (0x7<<17); |
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|
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/* enable port 2 */ |
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UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; |
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|
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return 0; |
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} |
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|
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void usb_board_init_fail(void) |
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{ |
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return; |
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} |
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|
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void usb_board_stop(void) |
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{ |
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UHCHR |= UHCHR_FHR; |
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udelay(11); |
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UHCHR &= ~UHCHR_FHR; |
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|
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UHCCOMS |= 1; |
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udelay(10); |
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|
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CKEN &= ~CKEN10_USBHOST; |
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|
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return; |
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} |
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#endif |
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|
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#ifdef CONFIG_DRIVER_DM9000 |
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int board_eth_init(bd_t *bis) |
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{ |
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return dm9000_initialize(bis); |
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} |
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#endif |
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@ -0,0 +1 @@ |
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TEXT_BASE = 0xa1000000
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@ -0,0 +1,36 @@ |
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/* |
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* Toradex Colibri PXA270 Lowlevel Hardware Initialization |
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* |
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
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* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
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#include <config.h> |
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#include <version.h> |
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#include <asm/arch/pxa-regs.h> |
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#include <asm/arch/macro.h> |
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|
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.globl lowlevel_init
|
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lowlevel_init: |
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pxa_gpio_setup |
||||
pxa_wait_ticks 0x8000 |
||||
pxa_mem_setup |
||||
pxa_wakeup |
||||
pxa_intr_setup |
||||
pxa_clock_setup |
||||
|
||||
mov pc, lr |
||||
@ -0,0 +1,48 @@ |
||||
|
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := vpac270.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1 @@ |
||||
TEXT_BASE = 0xa1000000
|
||||
@ -0,0 +1,40 @@ |
||||
/* |
||||
* Voipac PXA270 Lowlevel Hardware Initialization |
||||
* |
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
* |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/arch/pxa-regs.h> |
||||
#include <asm/arch/macro.h> |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
pxa_gpio_setup |
||||
pxa_wait_ticks 0x8000 |
||||
pxa_mem_setup |
||||
pxa_wakeup |
||||
pxa_intr_setup |
||||
pxa_clock_setup |
||||
|
||||
mov pc, lr |
||||
@ -0,0 +1,55 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/pxa/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,127 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/hardware.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations |
||||
*/ |
||||
extern struct serial_device serial_ffuart_device; |
||||
extern struct serial_device serial_btuart_device; |
||||
extern struct serial_device serial_stuart_device; |
||||
|
||||
struct serial_device *default_serial_console (void) |
||||
{ |
||||
return &serial_ffuart_device; |
||||
} |
||||
|
||||
int board_init (void) |
||||
{ |
||||
/* memory and cpu-speed are setup before relocation */ |
||||
/* so we do _nothing_ here */ |
||||
|
||||
/* arch number of vpac270 */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_VPAC270; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0xa0000100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init (void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
||||
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int usb_board_init(void) |
||||
{ |
||||
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); |
||||
|
||||
UHCHR |= UHCHR_FSBIR; |
||||
|
||||
while (UHCHR & UHCHR_FSBIR); |
||||
|
||||
UHCHR &= ~UHCHR_SSE; |
||||
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); |
||||
|
||||
/* Clear any OTG Pin Hold */ |
||||
if (PSSR & PSSR_OTGPH) |
||||
PSSR |= PSSR_OTGPH; |
||||
|
||||
UHCRHDA &= ~(0x200); |
||||
UHCRHDA |= 0x100; |
||||
|
||||
/* Set port power control mask bits, only 3 ports. */ |
||||
UHCRHDB |= (0x7<<17); |
||||
|
||||
/* enable port 2 */ |
||||
UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void usb_board_init_fail(void) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
void usb_board_stop(void) |
||||
{ |
||||
UHCHR |= UHCHR_FHR; |
||||
udelay(11); |
||||
UHCHR &= ~UHCHR_FHR; |
||||
|
||||
UHCCOMS |= 1; |
||||
udelay(10); |
||||
|
||||
CKEN &= ~CKEN10_USBHOST; |
||||
|
||||
return; |
||||
} |
||||
|
||||
#ifdef CONFIG_DRIVER_DM9000 |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return dm9000_initialize(bis); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,54 @@ |
||||
|
||||
#
|
||||
# Copyright (C) 2009
|
||||
# Marek Vasut <marek.vasut@gmail.com>
|
||||
#
|
||||
# Heavily based on pxa255_idp platform
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := zipitz2.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1 @@ |
||||
TEXT_BASE = 0xa1000000
|
||||
@ -0,0 +1,40 @@ |
||||
/* |
||||
* Aeronix Zipit Z2 Lowlevel Hardware Initialization |
||||
* |
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
* |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/arch/pxa-regs.h> |
||||
#include <asm/arch/macro.h> |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
pxa_gpio_setup |
||||
pxa_wait_ticks 0x8000 |
||||
pxa_mem_setup |
||||
pxa_wakeup |
||||
pxa_intr_setup |
||||
pxa_clock_setup |
||||
|
||||
mov pc, lr |
||||
@ -0,0 +1,56 @@ |
||||
/* |
||||
* (C) Copyright 2000-2005 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/pxa/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,213 @@ |
||||
/*
|
||||
* Copyright (C) 2009 |
||||
* Marek Vasut <marek.vasut@gmail.com> |
||||
* |
||||
* Heavily based on pxa255_idp platform |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <serial.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <spi.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_CMD_SPI |
||||
void lcd_start(void); |
||||
#else |
||||
inline void lcd_start(void) {}; |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
/* memory and cpu-speed are setup before relocation */ |
||||
/* so we do _nothing_ here */ |
||||
|
||||
/* arch number of Lubbock-Board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0xa0000100; |
||||
|
||||
/* Enable LCD */ |
||||
lcd_start(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
setenv("stdout", "serial"); |
||||
setenv("stderr", "serial"); |
||||
return 0; |
||||
} |
||||
|
||||
struct serial_device *default_serial_console (void) |
||||
{ |
||||
return &serial_stuart_device; |
||||
} |
||||
|
||||
int dram_init (void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_SPI |
||||
|
||||
struct { |
||||
unsigned char reg; |
||||
unsigned short data; |
||||
unsigned char mdelay; |
||||
} lcd_data[] = { |
||||
{ 0x07, 0x0000, 0 }, |
||||
{ 0x13, 0x0000, 10 }, |
||||
{ 0x11, 0x3004, 0 }, |
||||
{ 0x14, 0x200F, 0 }, |
||||
{ 0x10, 0x1a20, 0 }, |
||||
{ 0x13, 0x0040, 50 }, |
||||
{ 0x13, 0x0060, 0 }, |
||||
{ 0x13, 0x0070, 200 }, |
||||
{ 0x01, 0x0127, 0 }, |
||||
{ 0x02, 0x0700, 0 }, |
||||
{ 0x03, 0x1030, 0 }, |
||||
{ 0x08, 0x0208, 0 }, |
||||
{ 0x0B, 0x0620, 0 }, |
||||
{ 0x0C, 0x0110, 0 }, |
||||
{ 0x30, 0x0120, 0 }, |
||||
{ 0x31, 0x0127, 0 }, |
||||
{ 0x32, 0x0000, 0 }, |
||||
{ 0x33, 0x0503, 0 }, |
||||
{ 0x34, 0x0727, 0 }, |
||||
{ 0x35, 0x0124, 0 }, |
||||
{ 0x36, 0x0706, 0 }, |
||||
{ 0x37, 0x0701, 0 }, |
||||
{ 0x38, 0x0F00, 0 }, |
||||
{ 0x39, 0x0F00, 0 }, |
||||
{ 0x40, 0x0000, 0 }, |
||||
{ 0x41, 0x0000, 0 }, |
||||
{ 0x42, 0x013f, 0 }, |
||||
{ 0x43, 0x0000, 0 }, |
||||
{ 0x44, 0x013f, 0 }, |
||||
{ 0x45, 0x0000, 0 }, |
||||
{ 0x46, 0xef00, 0 }, |
||||
{ 0x47, 0x013f, 0 }, |
||||
{ 0x48, 0x0000, 0 }, |
||||
{ 0x07, 0x0015, 30 }, |
||||
{ 0x07, 0x0017, 0 }, |
||||
{ 0x20, 0x0000, 0 }, |
||||
{ 0x21, 0x0000, 0 }, |
||||
{ 0x22, 0x0000, 0 }, |
||||
}; |
||||
|
||||
void zipitz2_spi_sda(int set) |
||||
{ |
||||
/* GPIO 13 */ |
||||
if (set) |
||||
GPSR0 = (1 << 13); |
||||
else |
||||
GPCR0 = (1 << 13); |
||||
} |
||||
|
||||
void zipitz2_spi_scl(int set) |
||||
{ |
||||
/* GPIO 22 */ |
||||
if (set) |
||||
GPCR0 = (1 << 22); |
||||
else |
||||
GPSR0 = (1 << 22); |
||||
} |
||||
|
||||
unsigned char zipitz2_spi_read(void) |
||||
{ |
||||
/* GPIO 40 */ |
||||
return !!(GPLR1 & (1 << 8)); |
||||
} |
||||
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
||||
{ |
||||
/* Always valid */ |
||||
return 1; |
||||
} |
||||
|
||||
void spi_cs_activate(struct spi_slave *slave) |
||||
{ |
||||
/* GPIO 88 low */ |
||||
GPCR2 = (1 << 24); |
||||
} |
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave) |
||||
{ |
||||
/* GPIO 88 high */ |
||||
GPSR2 = (1 << 24); |
||||
|
||||
} |
||||
|
||||
void lcd_start(void) |
||||
{ |
||||
int i; |
||||
unsigned char reg[3] = { 0x74, 0x00, 0 }; |
||||
unsigned char data[3] = { 0x76, 0, 0 }; |
||||
unsigned char dummy[3] = { 0, 0, 0 }; |
||||
|
||||
/* PWM2 AF */ |
||||
GAFR0_L |= 0x00800000; |
||||
/* Enable clock to all PWM */ |
||||
CKEN |= 0x3; |
||||
/* Configure PWM2 */ |
||||
PWM_CTRL2 = 0x4f; |
||||
PWM_PWDUTY2 = 0x2ff; |
||||
PWM_PERVAL2 = 792; |
||||
|
||||
/* Toggle the reset pin to reset the LCD */ |
||||
GPSR0 = (1 << 19); |
||||
udelay(100000); |
||||
GPCR0 = (1 << 19); |
||||
udelay(20000); |
||||
GPSR0 = (1 << 19); |
||||
udelay(20000); |
||||
|
||||
/* Program the LCD init sequence */ |
||||
for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { |
||||
reg[0] = 0x74; |
||||
reg[1] = 0x0; |
||||
reg[2] = lcd_data[i].reg; |
||||
spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); |
||||
|
||||
data[0] = 0x76; |
||||
data[1] = lcd_data[i].data >> 8; |
||||
data[2] = lcd_data[i].data & 0xff; |
||||
spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); |
||||
|
||||
if (lcd_data[i].mdelay) |
||||
udelay(lcd_data[i].mdelay * 1000); |
||||
} |
||||
|
||||
GPSR0 = (1 << 11); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,278 @@ |
||||
/*
|
||||
* Toradex Colibri PXA270 configuration file |
||||
* |
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Board Configuration Options |
||||
*/ |
||||
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ |
||||
#define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */ |
||||
|
||||
#undef BOARD_LATE_INIT |
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT |
||||
#undef CONFIG_USE_IRQ |
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CONFIG_ENV_SIZE 0x4000 |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 |
||||
|
||||
#define CONFIG_ENV_OVERWRITE /* override default environment */ |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"if mmc init && fatload mmc 0 0xa0000000 uImage; then " \
|
||||
"bootm 0xa0000000; " \
|
||||
"fi; " \
|
||||
"if usb reset && fatload usb 0 0xa0000000 uImage; then " \
|
||||
"bootm 0xa0000000; " \
|
||||
"fi; " \
|
||||
"bootm 0x80000;" |
||||
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" |
||||
#define CONFIG_TIMESTAMP |
||||
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
|
||||
#define CONFIG_LZMA /* LZMA compression support */ |
||||
|
||||
/*
|
||||
* Serial Console Configuration |
||||
*/ |
||||
#define CONFIG_PXA_SERIAL |
||||
#define CONFIG_FFUART 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Bootloader Components Configuration |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_ENV |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_CMD_FLASH |
||||
|
||||
/*
|
||||
* Networking Configuration |
||||
* chip on the Voipac PXA270 board |
||||
*/ |
||||
#ifdef CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
|
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_DRIVER_DM9000 1 |
||||
#define CONFIG_DM9000_BASE 0x08000000 |
||||
#define DM9000_IO (CONFIG_DM9000_BASE) |
||||
#define DM9000_DATA (CONFIG_DM9000_BASE + 4) |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#endif |
||||
|
||||
/*
|
||||
* MMC Card Configuration |
||||
*/ |
||||
#ifdef CONFIG_CMD_MMC |
||||
#define CONFIG_MMC |
||||
#define CONFIG_PXA_MMC |
||||
#define CONFIG_SYS_MMC_BASE 0xF0000000 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/*
|
||||
* KGDB |
||||
*/ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* HUSH Shell Configuration |
||||
*/ |
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ |
||||
#else |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#endif |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 |
||||
|
||||
/*
|
||||
* Clock Configuration |
||||
*/ |
||||
#undef CONFIG_SYS_CLKS_IN_HZ |
||||
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ |
||||
#define CONFIG_SYS_CPUSPEED 0x290 /* 520 MHz */ |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*
|
||||
* DRAM Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
||||
|
||||
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ |
||||
#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (0xa1000000) |
||||
|
||||
/*
|
||||
* NOR FLASH |
||||
*/ |
||||
#ifdef CONFIG_CMD_FLASH |
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
|
||||
#else /* No flash */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SYS_ENV_IS_NOWHERE |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x000000 |
||||
#define CONFIG_SYS_MONITOR_LEN 0x40000 |
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
|
||||
/*
|
||||
* GPIO settings |
||||
*/ |
||||
#define CONFIG_SYS_GPSR0_VAL 0x00000000 |
||||
#define CONFIG_SYS_GPSR1_VAL 0x00020000 |
||||
#define CONFIG_SYS_GPSR2_VAL 0x0002C000 |
||||
#define CONFIG_SYS_GPSR3_VAL 0x00000000 |
||||
|
||||
#define CONFIG_SYS_GPCR0_VAL 0x00000000 |
||||
#define CONFIG_SYS_GPCR1_VAL 0x00000000 |
||||
#define CONFIG_SYS_GPCR2_VAL 0x00000000 |
||||
#define CONFIG_SYS_GPCR3_VAL 0x00000000 |
||||
|
||||
#define CONFIG_SYS_GPDR0_VAL 0x08000000 |
||||
#define CONFIG_SYS_GPDR1_VAL 0x0002A981 |
||||
#define CONFIG_SYS_GPDR2_VAL 0x0202FC00 |
||||
#define CONFIG_SYS_GPDR3_VAL 0x00000000 |
||||
|
||||
#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 |
||||
#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010 |
||||
#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A |
||||
#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008 |
||||
#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA |
||||
#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000 |
||||
#define CONFIG_SYS_GAFR3_L_VAL 0x54000300 |
||||
#define CONFIG_SYS_GAFR3_U_VAL 0x00024001 |
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x30 |
||||
|
||||
/*
|
||||
* Clock settings |
||||
*/ |
||||
#define CONFIG_SYS_CKEN 0x00500240 |
||||
#define CONFIG_SYS_CCCR 0x02000290 |
||||
|
||||
/*
|
||||
* Memory settings |
||||
*/ |
||||
#define CONFIG_SYS_MSC0_VAL 0x000095f2 |
||||
#define CONFIG_SYS_MSC1_VAL 0x00007ff4 |
||||
#define CONFIG_SYS_MSC2_VAL 0x00000000 |
||||
#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9 |
||||
#define CONFIG_SYS_MDREFR_VAL 0x2013e01e |
||||
#define CONFIG_SYS_MDMRS_VAL 0x00320032 |
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
||||
#define CONFIG_SYS_SXCNFG_VAL 0x40044004 |
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces |
||||
*/ |
||||
#define CONFIG_SYS_MECR_VAL 0x00000001 |
||||
#define CONFIG_SYS_MCMEM0_VAL 0x00014307 |
||||
#define CONFIG_SYS_MCMEM1_VAL 0x00014307 |
||||
#define CONFIG_SYS_MCATT0_VAL 0x0001c787 |
||||
#define CONFIG_SYS_MCATT1_VAL 0x0001c787 |
||||
#define CONFIG_SYS_MCIO0_VAL 0x0001430f |
||||
#define CONFIG_SYS_MCIO1_VAL 0x0001430f |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
#ifdef CONFIG_CMD_USB |
||||
#define CONFIG_USB_OHCI_NEW |
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT |
||||
#define CONFIG_SYS_USB_OHCI_BOARD_INIT |
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 |
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "tdex270" |
||||
#define CONFIG_USB_STORAGE |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,323 @@ |
||||
/*
|
||||
* Voipac PXA270 configuration file |
||||
* |
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Board Configuration Options |
||||
*/ |
||||
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ |
||||
#define CONFIG_VPAC270 1 /* Voipac PXA270 board */ |
||||
|
||||
#undef BOARD_LATE_INIT |
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT |
||||
#undef CONFIG_USE_IRQ |
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CONFIG_ENV_SIZE 0x4000 |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 |
||||
|
||||
#define CONFIG_ENV_OVERWRITE /* override default environment */ |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
|
||||
"bootm 0xa4000000; " \
|
||||
"fi; " \
|
||||
"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
|
||||
"bootm 0xa4000000; " \
|
||||
"fi; " \
|
||||
"bootm 0x40000;" |
||||
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" |
||||
#define CONFIG_TIMESTAMP |
||||
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
|
||||
#define CONFIG_LZMA /* LZMA compression support */ |
||||
|
||||
/*
|
||||
* Serial Console Configuration |
||||
*/ |
||||
#define CONFIG_PXA_SERIAL |
||||
#define CONFIG_FFUART 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Bootloader Components Configuration |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_ENV |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_USB |
||||
#undef CONFIG_LCD |
||||
#define CONFIG_CMD_IDE |
||||
|
||||
#ifdef CONFIG_ONENAND_U_BOOT |
||||
#undef CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_ONENAND |
||||
#else |
||||
#define CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_ONENAND |
||||
#endif |
||||
|
||||
/*
|
||||
* Networking Configuration |
||||
* chip on the Voipac PXA270 board |
||||
*/ |
||||
#ifdef CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
|
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_DRIVER_DM9000 1 |
||||
#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ |
||||
#define DM9000_IO (CONFIG_DM9000_BASE) |
||||
#define DM9000_DATA (CONFIG_DM9000_BASE + 4) |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#endif |
||||
|
||||
/*
|
||||
* MMC Card Configuration |
||||
*/ |
||||
#ifdef CONFIG_CMD_MMC |
||||
#define CONFIG_MMC |
||||
#define CONFIG_PXA_MMC |
||||
#define CONFIG_SYS_MMC_BASE 0xF0000000 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/*
|
||||
* KGDB |
||||
*/ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* HUSH Shell Configuration |
||||
*/ |
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ |
||||
#else |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#endif |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 |
||||
|
||||
/*
|
||||
* Clock Configuration |
||||
*/ |
||||
#undef CONFIG_SYS_CLKS_IN_HZ |
||||
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ |
||||
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*
|
||||
* DRAM Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */ |
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ |
||||
#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ |
||||
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ |
||||
|
||||
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ |
||||
#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (0x5c000000) |
||||
|
||||
/*
|
||||
* NOR FLASH |
||||
*/ |
||||
#if defined(CONFIG_CMD_FLASH) /* NOR */ |
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ |
||||
|
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
|
||||
#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SYS_ONENAND_BASE 0x00000000 |
||||
#define CONFIG_ENV_IS_IN_ONENAND 1 |
||||
|
||||
#else /* No flash */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SYS_ENV_IS_NOWHERE |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x000000 |
||||
#define CONFIG_SYS_MONITOR_LEN 0x40000 |
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
/*
|
||||
* IDE |
||||
*/ |
||||
#ifdef CONFIG_CMD_IDE |
||||
#define CONFIG_LBA48 |
||||
#undef CONFIG_IDE_LED |
||||
#undef CONFIG_IDE_RESET |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 |
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 |
||||
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 |
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x120 |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 |
||||
|
||||
#define CONFIG_SYS_ATA_STRIDE 2 |
||||
#endif |
||||
|
||||
/*
|
||||
* GPIO settings |
||||
*/ |
||||
#define CONFIG_SYS_GPSR0_VAL 0x01308800 |
||||
#define CONFIG_SYS_GPSR1_VAL 0x00cf0000 |
||||
#define CONFIG_SYS_GPSR2_VAL 0x922ac000 |
||||
#define CONFIG_SYS_GPSR3_VAL 0x0161e800 |
||||
|
||||
#define CONFIG_SYS_GPCR0_VAL 0x00010000 |
||||
#define CONFIG_SYS_GPCR1_VAL 0x0 |
||||
#define CONFIG_SYS_GPCR2_VAL 0x0 |
||||
#define CONFIG_SYS_GPCR3_VAL 0x0 |
||||
|
||||
#define CONFIG_SYS_GPDR0_VAL 0xcbb18800 |
||||
#define CONFIG_SYS_GPDR1_VAL 0xfccfa981 |
||||
#define CONFIG_SYS_GPDR2_VAL 0x922affff |
||||
#define CONFIG_SYS_GPDR3_VAL 0x0161e904 |
||||
|
||||
#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 |
||||
#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510 |
||||
#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a |
||||
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa |
||||
#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa |
||||
#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401 |
||||
#define CONFIG_SYS_GAFR3_L_VAL 0x54010310 |
||||
#define CONFIG_SYS_GAFR3_U_VAL 0x00025401 |
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x30 |
||||
|
||||
/*
|
||||
* Clock settings |
||||
*/ |
||||
#define CONFIG_SYS_CKEN 0x00500240 |
||||
#define CONFIG_SYS_CCCR 0x02000290 |
||||
|
||||
/*
|
||||
* Memory settings |
||||
*/ |
||||
#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa |
||||
#define CONFIG_SYS_MSC1_VAL 0x02ccf974 |
||||
#define CONFIG_SYS_MSC2_VAL 0x00000000 |
||||
#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 |
||||
#define CONFIG_SYS_MDREFR_VAL 0x201fe01e |
||||
#define CONFIG_SYS_MDMRS_VAL 0x00000000 |
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
||||
#define CONFIG_SYS_SXCNFG_VAL 0x40044004 |
||||
#define CONFIG_SYS_MEM_BUF_IMP 0x0f |
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces |
||||
*/ |
||||
#define CONFIG_SYS_MECR_VAL 0x00000001 |
||||
#define CONFIG_SYS_MCMEM0_VAL 0x00014307 |
||||
#define CONFIG_SYS_MCMEM1_VAL 0x00014307 |
||||
#define CONFIG_SYS_MCATT0_VAL 0x0001c787 |
||||
#define CONFIG_SYS_MCATT1_VAL 0x0001c787 |
||||
#define CONFIG_SYS_MCIO0_VAL 0x0001430f |
||||
#define CONFIG_SYS_MCIO1_VAL 0x0001430f |
||||
|
||||
/*
|
||||
* LCD |
||||
*/ |
||||
#ifdef CONFIG_LCD |
||||
#define CONFIG_VOIPAC_LCD |
||||
#endif |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
#ifdef CONFIG_CMD_USB |
||||
#define CONFIG_USB_OHCI_NEW |
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT |
||||
#define CONFIG_SYS_USB_OHCI_BOARD_INIT |
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 |
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270" |
||||
#define CONFIG_USB_STORAGE |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,259 @@ |
||||
/*
|
||||
* Aeronix Zipit Z2 configuration file |
||||
* |
||||
* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Board Configuration Options |
||||
*/ |
||||
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ |
||||
#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */ |
||||
|
||||
#undef BOARD_LATE_INIT |
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT |
||||
#undef CONFIG_USE_IRQ |
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_ADDR 0x40000 |
||||
#define CONFIG_ENV_SIZE 0x20000 |
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE) |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 512 |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
|
||||
"source 0xa0000000; " \
|
||||
"else " \
|
||||
"bootm 0x60000; " \
|
||||
"fi; " |
||||
#define CONFIG_BOOTARGS \ |
||||
"console=tty0 console=ttyS2,115200 fbcon=rotate:3" |
||||
#define CONFIG_TIMESTAMP |
||||
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
|
||||
#define CONFIG_LZMA /* LZMA compression support */ |
||||
|
||||
/*
|
||||
* Serial Console Configuration |
||||
* STUART - the lower serial port on Colibri board |
||||
*/ |
||||
#define CONFIG_PXA_SERIAL |
||||
#define CONFIG_STUART 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Bootloader Components Configuration |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#undef CONFIG_CMD_NET |
||||
#define CONFIG_CMD_ENV |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_SPI |
||||
|
||||
/*
|
||||
* MMC Card Configuration |
||||
*/ |
||||
#ifdef CONFIG_CMD_MMC |
||||
#define CONFIG_MMC |
||||
#define CONFIG_PXA_MMC |
||||
#define CONFIG_SYS_MMC_BASE 0xF0000000 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/*
|
||||
* SPI and LCD |
||||
*/ |
||||
#ifdef CONFIG_CMD_SPI |
||||
#define CONFIG_SOFT_SPI |
||||
#define CONFIG_LCD |
||||
#define CONFIG_LMS283GF05 |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_CMD_BMP |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_SPLASH_SCREEN_ALIGN |
||||
#define CONFIG_VIDEO_BMP_GZIP |
||||
#define CONFIG_VIDEO_BMP_RLE8 |
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) |
||||
#undef SPI_INIT |
||||
|
||||
#define SPI_DELAY udelay(10) |
||||
#define SPI_SDA(val) zipitz2_spi_sda(val) |
||||
#define SPI_SCL(val) zipitz2_spi_scl(val) |
||||
#define SPI_READ zipitz2_spi_read() |
||||
#ifndef __ASSEMBLY__ |
||||
void zipitz2_spi_sda(int); |
||||
void zipitz2_spi_scl(int); |
||||
unsigned char zipitz2_spi_read(void); |
||||
#endif |
||||
#endif |
||||
|
||||
/*
|
||||
* KGDB |
||||
*/ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* HUSH Shell Configuration |
||||
*/ |
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ |
||||
#else |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#endif |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 |
||||
|
||||
/*
|
||||
* Clock Configuration |
||||
*/ |
||||
#undef CONFIG_SYS_CLKS_IN_HZ |
||||
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ |
||||
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*
|
||||
* DRAM Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
|
||||
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ |
||||
#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE |
||||
|
||||
/*
|
||||
* NOR FLASH |
||||
*/ |
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ |
||||
#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ |
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 |
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
||||
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) |
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) |
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
|
||||
/*
|
||||
* GPIO settings |
||||
*/ |
||||
#define CONFIG_SYS_GAFR0_L_VAL 0x02000140 |
||||
#define CONFIG_SYS_GAFR0_U_VAL 0x59188000 |
||||
#define CONFIG_SYS_GAFR1_L_VAL 0x63900002 |
||||
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 |
||||
#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa |
||||
#define CONFIG_SYS_GAFR2_U_VAL 0x29000308 |
||||
#define CONFIG_SYS_GAFR3_L_VAL 0x54000000 |
||||
#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 |
||||
#define CONFIG_SYS_GPCR0_VAL 0x00000000 |
||||
#define CONFIG_SYS_GPCR1_VAL 0x00000020 |
||||
#define CONFIG_SYS_GPCR2_VAL 0x00000000 |
||||
#define CONFIG_SYS_GPCR3_VAL 0x00000000 |
||||
#define CONFIG_SYS_GPDR0_VAL 0xdafcee00 |
||||
#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab |
||||
#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff |
||||
#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a |
||||
#define CONFIG_SYS_GPSR0_VAL 0x06080400 |
||||
#define CONFIG_SYS_GPSR1_VAL 0x007f0000 |
||||
#define CONFIG_SYS_GPSR2_VAL 0x032a0000 |
||||
#define CONFIG_SYS_GPSR3_VAL 0x00000180 |
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x30 |
||||
|
||||
/*
|
||||
* Clock settings |
||||
*/ |
||||
#define CONFIG_SYS_CKEN 0x00511220 |
||||
#define CONFIG_SYS_CCCR 0x00000190 |
||||
|
||||
/*
|
||||
* Memory settings |
||||
*/ |
||||
#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 |
||||
#define CONFIG_SYS_MSC1_VAL 0x0000ccd1 |
||||
#define CONFIG_SYS_MSC2_VAL 0x0000b884 |
||||
#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 |
||||
#define CONFIG_SYS_MDREFR_VAL 0x2011a01e |
||||
#define CONFIG_SYS_MDMRS_VAL 0x00000000 |
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 |
||||
#define CONFIG_SYS_SXCNFG_VAL 0x40044004 |
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces |
||||
*/ |
||||
#define CONFIG_SYS_MECR_VAL 0x00000001 |
||||
#define CONFIG_SYS_MCMEM0_VAL 0x00014307 |
||||
#define CONFIG_SYS_MCMEM1_VAL 0x00014307 |
||||
#define CONFIG_SYS_MCATT0_VAL 0x0001c787 |
||||
#define CONFIG_SYS_MCATT1_VAL 0x0001c787 |
||||
#define CONFIG_SYS_MCIO0_VAL 0x0001430f |
||||
#define CONFIG_SYS_MCIO1_VAL 0x0001430f |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,83 @@ |
||||
IPL =onenand_ipl
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
|
||||
LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
|
||||
AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
|
||||
CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
|
||||
OBJCFLAGS += --gap-fill=0x00
|
||||
|
||||
SOBJS := lowlevel_init.o
|
||||
SOBJS += start.o
|
||||
COBJS := vpac270.o
|
||||
COBJS += onenand_read.o
|
||||
COBJS += onenand_boot.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
|
||||
|
||||
onenandobj := $(OBJTREE)/onenand_ipl/
|
||||
|
||||
ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin
|
||||
|
||||
all: $(obj).depend $(ALL) |
||||
|
||||
$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl |
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=0x5c040400 -O binary $< $@
|
||||
|
||||
$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl |
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds |
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
|
||||
-Map $@.map -o $@
|
||||
|
||||
$(onenandobj)u-boot.lds: $(LDSCRIPT) |
||||
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
|
||||
|
||||
# create symbolic links from common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)start.S: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
|
||||
|
||||
# from onenand_ipl directory
|
||||
$(obj)onenand_ipl.h: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@
|
||||
|
||||
$(obj)onenand_boot.c: $(obj)onenand_ipl.h |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@
|
||||
|
||||
$(obj)onenand_read.c: $(obj)onenand_ipl.h |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@
|
||||
|
||||
ifneq ($(OBJTREE), $(SRCTREE)) |
||||
$(obj)vpac270.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@
|
||||
|
||||
$(obj)lowlevel_init.S: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/lowlevel_init.S $@
|
||||
endif |
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S |
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)$.c |
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1 @@ |
||||
TEXT_BASE = 0x5c03fc00
|
||||
@ -0,0 +1,34 @@ |
||||
/* |
||||
* Voipac PXA270 Lowlevel Hardware Initialization |
||||
* |
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
* |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/arch/pxa-regs.h> |
||||
#include <asm/arch/macro.h> |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
pxa_clock_setup |
||||
mov pc, lr |
||||
@ -0,0 +1,51 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) . = ALIGN(4); } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,42 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/hardware.h> |
||||
|
||||
int board_init (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int s_init(int skip) |
||||
{ |
||||
return 0; |
||||
} |
||||
Loading…
Reference in new issue