Add Freescale MCF54418TWR ColdFire development board support. Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Alison Wang <b18965@freescale.com>master
Alison Wang
12 years ago
committed by
jason
parent
45370e1836
commit
186fc4db26
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# Copyright 2010-2012 Freescale Semiconductor, Inc.
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# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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# Copyright 2010-2012 Freescale Semiconductor, Inc.
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# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp |
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
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/*
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* Copyright 2010-2012 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <spi.h> |
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#include <asm/io.h> |
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#include <asm/immap.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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/*
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* need to to: |
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* Check serial flash size. if 2mb evb, else 8mb demo |
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*/ |
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puts("Board: "); |
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puts("Freescale MCF54418 Tower System\n"); |
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return 0; |
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}; |
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phys_size_t initdram(int board_type) |
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{ |
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u32 dramsize; |
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#if defined(CONFIG_SERIAL_BOOT) |
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/*
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* Serial Boot: The dram is already initialized in start.S |
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* only require to return DRAM size |
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*/ |
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; |
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#else |
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sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); |
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ccm_t *ccm = (ccm_t *)MMAP_CCM; |
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gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
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pm_t *pm = (pm_t *) MMAP_PM; |
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u32 i; |
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; |
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for (i = 0x13; i < 0x20; i++) { |
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if (dramsize == (1 << i)) |
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break; |
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} |
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out_8(&pm->pmcr0, 0x2E); |
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out_8(&gpio->mscr_sdram, 1); |
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clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF); |
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setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK); |
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out_be32(&sdram->rcrcr, 0x40000000); |
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out_be32(&sdram->padcr, 0x01030203); |
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out_be32(&sdram->cr00, 0x01010101); |
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out_be32(&sdram->cr01, 0x00000101); |
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out_be32(&sdram->cr02, 0x01010100); |
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out_be32(&sdram->cr03, 0x01010000); |
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out_be32(&sdram->cr04, 0x00010101); |
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out_be32(&sdram->cr06, 0x00010100); |
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out_be32(&sdram->cr07, 0x00000001); |
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out_be32(&sdram->cr08, 0x01000001); |
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out_be32(&sdram->cr09, 0x00000100); |
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out_be32(&sdram->cr10, 0x00010001); |
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out_be32(&sdram->cr11, 0x00000200); |
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out_be32(&sdram->cr12, 0x01000002); |
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out_be32(&sdram->cr13, 0x00000000); |
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out_be32(&sdram->cr14, 0x00000100); |
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out_be32(&sdram->cr15, 0x02000100); |
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out_be32(&sdram->cr16, 0x02000407); |
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out_be32(&sdram->cr17, 0x02030007); |
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out_be32(&sdram->cr18, 0x02000100); |
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out_be32(&sdram->cr19, 0x0A030203); |
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out_be32(&sdram->cr20, 0x00020708); |
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out_be32(&sdram->cr21, 0x00050008); |
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out_be32(&sdram->cr22, 0x04030002); |
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out_be32(&sdram->cr23, 0x00000004); |
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out_be32(&sdram->cr24, 0x020A0000); |
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out_be32(&sdram->cr25, 0x0C00000E); |
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out_be32(&sdram->cr26, 0x00002004); |
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out_be32(&sdram->cr28, 0x00100010); |
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out_be32(&sdram->cr29, 0x00100010); |
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out_be32(&sdram->cr31, 0x07990000); |
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out_be32(&sdram->cr40, 0x00000000); |
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out_be32(&sdram->cr41, 0x00C80064); |
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out_be32(&sdram->cr42, 0x44520002); |
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out_be32(&sdram->cr43, 0x00C80023); |
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out_be32(&sdram->cr45, 0x0000C350); |
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out_be32(&sdram->cr56, 0x04000000); |
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out_be32(&sdram->cr57, 0x03000304); |
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out_be32(&sdram->cr58, 0x40040000); |
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out_be32(&sdram->cr59, 0xC0004004); |
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out_be32(&sdram->cr60, 0x0642C000); |
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out_be32(&sdram->cr61, 0x00000642); |
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asm("tpf"); |
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out_be32(&sdram->cr09, 0x01000100); |
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udelay(100); |
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#endif |
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return dramsize; |
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}; |
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int testdram(void) |
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{ |
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return 0; |
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} |
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@ -0,0 +1,97 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(m68k) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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.text : |
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{ |
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arch/m68k/cpu/mcf5445x/start.o (.text*) |
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*(.text*) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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__got_start = .; |
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KEEP(*(.got)) |
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__got_end = .; |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
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_FIXUP_TABLE_ = .; |
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KEEP(*(.fixup)) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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.data : |
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{ |
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*(.data*) |
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*(.sdata*) |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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_sbss = .; |
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*(.bss*) |
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*(.sbss*) |
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*(COMMON) |
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. = ALIGN(4); |
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_ebss = .; |
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} |
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__bss_end__ = . ; |
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PROVIDE (end = .); |
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} |
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@ -0,0 +1,244 @@ |
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Freescale MCF54418TWR ColdFire Development Board |
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================================================ |
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TsiChung Liew(Tsi-Chung.Liew@freescale.com) |
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Created Mar 22, 2012 |
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=========================================== |
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Changed files: |
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============== |
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- board/freescale/m54418twr/m54418twr.c Dram setup |
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- board/freescale/m54418twr/Makefile Makefile |
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- board/freescale/m54418twr/config.mk config make |
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- board/freescale/m54418twr/u-boot.lds Linker description |
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- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code |
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- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs |
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- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support |
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- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock |
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- arch/m68k/cpu/mcf5445x/Makefile Makefile |
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- arch/m68k/cpu/mcf5445x/config.mk config make |
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- arch/m68k/cpu/mcf5445x/start.S start up assembly code |
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- doc/README.m54418twr This readme file |
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- drivers/net/mcffec.c ColdFire common FEC driver |
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- drivers/net/mcfmii.c ColdFire common MII driver |
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- drivers/serial/mcfuart.c ColdFire common UART driver |
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- arch/m68k/include/asm/bitops.h Bit operation function export |
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- arch/m68k/include/asm/byteorder.h Byte order functions |
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- arch/m68k/include/asm/fec.h FEC structure and definition |
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- arch/m68k/include/asm/global_data.h Global data structure |
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- arch/m68k/include/asm/immap.h ColdFire specific header file and driver macros |
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- arch/m68k/include/asm/immap_5441x.h mcf5441x specific header file |
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- arch/m68k/include/asm/io.h io functions |
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- arch/m68k/include/asm/m5441x.h mcf5441x specific header file |
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- arch/m68k/include/asm/posix_types.h Posix |
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- arch/m68k/include/asm/processor.h header file |
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- arch/m68k/include/asm/ptrace.h Exception structure |
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- arch/m68k/include/asm/rtc.h Realtime clock header file |
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- arch/m68k/include/asm/string.h String function export |
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- arch/m68k/include/asm/timer.h Timer structure and definition |
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- arch/m68k/include/asm/types.h Data types definition |
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- arch/m68k/include/asm/uart.h Uart structure and definition |
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- arch/m68k/include/asm/u-boot.h u-boot structure |
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- include/configs/M54418TWR.h Board specific configuration file |
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- arch/m68k/lib/board.c board init function |
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- arch/m68k/lib/cache.c |
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- arch/m68k/lib/interrupts.c Coldfire common interrupt functions |
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- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) |
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- arch/m68k/lib/traps.c Exception init code |
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1 MCF5441x specific Options/Settings |
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==================================== |
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1.1 pre-loader is no longer suppoer in thie coldfire family |
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1.2 Configuration settings for M54418TWR Development Board |
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CONFIG_MCF5441x -- define for all MCF5441x CPUs |
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CONFIG_M54418 -- define for all Freescale MCF54418 CPUs |
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CONFIG_M54418TWR -- define for M54418TWR board |
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CONFIG_MCFUART -- define to use common CF Uart driver |
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CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 |
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CONFIG_BAUDRATE -- define UART baudrate |
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CONFIG_MCFFEC -- define to use common CF FEC driver |
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CONFIG_MII -- enable to use MII driver |
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CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery |
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CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer |
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CONFIG_SYS_FAULT_ECHO_LINK_DOWN -- |
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CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration |
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CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration |
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CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register |
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CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register |
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MCFFEC_TOUT_LOOP -- set FEC timeout loop |
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CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot |
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CONFIG_MCFTMR -- define to use DMA timer |
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CONFIG_SYS_IMMR -- define for MBAR offset |
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CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc |
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CONFIG_SYS_MBAR -- define MBAR offset |
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CONFIG_MONITOR_IS_IN_RAM -- Not support |
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CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM |
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CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register |
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CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register |
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CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register |
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CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base |
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2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL |
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=========================================== |
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2.1. System memory map: |
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MRAM: 0x00000000-0x0003FFFF (256KB) |
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DDR: 0x40000000-0x47FFFFFF (128MB) |
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SRAM: 0x80000000-0x8000FFFF (64KB) |
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IP: 0xE0000000-0xFFFFFFFF (512MB) |
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3. COMPILATION |
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============== |
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3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF version) |
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from codesourcery.com was used. Download it from: |
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http://www.codesourcery.com/gnu_toolchains/coldfire/download.html |
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3.2 Compilation |
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export CROSS_COMPILE=cross-compile-prefix |
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cd u-boot |
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make distclean |
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make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock |
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make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock |
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make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock |
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make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input clock |
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make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock |
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make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock |
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make |
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4. SCREEN DUMP |
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============== |
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4.1 M54418TWR Development board |
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Boot from NAND flash (NOTE: May not show exactly the same) |
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U-Boot 2012.10-00209-g12ae1d8-dirty (Oct 18 2012 - 15:54:54) |
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CPU: Freescale MCF54418 (Mask:a3 Version:1) |
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CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz |
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INP CLK 50 MHz VCO CLK 500 MHz |
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Board: Freescale MCF54418 Tower System |
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SPI: ready |
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DRAM: 128 MiB |
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NAND: 256 MiB |
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In: serial |
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Out: serial |
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Err: serial |
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Net: FEC0, FEC1 |
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-> pri |
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baudrate=115200 |
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bootargs=root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(k |
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ernel)ro,-(jffs2) console=ttyS0,115200 |
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bootdelay=2 |
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eth1addr=00:e0:0c:bc:e5:61 |
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ethact=FEC0 |
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ethaddr=00:e0:0c:bc:e5:60 |
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fileaddr=40010000 |
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filesize=27354 |
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gatewayip=192.168.1.1 |
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hostname=M54418TWR |
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inpclk=50000000 |
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ipaddr=192.168.1.2 |
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load=tftp ${loadaddr} ${u-boot}; |
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loadaddr=0x40010000 |
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mem=129024k |
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netdev=eth0 |
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netmask=255.255.255.0 |
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prog=nand device 0;nand erase 0 40000;nb_update ${loadaddr} ${filesize};save |
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serverip=192.168.1.1 |
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stderr=serial |
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stdin=serial |
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stdout=serial |
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u-boot=u-boot.bin |
||||
upd=run load; run prog |
||||
|
||||
Environment size: 653/131068 bytes |
||||
-> bdinfo |
||||
memstart = 0x40000000 |
||||
memsize = 0x08000000 |
||||
flashstart = 0x00000000 |
||||
flashsize = 0x00000000 |
||||
flashoffset = 0x00000000 |
||||
sramstart = 0x80000000 |
||||
sramsize = 0x00010000 |
||||
mbar = 0xFC000000 |
||||
cpufreq = 250 MHz |
||||
busfreq = 125 MHz |
||||
flbfreq = 125 MHz |
||||
inpfreq = 50 MHz |
||||
vcofreq = 500 MHz |
||||
ethaddr = 00:e0:0c:bc:e5:60 |
||||
eth1addr = 00:e0:0c:bc:e5:61 |
||||
ip_addr = 192.168.1.2 |
||||
baudrate = 115200 bps |
||||
-> help |
||||
? - alias for 'help' |
||||
base - print or set address offset |
||||
bdinfo - print Board Info structure |
||||
boot - boot default, i.e., run 'bootcmd' |
||||
bootd - boot default, i.e., run 'bootcmd' |
||||
bootelf - Boot from an ELF image in memory |
||||
bootm - boot application image from memory |
||||
bootp - boot image via network using BOOTP/TFTP protocol |
||||
bootvx - Boot vxWorks from an ELF image |
||||
cmp - memory compare |
||||
coninfo - print console devices and information |
||||
cp - memory copy |
||||
crc32 - checksum calculation |
||||
dcache - enable or disable data cache |
||||
dhcp - boot image via network using DHCP/TFTP protocol |
||||
echo - echo args to console |
||||
editenv - edit environment variable |
||||
env - environment handling commands |
||||
exit - exit script |
||||
false - do nothing, unsuccessfully |
||||
go - start application at address 'addr' |
||||
help - print command description/usage |
||||
icache - enable or disable instruction cache |
||||
iminfo - print header information for application image |
||||
imxtract- extract a part of a multi-image |
||||
itest - return true/false on integer compare |
||||
loop - infinite loop on address range |
||||
md - memory display |
||||
mdio - MDIO utility commands |
||||
mii - MII utility commands |
||||
mm - memory modify (auto-incrementing address) |
||||
mtest - simple RAM read/write test |
||||
mw - memory write (fill) |
||||
nand - NAND sub-system |
||||
nb_update- Nand boot update program |
||||
nboot - boot from NAND device |
||||
nfs - boot image via network using NFS protocol |
||||
nm - memory modify (constant address) |
||||
ping - send ICMP ECHO_REQUEST to network host |
||||
printenv- print environment variables |
||||
reginfo - print register information |
||||
reset - Perform RESET of the CPU |
||||
run - run commands in an environment variable |
||||
saveenv - save environment variables to persistent storage |
||||
setenv - set environment variables |
||||
sf - SPI flash sub-system |
||||
showvar - print local hushshell variables |
||||
sleep - delay execution for some time |
||||
source - run script from memory |
||||
sspi - SPI utility command |
||||
test - minimal test like /bin/sh |
||||
tftpboot- boot image via network using TFTP protocol |
||||
true - do nothing, successfully |
||||
version - print monitor, compiler and linker version |
||||
@ -0,0 +1,448 @@ |
||||
/*
|
||||
* Configuation settings for the Freescale MCF54418 TWR board. |
||||
* |
||||
* Copyright 2010-2012 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef _M54418TWR_H |
||||
#define _M54418TWR_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_MCF5441x /* define processor family */ |
||||
#define CONFIG_M54418 /* define processor type */ |
||||
#define CONFIG_M54418TWR /* M54418TWR board */ |
||||
|
||||
#define CONFIG_MCFUART |
||||
#define CONFIG_SYS_UART_PORT (0) |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
||||
|
||||
#undef CONFIG_WATCHDOG |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/* Command line configuration */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_BOOTD |
||||
#define CONFIG_CMD_CACHE |
||||
#undef CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ELF |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_I2C |
||||
#undef CONFIG_CMD_JFFS2 |
||||
#undef CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_MISC |
||||
#define CONFIG_CMD_MII |
||||
#undef CONFIG_CMD_NAND |
||||
#undef CONFIG_CMD_NAND_YAFFS |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_CMD_SF |
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#undef CONFIG_CMD_LOADB |
||||
#undef CONFIG_CMD_LOADS |
||||
|
||||
/*
|
||||
* NAND FLASH |
||||
*/ |
||||
#ifdef CONFIG_CMD_NAND |
||||
#define CONFIG_JFFS2_NAND |
||||
#define CONFIG_NAND_FSL_NFC |
||||
#define CONFIG_SYS_NAND_BASE 0xFC0FC000 |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE |
||||
#define CONFIG_SYS_NAND_SELECT_DEVICE |
||||
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ |
||||
#endif |
||||
|
||||
/* Network configuration */ |
||||
#define CONFIG_MCFFEC |
||||
#ifdef CONFIG_MCFFEC |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_MII 1 |
||||
#define CONFIG_MII_INIT 1 |
||||
#define CONFIG_SYS_DISCOVER_PHY |
||||
#define CONFIG_SYS_RX_ETH_BUFFER 2 |
||||
#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN |
||||
#define CONFIG_SYS_TX_ETH_BUFFER 2 |
||||
#define CONFIG_HAS_ETH1 |
||||
|
||||
#define CONFIG_SYS_FEC0_PINMUX 0 |
||||
#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE |
||||
#define CONFIG_SYS_FEC1_PINMUX 0 |
||||
#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE |
||||
#define MCFFEC_TOUT_LOOP 50000 |
||||
#define CONFIG_SYS_FEC0_PHYADDR 0 |
||||
#define CONFIG_SYS_FEC1_PHYADDR 1 |
||||
|
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ |
||||
|
||||
#ifdef CONFIG_SYS_NAND_BOOT |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ |
||||
"mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
|
||||
"-(jffs2) console=ttyS0,115200" |
||||
#else |
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ |
||||
__stringify(CONFIG_SERVERIP) ":/tftpboot/" \
|
||||
__stringify(CONFIG_IPADDR) " ip=" \
|
||||
__stringify(CONFIG_IPADDR) ":" \
|
||||
__stringify(CONFIG_SERVERIP)":" \
|
||||
__stringify(CONFIG_GATEWAYIP)": " \
|
||||
__stringify(CONFIG_NETMASK) \
|
||||
"::eth0:off:rw console=ttyS0,115200" |
||||
#endif |
||||
|
||||
#define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 |
||||
#define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 |
||||
#define CONFIG_ETHPRIME "FEC0" |
||||
#define CONFIG_IPADDR 192.168.1.2 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_SERVERIP 192.168.1.1 |
||||
#define CONFIG_GATEWAYIP 192.168.1.1 |
||||
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
#define CONFIG_SYS_FEC_BUF_USE_SRAM |
||||
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
||||
#ifndef CONFIG_SYS_DISCOVER_PHY |
||||
#define FECDUPLEX FULL |
||||
#define FECSPEED _100BASET |
||||
#define LINKSTATUS 1 |
||||
#else |
||||
#define LINKSTATUS 0 |
||||
#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
||||
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
||||
#endif |
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */ |
||||
#endif |
||||
|
||||
#define CONFIG_HOSTNAME M54418TWR |
||||
|
||||
#if defined(CONFIG_CF_SBF) |
||||
/* ST Micro serial flash */ |
||||
#define CONFIG_SYS_LOAD_ADDR2 0x40010007 |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=0x40010000\0" \
|
||||
"sbfhdr=sbfhdr.bin\0" \
|
||||
"uboot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${sbfhdr};" \
|
||||
"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=sf probe 0:1 1000000 3;" \
|
||||
"sf erase 0 40000;" \
|
||||
"sf write ${loadaddr} 0 40000;" \
|
||||
"save\0" \
|
||||
"" |
||||
#elif defined(CONFIG_SYS_NAND_BOOT) |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=0x40010000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot};\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=nand device 0;" \
|
||||
"nand erase 0 40000;" \
|
||||
"nb_update ${loadaddr} ${filesize};" \
|
||||
"save\0" \
|
||||
"" |
||||
#else |
||||
#define CONFIG_SYS_UBOOT_END 0x3FFFF |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=40010000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off mram" " ;" \
|
||||
"cp.b ${loadaddr} 0 ${filesize};" \
|
||||
"save\0" \
|
||||
"" |
||||
#endif |
||||
|
||||
/* Realtime clock */ |
||||
#undef CONFIG_MCFRTC |
||||
#define CONFIG_RTC_MCFRRTC |
||||
#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 |
||||
|
||||
/* Timer */ |
||||
#define CONFIG_MCFTMR |
||||
#undef CONFIG_MCFPIT |
||||
|
||||
/* I2c */ |
||||
#undef CONFIG_FSL_I2C |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
/* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SPEED 80000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000 |
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
||||
|
||||
/* DSPI and Serial Flash */ |
||||
#define CONFIG_CF_SPI |
||||
#define CONFIG_CF_DSPI |
||||
#define CONFIG_SERIAL_FLASH |
||||
#define CONFIG_HARD_SPI |
||||
#define CONFIG_SYS_SBFHDR_SIZE 0x7 |
||||
#ifdef CONFIG_CMD_SPI |
||||
# define CONFIG_SPI_FLASH |
||||
# define CONFIG_SPI_FLASH_ATMEL |
||||
|
||||
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
||||
DSPI_CTAR_PCSSCK_1CLK | \
|
||||
DSPI_CTAR_PASC(0) | \
|
||||
DSPI_CTAR_PDT(0) | \
|
||||
DSPI_CTAR_CSSCK(0) | \
|
||||
DSPI_CTAR_ASC(0) | \
|
||||
DSPI_CTAR_DT(1)) |
||||
# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) |
||||
# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) |
||||
#endif |
||||
|
||||
/* Input, PCI, Flexbus, and VCO */ |
||||
#define CONFIG_EXTRA_CLOCK |
||||
|
||||
#define CONFIG_PRAM 2048 /* 2048 KB */ |
||||
|
||||
/* HUSH */ |
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
#define CONFIG_SYS_PROMPT "-> " |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
||||
|
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
#define CONFIG_SYS_MBAR 0xFC000000 |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
||||
/* End of used area in internal SRAM */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
||||
#define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
||||
/* size in bytes reserved for initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 256 |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
CONFIG_SYS_GBL_DATA_SIZE) - 32) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000 |
||||
#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) |
||||
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) |
||||
#define CONFIG_SYS_DRAM_TEST |
||||
|
||||
#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) |
||||
#define CONFIG_SERIAL_BOOT |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SERIAL_BOOT) |
||||
#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) |
||||
/* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) |
||||
/* Reserve 256 kB for malloc() */ |
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10) |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization ?? |
||||
*/ |
||||
/* Initial Memory map for Linux */ |
||||
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ |
||||
(CONFIG_SYS_SDRAM_SIZE << 20)) |
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash |
||||
*/ |
||||
#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_IS_IN_MRAM 1 |
||||
#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ |
||||
#define CONFIG_ENV_SIZE 0x1000 |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CF_SBF) |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH 1 |
||||
#define CONFIG_ENV_SPI_CS 1 |
||||
#define CONFIG_ENV_OFFSET 0x40000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#endif |
||||
#if defined(CONFIG_SYS_NAND_BOOT) |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_IS_IN_NAND 1 |
||||
#define CONFIG_ENV_OFFSET 0x80000 |
||||
#define CONFIG_ENV_SIZE 0x20000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 |
||||
#endif |
||||
#undef CONFIG_ENV_OVERWRITE |
||||
|
||||
/* FLASH organization */ |
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
||||
|
||||
#undef CONFIG_SYS_FLASH_CFI |
||||
#ifdef CONFIG_SYS_FLASH_CFI |
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 |
||||
/* Max size that the board might have */ |
||||
#define CONFIG_SYS_FLASH_SIZE 0x1000000 |
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
/* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
/* max number of sectors on one chip */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 270 |
||||
/* "Real" (hardware) sectors protection */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_FLASH_CHECKSUM |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } |
||||
#else |
||||
/* max number of sectors on one chip */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 270 |
||||
/* max number of sectors on one chip */ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 0 |
||||
#endif |
||||
|
||||
/*
|
||||
* This is setting for JFFS2 support in u-boot. |
||||
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. |
||||
*/ |
||||
#ifdef CONFIG_CMD_JFFS2 |
||||
#define CONFIG_JFFS2_DEV "nand0" |
||||
#define CONFIG_JFFS2_PART_OFFSET (0x800000) |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_DEVICE |
||||
#define MTDIDS_DEFAULT "nand0=m54418twr.nand" |
||||
|
||||
#define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ |
||||
"7m(kernel)," \
|
||||
"-(rootfs)" |
||||
|
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts command */ |
||||
#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ |
||||
#define CONFIG_RBTREE |
||||
#define MTDIDS_DEFAULT "nand0=NAND" |
||||
#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ |
||||
"-(ubi)" |
||||
#endif |
||||
/* Cache Configuration */ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 |
||||
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - 8) |
||||
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - 4) |
||||
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
||||
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) |
||||
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ |
||||
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
|
||||
CF_ACR_EN | CF_ACR_SM_ALL) |
||||
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ |
||||
CF_CACR_ICINVA | CF_CACR_EUSP) |
||||
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ |
||||
CF_CACR_DEC | CF_CACR_DDCM_P | \
|
||||
CF_CACR_DCINVA) & ~CF_CACR_ICINVA) |
||||
|
||||
#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - 12) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory bank definitions |
||||
*/ |
||||
/*
|
||||
* CS0 - NOR Flash 16MB |
||||
* CS1 - Available |
||||
* CS2 - Available |
||||
* CS3 - Available |
||||
* CS4 - Available |
||||
* CS5 - Available |
||||
*/ |
||||
|
||||
/* Flash */ |
||||
#define CONFIG_SYS_CS0_BASE 0x00000000 |
||||
#define CONFIG_SYS_CS0_MASK 0x000F0101 |
||||
#define CONFIG_SYS_CS0_CTRL 0x00001D60 |
||||
|
||||
#endif /* _M54418TWR_H */ |
||||
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Reference in new issue