Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass <sjg@chromium.org>master
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/*
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* From Coreboot file of the same name |
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* |
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* Copyright (C) 2011 The Chromium Authors. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <asm/cpu.h> |
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#include <asm/msr.h> |
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#include <asm/processor.h> |
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#include <asm/turbo.h> |
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#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
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static inline int get_global_turbo_state(void) |
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{ |
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return TURBO_UNKNOWN; |
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} |
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static inline void set_global_turbo_state(int state) |
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{ |
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} |
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#else |
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static int g_turbo_state = TURBO_UNKNOWN; |
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static inline int get_global_turbo_state(void) |
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{ |
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return g_turbo_state; |
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} |
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static inline void set_global_turbo_state(int state) |
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{ |
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g_turbo_state = state; |
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} |
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#endif |
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static const char *const turbo_state_desc[] = { |
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[TURBO_UNKNOWN] = "unknown", |
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[TURBO_UNAVAILABLE] = "unavailable", |
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[TURBO_DISABLED] = "available but hidden", |
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[TURBO_ENABLED] = "available and visible" |
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}; |
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/*
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* Determine the current state of Turbo and cache it for later. |
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* Turbo is a package level config so it does not need to be |
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* enabled on every core. |
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*/ |
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int turbo_get_state(void) |
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{ |
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struct cpuid_result cpuid_regs; |
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int turbo_en, turbo_cap; |
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msr_t msr; |
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int turbo_state = get_global_turbo_state(); |
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/* Return cached state if available */ |
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if (turbo_state != TURBO_UNKNOWN) |
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return turbo_state; |
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cpuid_regs = cpuid(CPUID_LEAF_PM); |
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turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); |
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msr = msr_read(MSR_IA32_MISC_ENABLES); |
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turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); |
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if (!turbo_cap && turbo_en) { |
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/* Unavailable */ |
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turbo_state = TURBO_UNAVAILABLE; |
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} else if (!turbo_cap && !turbo_en) { |
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/* Available but disabled */ |
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turbo_state = TURBO_DISABLED; |
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} else if (turbo_cap && turbo_en) { |
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/* Available */ |
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turbo_state = TURBO_ENABLED; |
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} |
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set_global_turbo_state(turbo_state); |
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debug("Turbo is %s\n", turbo_state_desc[turbo_state]); |
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return turbo_state; |
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} |
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void turbo_enable(void) |
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{ |
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msr_t msr; |
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/* Only possible if turbo is available but hidden */ |
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if (turbo_get_state() == TURBO_DISABLED) { |
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/* Clear Turbo Disable bit in Misc Enables */ |
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msr = msr_read(MSR_IA32_MISC_ENABLES); |
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msr.hi &= ~H_MISC_DISABLE_TURBO; |
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msr_write(MSR_IA32_MISC_ENABLES, msr); |
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/* Update cached turbo state */ |
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set_global_turbo_state(TURBO_ENABLED); |
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debug("Turbo has been enabled\n"); |
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} |
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} |
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/*
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* From Coreboot file of same name |
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* |
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* Copyright (C) 2007-2009 coresystems GmbH |
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* 2012 secunet Security Networks AG |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _ASM_SPEEDSTEP_H |
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#define _ASM_SPEEDSTEP_H |
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/* Magic value used to locate speedstep configuration in the device tree */ |
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#define SPEEDSTEP_APIC_MAGIC 0xACAC |
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/* MWAIT coordination I/O base address. This must match
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* the \_PR_.CPU0 PM base address. |
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*/ |
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#define PMB0_BASE 0x510 |
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/* PMB1: I/O port that triggers SMI once cores are in the same state.
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* See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] |
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*/ |
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#define PMB1_BASE 0x800 |
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struct sst_state { |
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uint8_t dynfsb:1; /* whether this is SLFM */ |
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uint8_t nonint:1; /* add .5 to ratio */ |
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uint8_t ratio:6; |
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uint8_t vid; |
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uint8_t is_turbo; |
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uint8_t is_slfm; |
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uint32_t power; |
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}; |
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#define SPEEDSTEP_RATIO_SHIFT 8 |
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#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) |
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#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) |
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#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) |
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#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) |
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#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) |
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#define SPEEDSTEP_VID_MASK 0x3f |
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#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \ |
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0, /* dynfsb won't be read. */ \
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((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \
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(((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \
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>> SPEEDSTEP_RATIO_SHIFT), \
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(val & mask) & SPEEDSTEP_VID_MASK, \
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0, /* not turbo by default */ \
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0, /* not slfm by default */ \
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0 /* power is hardcoded in software. */ \
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}) |
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#define SPEEDSTEP_ENCODE_STATE(state) ( \ |
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((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \
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((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \
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((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
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((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) |
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#define SPEEDSTEP_DOUBLE_RATIO(state) ( \ |
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((uint8_t)(state).ratio * 2) + (state).nonint) |
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struct sst_params { |
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struct sst_state slfm; |
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struct sst_state min; |
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struct sst_state max; |
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struct sst_state turbo; |
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}; |
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/* Looking at core2's spec, the highest normal bus ratio for an eist enabled
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processor is 14, the lowest is always 6. This makes 5 states with the |
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minimal step width of 2. With turbo mode and super LFM we have at most 7. */ |
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#define SPEEDSTEP_MAX_NORMAL_STATES 5 |
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#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) |
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struct sst_table { |
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/* Table of p-states for EMTTM and ACPI by decreasing performance. */ |
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struct sst_state states[SPEEDSTEP_MAX_STATES]; |
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int num_states; |
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}; |
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void speedstep_gen_pstates(struct sst_table *); |
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#define SPEEDSTEP_MAX_POWER_YONAH 31000 |
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#define SPEEDSTEP_MIN_POWER_YONAH 13100 |
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#define SPEEDSTEP_MAX_POWER_MEROM 35000 |
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#define SPEEDSTEP_MIN_POWER_MEROM 25000 |
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#define SPEEDSTEP_SLFM_POWER_MEROM 12000 |
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#define SPEEDSTEP_MAX_POWER_PENRYN 35000 |
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#define SPEEDSTEP_MIN_POWER_PENRYN 15000 |
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#define SPEEDSTEP_SLFM_POWER_PENRYN 12000 |
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#endif |
@ -0,0 +1,31 @@ |
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/*
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* From coreboot file of the same name |
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* |
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _ASM_TURBO_H |
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#define _ASM_TURBO_H |
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#define CPUID_LEAF_PM 6 |
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#define PM_CAP_TURBO_MODE (1 << 1) |
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#define MSR_IA32_MISC_ENABLES 0x1a0 |
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#define H_MISC_DISABLE_TURBO (1 << 6) |
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enum { |
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TURBO_UNKNOWN, |
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TURBO_UNAVAILABLE, |
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TURBO_DISABLED, |
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TURBO_ENABLED, |
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}; |
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/* Return current turbo state */ |
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int turbo_get_state(void); |
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/* Enable turbo */ |
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void turbo_enable(void); |
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#endif |
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