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@ -299,6 +299,8 @@ static void mctl_sys_init(struct dram_para *para) |
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/* Put all DRAM-related blocks to reset state */ |
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clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET); |
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clrbits_le32(&ccm->dram_gate_reset, BIT(0)); |
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udelay(5); |
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writel(0, &ccm->dram_gate_reset); |
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clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); |
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clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); |
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@ -313,7 +315,9 @@ static void mctl_sys_init(struct dram_para *para) |
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/* Configure DRAM mod clock */ |
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writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); |
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setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); |
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writel(BIT(0) | BIT(RESET_SHIFT), &ccm->dram_gate_reset); |
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writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset); |
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udelay(5); |
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setbits_le32(&ccm->dram_gate_reset, BIT(0)); |
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/* Disable all channels */ |
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writel(0, &mctl_com->maer0); |
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