Conflicts: drivers/serial/serial.c The conflict above was a trivial case of adding one init function in each branch, and manually resolved in merge.master
Albert ARIBAUD
11 years ago
commit
19d829fa60
@ -0,0 +1,6 @@ |
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SECTION 0x0 BOOTABLE |
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TAG LAST |
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LOAD 0x0 spl/u-boot-spl.bin |
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CALL 0x14 0x0 |
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LOAD 0x40000100 u-boot.bin |
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CALL 0x40000100 0x0 |
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@ -0,0 +1,8 @@ |
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SECTION 0x0 BOOTABLE |
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TAG LAST |
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LOAD 0x0 spl/u-boot-spl.bin |
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LOAD IVT 0x8000 0x14 |
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CALL HAB 0x8000 0x0 |
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LOAD 0x40000100 u-boot.bin |
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LOAD IVT 0x8000 0x40000100 |
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CALL HAB 0x8000 0x0 |
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@ -0,0 +1,104 @@ |
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/*
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* Copyright (C) 2010-2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/hab.h> |
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/* -------- start of HAB API updates ------------*/ |
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#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) |
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#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) |
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#define hab_rvt_authenticate_image \ |
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((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) |
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#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY) |
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#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT) |
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#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT |
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bool is_hab_enabled(void) |
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{ |
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
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struct fuse_bank *bank = &ocotp->bank[0]; |
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struct fuse_bank0_regs *fuse = |
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(struct fuse_bank0_regs *)bank->fuse_regs; |
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uint32_t reg = readl(&fuse->cfg5); |
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return (reg & 0x2) == 0x2; |
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} |
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void display_event(uint8_t *event_data, size_t bytes) |
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{ |
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uint32_t i; |
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if (!(event_data && bytes > 0)) |
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return; |
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for (i = 0; i < bytes; i++) { |
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if (i == 0) |
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printf("\t0x%02x", event_data[i]); |
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else if ((i % 8) == 0) |
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printf("\n\t0x%02x", event_data[i]); |
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else |
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printf(" 0x%02x", event_data[i]); |
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} |
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} |
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int get_hab_status(void) |
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{ |
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uint32_t index = 0; /* Loop index */ |
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uint8_t event_data[128]; /* Event data buffer */ |
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size_t bytes = sizeof(event_data); /* Event size in bytes */ |
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enum hab_config config = 0; |
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enum hab_state state = 0; |
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if (is_hab_enabled()) |
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puts("\nSecure boot enabled\n"); |
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else |
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puts("\nSecure boot disabled\n"); |
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/* Check HAB status */ |
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if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) { |
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printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", |
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config, state); |
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/* Display HAB Error events */ |
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while (hab_rvt_report_event(HAB_FAILURE, index, event_data, |
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&bytes) == HAB_SUCCESS) { |
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puts("\n"); |
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printf("--------- HAB Event %d -----------------\n", |
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index + 1); |
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puts("event data:\n"); |
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display_event(event_data, bytes); |
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puts("\n"); |
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bytes = sizeof(event_data); |
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index++; |
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} |
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} |
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/* Display message if no HAB events are found */ |
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else { |
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printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", |
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config, state); |
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puts("No HAB Events Found!\n\n"); |
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} |
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return 0; |
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} |
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int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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if ((argc != 1)) { |
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cmd_usage(cmdtp); |
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return 1; |
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} |
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get_hab_status(); |
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return 0; |
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} |
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U_BOOT_CMD( |
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hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, |
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"display HAB status", |
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"" |
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); |
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@ -0,0 +1,67 @@ |
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/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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*/ |
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#ifndef __SECURE_MX6Q_H__ |
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#define __SECURE_MX6Q_H__ |
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#include <linux/types.h> |
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/* -------- start of HAB API updates ------------*/ |
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/* The following are taken from HAB4 SIS */ |
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/* Status definitions */ |
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enum hab_status { |
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HAB_STS_ANY = 0x00, |
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HAB_FAILURE = 0x33, |
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HAB_WARNING = 0x69, |
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HAB_SUCCESS = 0xf0 |
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}; |
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/* Security Configuration definitions */ |
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enum hab_config { |
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HAB_CFG_RETURN = 0x33, /**< Field Return IC */ |
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HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */ |
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HAB_CFG_CLOSED = 0xcc /**< Secure IC */ |
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}; |
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/* State definitions */ |
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enum hab_state { |
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HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */ |
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HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */ |
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HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */ |
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HAB_STATE_TRUSTED = 0x99, /**< Trusted state */ |
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HAB_STATE_SECURE = 0xaa, /**< Secure state */ |
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HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */ |
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HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */ |
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HAB_STATE_NONE = 0xf0, /**< No security state machine */ |
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HAB_STATE_MAX |
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}; |
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/*Function prototype description*/ |
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typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t, |
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uint8_t* , size_t*); |
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typedef enum hab_status hab_rvt_report_status_t(enum hab_config *, |
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enum hab_state *); |
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typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*); |
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typedef enum hab_status hab_rvt_entry_t(void); |
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typedef enum hab_status hab_rvt_exit_t(void); |
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typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, |
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void **, size_t *, hab_loader_callback_f_t); |
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typedef void hapi_clock_init_t(void); |
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#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) |
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#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) |
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#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) |
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#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) |
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#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) |
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#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D) |
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#define HAB_CID_ROM 0 /**< ROM Caller ID */ |
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#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ |
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/* ----------- end of HAB API updates ------------*/ |
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#endif |
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@ -0,0 +1,220 @@ |
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/*
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* Freescale MXS UARTAPP Register Definitions |
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* |
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* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> |
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* |
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* Based on code from LTIB: |
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __ARCH_ARM___MXS_UARTAPP_H |
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#define __ARCH_ARM___MXS_UARTAPP_H |
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#include <asm/imx-common/regs-common.h> |
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#ifndef __ASSEMBLY__ |
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struct mxs_uartapp_regs { |
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mxs_reg_32(hw_uartapp_ctrl0) |
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mxs_reg_32(hw_uartapp_ctrl1) |
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mxs_reg_32(hw_uartapp_ctrl2) |
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mxs_reg_32(hw_uartapp_linectrl) |
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mxs_reg_32(hw_uartapp_linectrl2) |
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mxs_reg_32(hw_uartapp_intr) |
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mxs_reg_32(hw_uartapp_data) |
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mxs_reg_32(hw_uartapp_stat) |
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mxs_reg_32(hw_uartapp_debug) |
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mxs_reg_32(hw_uartapp_version) |
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mxs_reg_32(hw_uartapp_autobaud) |
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}; |
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#endif |
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#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) |
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#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) |
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#define UARTAPP_CTRL0_RUN_MASK (1 << 29) |
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#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) |
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#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) |
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#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 |
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#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) |
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#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 |
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#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF |
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#define UARTAPP_CTRL1_RUN_MASK (1 << 28) |
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#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 |
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#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF |
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#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) |
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#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) |
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#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) |
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#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) |
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#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) |
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#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) |
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#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) |
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#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) |
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#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 |
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#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) |
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#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) |
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#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) |
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#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) |
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#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) |
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#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) |
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) |
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) |
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) |
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#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 |
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#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) |
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#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) |
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#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) |
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#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) |
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#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) |
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#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) |
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) |
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) |
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) |
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#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) |
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#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) |
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#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) |
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#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) |
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#define UARTAPP_CTRL2_RTS_MASK (1 << 11) |
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#define UARTAPP_CTRL2_DTR_MASK (1 << 10) |
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#define UARTAPP_CTRL2_RXE_MASK (1 << 9) |
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#define UARTAPP_CTRL2_TXE_MASK (1 << 8) |
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#define UARTAPP_CTRL2_LBE_MASK (1 << 7) |
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#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) |
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#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) |
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#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) |
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#define UARTAPP_CTRL2_UARTEN_MASK 0x01 |
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#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 |
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#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) |
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#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 |
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#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 |
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#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) |
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#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F |
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#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) |
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#define UARTAPP_LINECTRL_WLEN_OFFSET 5 |
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#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) |
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#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) |
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#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) |
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#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) |
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#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) |
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#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) |
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#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) |
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#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) |
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#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) |
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#define UARTAPP_LINECTRL_BRK_MASK 1 |
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#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 |
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#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) |
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#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 |
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#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 |
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#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) |
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#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F |
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#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) |
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#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 |
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#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) |
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#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) |
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#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) |
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#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) |
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#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) |
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#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) |
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#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) |
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#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) |
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#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) |
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#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) |
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#define UARTAPP_INTR_OEIEN_MASK (1 << 26) |
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#define UARTAPP_INTR_BEIEN_MASK (1 << 25) |
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#define UARTAPP_INTR_PEIEN_MASK (1 << 24) |
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#define UARTAPP_INTR_FEIEN_MASK (1 << 23) |
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#define UARTAPP_INTR_RTIEN_MASK (1 << 22) |
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#define UARTAPP_INTR_TXIEN_MASK (1 << 21) |
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#define UARTAPP_INTR_RXIEN_MASK (1 << 20) |
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#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) |
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#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) |
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#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) |
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#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) |
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#define UARTAPP_INTR_ABDIS_MASK (1 << 11) |
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#define UARTAPP_INTR_OEIS_MASK (1 << 10) |
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#define UARTAPP_INTR_BEIS_MASK (1 << 9) |
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#define UARTAPP_INTR_PEIS_MASK (1 << 8) |
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#define UARTAPP_INTR_FEIS_MASK (1 << 7) |
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#define UARTAPP_INTR_RTIS_MASK (1 << 6) |
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#define UARTAPP_INTR_TXIS_MASK (1 << 5) |
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#define UARTAPP_INTR_RXIS_MASK (1 << 4) |
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#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) |
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#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) |
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#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) |
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#define UARTAPP_INTR_RIMIS_MASK 0x1 |
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#define UARTAPP_DATA_DATA_OFFSET 0 |
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#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF |
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#define UARTAPP_STAT_PRESENT_MASK (1 << 31) |
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#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) |
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#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) |
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#define UARTAPP_STAT_HISPEED_MASK (1 << 30) |
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#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) |
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#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) |
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#define UARTAPP_STAT_BUSY_MASK (1 << 29) |
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#define UARTAPP_STAT_CTS_MASK (1 << 28) |
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#define UARTAPP_STAT_TXFE_MASK (1 << 27) |
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#define UARTAPP_STAT_RXFF_MASK (1 << 26) |
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#define UARTAPP_STAT_TXFF_MASK (1 << 25) |
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#define UARTAPP_STAT_RXFE_MASK (1 << 24) |
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#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 |
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#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) |
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|
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#define UARTAPP_STAT_OERR_MASK (1 << 19) |
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#define UARTAPP_STAT_BERR_MASK (1 << 18) |
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#define UARTAPP_STAT_PERR_MASK (1 << 17) |
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#define UARTAPP_STAT_FERR_MASK (1 << 16) |
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#define UARTAPP_STAT_RXCOUNT_OFFSET 0 |
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#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF |
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|
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#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 |
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#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) |
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#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 |
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#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) |
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|
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#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) |
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#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) |
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#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) |
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#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) |
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#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) |
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#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 |
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#define UARTAPP_VERSION_MAJOR_OFFSET 24 |
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#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) |
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|
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#define UARTAPP_VERSION_MINOR_OFFSET 16 |
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#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) |
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#define UARTAPP_VERSION_STEP_OFFSET 0 |
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#define UARTAPP_VERSION_STEP_MASK 0xFFFF |
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#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 |
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#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) |
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|
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#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 |
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#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) |
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|
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#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) |
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#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) |
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#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) |
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#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) |
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#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 |
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#endif /* __ARCH_ARM___UARTAPP_H */ |
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@ -0,0 +1,48 @@ |
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High Assurance Boot (HAB) for i.MX6 CPUs |
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|
||||
To authenticate U-Boot only by the CPU there is no code required in |
||||
U-Boot itself. However, the U-Boot image to be programmed into the |
||||
boot media needs to be properly constructed, i.e. it must contain a |
||||
proper Command Sequence File (CSF). |
||||
|
||||
The Initial Vector Table contains a pointer to the CSF. Please see |
||||
doc/README.imximage for how to prepare u-boot.imx. |
||||
|
||||
The CSF itself is being generated by Freescale HAB tools. |
||||
|
||||
mkimage will output additional information about "HAB Blocks" |
||||
which can be used in the Freescale tooling to authenticate U-Boot |
||||
(entries in the CSF file). |
||||
|
||||
Image Type: Freescale IMX Boot Image |
||||
Image Ver: 2 (i.MX53/6 compatible) |
||||
Data Size: 327680 Bytes = 320.00 kB = 0.31 MB |
||||
Load Address: 177ff420 |
||||
Entry Point: 17800000 |
||||
HAB Blocks: 177ff400 00000000 0004dc00 |
||||
^^^^^^^^ ^^^^^^^^ ^^^^^^^^ |
||||
| | | |
||||
| | -------- (1) |
||||
| | |
||||
| ------------------- (2) |
||||
| |
||||
--------------------------- (3) |
||||
|
||||
(1) Size of area in file u-boot.imx to sign |
||||
This area should include the IVT, the Boot Data the DCD |
||||
and U-Boot itself. |
||||
(2) Start of area in u-boot.imx to sign |
||||
(3) Start of area in RAM to authenticate |
||||
|
||||
CONFIG_SECURE_BOOT currently enables only an additional command |
||||
'hab_status' in U-Boot to retrieve the HAB status and events. This |
||||
can be useful while developing and testing HAB. |
||||
|
||||
Commands to generate a signed U-Boot using Freescale HAB tools: |
||||
cst --o U-Boot_CSF.bin < U-Boot.CSF |
||||
objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0x00 \ |
||||
U-Boot_CSF.bin U-Boot_CSF_pad.bin |
||||
cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx |
||||
|
||||
NOTE: U-Boot_CSF.bin needs to be padded to the value specified in |
||||
the imximage.cfg file. |
||||
@ -0,0 +1,165 @@ |
||||
Freescale i.MX233/i.MX28 SB image generator via mkimage |
||||
======================================================= |
||||
|
||||
This tool allows user to produce SB BootStream encrypted with a zero key. |
||||
Such a BootStream is then bootable on i.MX23/i.MX28. |
||||
|
||||
Usage -- producing image: |
||||
========================= |
||||
The mxsimage tool is targeted to be a simple replacement for the elftosb2 . |
||||
To generate an image, write an image configuration file and run: |
||||
|
||||
mkimage -A arm -O u-boot -T mxsimage -n <path to configuration file> \ |
||||
<output bootstream file> |
||||
|
||||
The output bootstream file is usually using the .sb file extension. Note |
||||
that the example configuration files for producing bootable BootStream with |
||||
the U-Boot bootloader can be found under arch/arm/boot/cpu/arm926ejs/mxs/ |
||||
directory. See the following files: |
||||
|
||||
mxsimage.mx23.cfg -- This is an example configuration for i.MX23 |
||||
mxsimage.mx28.cfg -- This is an example configuration for i.MX28 |
||||
|
||||
Each configuration file uses very simple instruction semantics and a few |
||||
additional rules have to be followed so that a useful image can be produced. |
||||
These semantics and rules will be outlined now. |
||||
|
||||
- Each line of the configuration file contains exactly one instruction. |
||||
- Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 . |
||||
- The configuration file is a concatenation of blocks called "sections" and |
||||
optionally "DCD blocks" (see below). |
||||
- Each "section" is started by the "SECTION" instruction. |
||||
- The "SECTION" instruction has the following semantics: |
||||
|
||||
SECTION u32_section_number [BOOTABLE] |
||||
- u32_section_number :: User-selected ID of the section |
||||
- BOOTABLE :: Sets the section as bootable |
||||
|
||||
- A bootable section is one from which the BootROM starts executing |
||||
subsequent instructions or code. Exactly one section must be selected |
||||
as bootable, usually the one containing the instructions and data to |
||||
load the bootloader. |
||||
|
||||
- A "SECTION" must be immediatelly followed by a "TAG" instruction. |
||||
- The "TAG" instruction has the following semantics: |
||||
|
||||
TAG [LAST] |
||||
- LAST :: Flag denoting the last section in the file |
||||
|
||||
- After a "TAG" unstruction, any of the following instructions may follow |
||||
in any order and any quantity: |
||||
|
||||
NOOP |
||||
- This instruction does nothing |
||||
|
||||
LOAD u32_address string_filename |
||||
- Instructs the BootROM to load file pointed by "string_filename" onto |
||||
address "u32_address". |
||||
|
||||
LOAD IVT u32_address u32_IVT_entry_point |
||||
- Crafts and loads IVT onto address "u32_address" with the entry point |
||||
of u32_IVT_entry_point. |
||||
- i.MX28-specific instruction! |
||||
|
||||
LOAD DCD u32_address u32_DCD_block_ID |
||||
- Loads the DCD block with ID "u32_DCD_block_ID" onto address |
||||
"u32_address" and executes the contents of this DCD block |
||||
- i.MX28-specific instruction! |
||||
|
||||
FILL u32_address u32_pattern u32_length |
||||
- Starts to write memory from addres "u32_address" with a pattern |
||||
specified by "u32_pattern". Writes exactly "u32_length" bytes of the |
||||
pattern. |
||||
|
||||
JUMP [HAB] u32_address [u32_r0_arg] |
||||
- Jumps onto memory address specified by "u32_address" by setting this |
||||
address in PT. The BootROM will pass the "u32_r0_arg" value in ARM |
||||
register "r0" to the executed code if this option is specified. |
||||
Otherwise, ARM register "r0" will default to value 0x00000000. The |
||||
optional "HAB" flag is i.MX28-specific flag turning on the HAB boot. |
||||
|
||||
CALL [HAB] u32_address [u32_r0_arg] |
||||
- See JUMP instruction above, as the operation is exactly the same with |
||||
one difference. The CALL instruction does allow returning into the |
||||
BootROM from the executed code. U-Boot makes use of this in it's SPL |
||||
code. |
||||
|
||||
MODE string_mode |
||||
- Restart the CPU and start booting from device specified by the |
||||
"string_mode" argument. The "string_mode" differs for each CPU |
||||
and can be: |
||||
i.MX23, string_mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH |
||||
JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1 |
||||
i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH |
||||
JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1 |
||||
|
||||
- An optional "DCD" blocks can be added at the begining of the configuration |
||||
file. Note that the DCD is only supported on i.MX28. |
||||
- The DCD blocks must be inserted before the first "section" in the |
||||
configuration file. |
||||
- The DCD block has the following semantics: |
||||
|
||||
DCD u32_DCD_block_ID |
||||
- u32_DCD_block_ID :: The ID number of the DCD block, must match |
||||
the ID number used by "LOAD DCD" instruction. |
||||
|
||||
- The DCD block must be followed by one of the following instructions. All |
||||
of the instructions operate either on 1, 2 or 4 bytes. This is selected by |
||||
the 'n' suffix of the instruction: |
||||
|
||||
WRITE.n u32_address u32_value |
||||
- Write the "u32_value" to the "u32_address" address. |
||||
|
||||
ORR.n u32_address u32_value |
||||
- Read the "u32_address", perform a bitwise-OR with the "u32_value" and |
||||
write the result back to "u32_address". |
||||
|
||||
ANDC.n u32_address u32_value |
||||
- Read the "u32_address", perform a bitwise-AND with the complement of |
||||
"u32_value" and write the result back to "u32_address". |
||||
|
||||
EQZ.n u32_address u32_count |
||||
- Read the "u32_address" at most "u32_count" times and test if the value |
||||
read is zero. If it is, break the loop earlier. |
||||
|
||||
NEZ.n u32_address u32_count |
||||
- Read the "u32_address" at most "u32_count" times and test if the value |
||||
read is non-zero. If it is, break the loop earlier. |
||||
|
||||
EQ.n u32_address u32_mask |
||||
- Read the "u32_address" in a loop and test if the result masked with |
||||
"u32_mask" equals the "u32_mask". If the values are equal, break the |
||||
reading loop. |
||||
|
||||
NEQ.n u32_address u32_mask |
||||
- Read the "u32_address" in a loop and test if the result masked with |
||||
"u32_mask" does not equal the "u32_mask". If the values are not equal, |
||||
break the reading loop. |
||||
|
||||
NOOP |
||||
- This instruction does nothing. |
||||
|
||||
- If the verbose output from the BootROM is enabled, the BootROM will produce a |
||||
letter on the Debug UART for each instruction it started processing. Here is a |
||||
mapping between the above instructions and the BootROM verbose output: |
||||
|
||||
H -- SB Image header loaded |
||||
T -- TAG instruction |
||||
N -- NOOP instruction |
||||
L -- LOAD instruction |
||||
F -- FILL instruction |
||||
J -- JUMP instruction |
||||
C -- CALL instruction |
||||
M -- MODE instruction |
||||
|
||||
Usage -- verifying image: |
||||
========================= |
||||
|
||||
The mxsimage can also verify and dump contents of an image. Use the following |
||||
syntax to verify and dump contents of an image: |
||||
|
||||
mkimage -l <input bootstream file> |
||||
|
||||
This will output all the information from the SB image header and all the |
||||
instructions contained in the SB image. It will also check if the various |
||||
checksums in the SB image are correct. |
||||
@ -0,0 +1,151 @@ |
||||
/*
|
||||
* Freescale i.MX23/i.MX28 AUART driver |
||||
* |
||||
* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> |
||||
* |
||||
* Based on the MXC serial driver: |
||||
* |
||||
* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> |
||||
* |
||||
* Further based on the Linux mxs-auart.c driver: |
||||
* |
||||
* Freescale STMP37XX/STMP38X Application UART drkiver |
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <serial.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/arch/regs-base.h> |
||||
#include <asm/arch/regs-uartapp.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifndef CONFIG_MXS_AUART_BASE |
||||
#error "CONFIG_MXS_AUART_BASE must be set to the base UART to use" |
||||
#endif |
||||
|
||||
/* AUART clock always supplied by XTAL and always 24MHz */ |
||||
#define MXS_AUART_CLK 24000000 |
||||
|
||||
static struct mxs_uartapp_regs *get_uartapp_registers(void) |
||||
{ |
||||
return (struct mxs_uartapp_regs *)CONFIG_MXS_AUART_BASE; |
||||
} |
||||
|
||||
/**
|
||||
* Sets the baud rate and settings. |
||||
* The settings are: 8 data bits, no parit and 1 stop bit. |
||||
*/ |
||||
void mxs_auart_setbrg(void) |
||||
{ |
||||
u32 div; |
||||
u32 linectrl = 0; |
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers(); |
||||
|
||||
if (!gd->baudrate) |
||||
gd->baudrate = CONFIG_BAUDRATE; |
||||
|
||||
/*
|
||||
* From i.MX28 datasheet: |
||||
* div is calculated by calculating UARTCLK*32/baudrate, rounded to int |
||||
* div must be between 0xEC and 0x003FFFC0 inclusive |
||||
* Lowest 6 bits of div goes in BAUD_DIVFRAC part of LINECTRL register |
||||
* Next 16 bits goes in BAUD_DIVINT part of LINECTRL register |
||||
*/ |
||||
div = (MXS_AUART_CLK * 32) / gd->baudrate; |
||||
if (div < 0xEC || div > 0x003FFFC0) |
||||
return; |
||||
|
||||
linectrl |= ((div & UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK) << |
||||
UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET) & |
||||
UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK; |
||||
linectrl |= ((div >> UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET) << |
||||
UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET) & |
||||
UARTAPP_LINECTRL_BAUD_DIVINT_MASK; |
||||
|
||||
/* Word length: 8 bits */ |
||||
linectrl |= UARTAPP_LINECTRL_WLEN_8BITS; |
||||
|
||||
/* Enable FIFOs. */ |
||||
linectrl |= UARTAPP_LINECTRL_FEN_MASK; |
||||
|
||||
/* Write above settings, no parity, 1 stop bit */ |
||||
writel(linectrl, ®s->hw_uartapp_linectrl); |
||||
} |
||||
|
||||
int mxs_auart_init(void) |
||||
{ |
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers(); |
||||
/* Reset everything */ |
||||
mxs_reset_block(®s->hw_uartapp_ctrl0_reg); |
||||
/* Disable interrupts */ |
||||
writel(0, ®s->hw_uartapp_intr); |
||||
/* Set baud rate and settings */ |
||||
serial_setbrg(); |
||||
/* Disable RTS and CTS, ignore LINECTRL2 register */ |
||||
writel(UARTAPP_CTRL2_RTSEN_MASK | |
||||
UARTAPP_CTRL2_CTSEN_MASK | |
||||
UARTAPP_CTRL2_USE_LCR2_MASK, |
||||
®s->hw_uartapp_ctrl2_clr); |
||||
/* Enable receiver, transmitter and UART */ |
||||
writel(UARTAPP_CTRL2_RXE_MASK | |
||||
UARTAPP_CTRL2_TXE_MASK | |
||||
UARTAPP_CTRL2_UARTEN_MASK, |
||||
®s->hw_uartapp_ctrl2_set); |
||||
return 0; |
||||
} |
||||
|
||||
void mxs_auart_putc(const char c) |
||||
{ |
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers(); |
||||
/* Wait in loop while the transmit FIFO is full */ |
||||
while (readl(®s->hw_uartapp_stat) & UARTAPP_STAT_TXFF_MASK) |
||||
; |
||||
|
||||
writel(c, ®s->hw_uartapp_data); |
||||
|
||||
if (c == '\n') |
||||
mxs_auart_putc('\r'); |
||||
} |
||||
|
||||
int mxs_auart_tstc(void) |
||||
{ |
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers(); |
||||
/* Checks if receive FIFO is empty */ |
||||
return !(readl(®s->hw_uartapp_stat) & UARTAPP_STAT_RXFE_MASK); |
||||
} |
||||
|
||||
int mxs_auart_getc(void) |
||||
{ |
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers(); |
||||
/* Wait until a character is available to read */ |
||||
while (!mxs_auart_tstc()) |
||||
; |
||||
/* Read the character from the data register */ |
||||
return readl(®s->hw_uartapp_data) & 0xFF; |
||||
} |
||||
|
||||
static struct serial_device mxs_auart_drv = { |
||||
.name = "mxs_auart_serial", |
||||
.start = mxs_auart_init, |
||||
.stop = NULL, |
||||
.setbrg = mxs_auart_setbrg, |
||||
.putc = mxs_auart_putc, |
||||
.puts = default_serial_puts, |
||||
.getc = mxs_auart_getc, |
||||
.tstc = mxs_auart_tstc, |
||||
}; |
||||
|
||||
void mxs_auart_initialize(void) |
||||
{ |
||||
serial_register(&mxs_auart_drv); |
||||
} |
||||
|
||||
__weak struct serial_device *default_serial_console(void) |
||||
{ |
||||
return &mxs_auart_drv; |
||||
} |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,230 @@ |
||||
/*
|
||||
* Freescale i.MX28 SB image generator |
||||
* |
||||
* Copyright (C) 2012 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __MXSSB_H__ |
||||
#define __MXSSB_H__ |
||||
|
||||
#include <stdint.h> |
||||
#include <arpa/inet.h> |
||||
|
||||
#define SB_BLOCK_SIZE 16 |
||||
|
||||
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) |
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) |
||||
|
||||
struct sb_boot_image_version { |
||||
uint16_t major; |
||||
uint16_t pad0; |
||||
uint16_t minor; |
||||
uint16_t pad1; |
||||
uint16_t revision; |
||||
uint16_t pad2; |
||||
}; |
||||
|
||||
struct sb_boot_image_header { |
||||
union { |
||||
/* SHA1 of the header. */ |
||||
uint8_t digest[20]; |
||||
struct { |
||||
/* CBC-MAC initialization vector. */ |
||||
uint8_t iv[16]; |
||||
uint8_t extra[4]; |
||||
}; |
||||
}; |
||||
/* 'STMP' */ |
||||
uint8_t signature1[4]; |
||||
/* Major version of the image format. */ |
||||
uint8_t major_version; |
||||
/* Minor version of the image format. */ |
||||
uint8_t minor_version; |
||||
/* Flags associated with the image. */ |
||||
uint16_t flags; |
||||
/* Size of the image in 16b blocks. */ |
||||
uint32_t image_blocks; |
||||
/* Offset of the first tag in 16b blocks. */ |
||||
uint32_t first_boot_tag_block; |
||||
/* ID of the section to boot from. */ |
||||
uint32_t first_boot_section_id; |
||||
/* Amount of crypto keys. */ |
||||
uint16_t key_count; |
||||
/* Offset to the key dictionary in 16b blocks. */ |
||||
uint16_t key_dictionary_block; |
||||
/* Size of this header in 16b blocks. */ |
||||
uint16_t header_blocks; |
||||
/* Amount of section headers. */ |
||||
uint16_t section_count; |
||||
/* Section header size in 16b blocks. */ |
||||
uint16_t section_header_size; |
||||
/* Padding to align timestamp to uint64_t. */ |
||||
uint8_t padding0[2]; |
||||
/* 'sgtl' (since v1.1) */ |
||||
uint8_t signature2[4]; |
||||
/* Image generation date, in microseconds since 1.1.2000 . */ |
||||
uint64_t timestamp_us; |
||||
/* Product version. */ |
||||
struct sb_boot_image_version |
||||
product_version; |
||||
/* Component version. */ |
||||
struct sb_boot_image_version |
||||
component_version; |
||||
/* Drive tag for the system drive. (since v1.1) */ |
||||
uint16_t drive_tag; |
||||
/* Padding. */ |
||||
uint8_t padding1[6]; |
||||
}; |
||||
|
||||
#define SB_VERSION_MAJOR 1 |
||||
#define SB_VERSION_MINOR 1 |
||||
|
||||
/* Enable to HTLLC verbose boot report. */ |
||||
#define SB_IMAGE_FLAG_VERBOSE (1 << 0) |
||||
|
||||
struct sb_key_dictionary_key { |
||||
/* The CBC-MAC of image and sections header. */ |
||||
uint8_t cbc_mac[SB_BLOCK_SIZE]; |
||||
/* The AES key encrypted by image key (zero). */ |
||||
uint8_t key[SB_BLOCK_SIZE]; |
||||
}; |
||||
|
||||
struct sb_ivt_header { |
||||
uint32_t header; |
||||
uint32_t entry; |
||||
uint32_t reserved1; |
||||
uint32_t dcd; |
||||
uint32_t boot_data; |
||||
uint32_t self; |
||||
uint32_t csf; |
||||
uint32_t reserved2; |
||||
}; |
||||
|
||||
#define SB_HAB_IVT_TAG 0xd1UL |
||||
#define SB_HAB_DCD_TAG 0xd2UL |
||||
|
||||
#define SB_HAB_VERSION 0x40UL |
||||
|
||||
/*
|
||||
* The "size" field in the IVT header is not naturally aligned, |
||||
* use this macro to fill first 4 bytes of the IVT header without |
||||
* causing issues on some systems (esp. M68k, PPC, MIPS-BE, ARM-BE). |
||||
*/ |
||||
static inline uint32_t sb_hab_ivt_header(void) |
||||
{ |
||||
uint32_t ret = 0; |
||||
ret |= SB_HAB_IVT_TAG << 24; |
||||
ret |= sizeof(struct sb_ivt_header) << 16; |
||||
ret |= SB_HAB_VERSION; |
||||
return htonl(ret); |
||||
} |
||||
|
||||
struct sb_sections_header { |
||||
/* Section number. */ |
||||
uint32_t section_number; |
||||
/* Offset of this sections first instruction after "TAG". */ |
||||
uint32_t section_offset; |
||||
/* Size of the section in 16b blocks. */ |
||||
uint32_t section_size; |
||||
/* Section flags. */ |
||||
uint32_t section_flags; |
||||
}; |
||||
|
||||
#define SB_SECTION_FLAG_BOOTABLE (1 << 0) |
||||
|
||||
struct sb_command { |
||||
struct { |
||||
uint8_t checksum; |
||||
uint8_t tag; |
||||
uint16_t flags; |
||||
#define ROM_TAG_CMD_FLAG_ROM_LAST_TAG 0x1 |
||||
#define ROM_LOAD_CMD_FLAG_DCD_LOAD 0x1 /* MX28 only */ |
||||
#define ROM_JUMP_CMD_FLAG_HAB 0x1 /* MX28 only */ |
||||
#define ROM_CALL_CMD_FLAG_HAB 0x1 /* MX28 only */ |
||||
} header; |
||||
|
||||
union { |
||||
struct { |
||||
uint32_t reserved[3]; |
||||
} nop; |
||||
struct { |
||||
uint32_t section_number; |
||||
uint32_t section_length; |
||||
uint32_t section_flags; |
||||
} tag; |
||||
struct { |
||||
uint32_t address; |
||||
uint32_t count; |
||||
uint32_t crc32; |
||||
} load; |
||||
struct { |
||||
uint32_t address; |
||||
uint32_t count; |
||||
uint32_t pattern; |
||||
} fill; |
||||
struct { |
||||
uint32_t address; |
||||
uint32_t reserved; |
||||
/* Passed in register r0 before JUMP */ |
||||
uint32_t argument; |
||||
} jump; |
||||
struct { |
||||
uint32_t address; |
||||
uint32_t reserved; |
||||
/* Passed in register r0 before CALL */ |
||||
uint32_t argument; |
||||
} call; |
||||
struct { |
||||
uint32_t reserved1; |
||||
uint32_t reserved2; |
||||
uint32_t mode; |
||||
} mode; |
||||
|
||||
}; |
||||
}; |
||||
|
||||
/*
|
||||
* Most of the mode names are same or at least similar |
||||
* on i.MX23 and i.MX28, but some of the mode names |
||||
* differ. The "name" field represents the mode name |
||||
* on i.MX28 as seen in Table 12-2 of the datasheet. |
||||
* The "altname" field represents the differently named |
||||
* fields on i.MX23 as seen in Table 35-3 of the |
||||
* datasheet. |
||||
*/ |
||||
static const struct { |
||||
const char *name; |
||||
const char *altname; |
||||
const uint8_t mode; |
||||
} modetable[] = { |
||||
{ "USB", NULL, 0x00 }, |
||||
{ "I2C", NULL, 0x01 }, |
||||
{ "SPI2_FLASH", "SPI1_FLASH", 0x02 }, |
||||
{ "SPI3_FLASH", "SPI2_FLASH", 0x03 }, |
||||
{ "NAND_BCH", NULL, 0x04 }, |
||||
{ "JTAG", NULL, 0x06 }, |
||||
{ "SPI3_EEPROM", "SPI2_EEPROM", 0x08 }, |
||||
{ "SD_SSP0", NULL, 0x09 }, |
||||
{ "SD_SSP1", NULL, 0x0A } |
||||
}; |
||||
|
||||
enum sb_tag { |
||||
ROM_NOP_CMD = 0x00, |
||||
ROM_TAG_CMD = 0x01, |
||||
ROM_LOAD_CMD = 0x02, |
||||
ROM_FILL_CMD = 0x03, |
||||
ROM_JUMP_CMD = 0x04, |
||||
ROM_CALL_CMD = 0x05, |
||||
ROM_MODE_CMD = 0x06 |
||||
}; |
||||
|
||||
struct sb_source_entry { |
||||
uint8_t tag; |
||||
uint32_t address; |
||||
uint32_t flags; |
||||
char *filename; |
||||
}; |
||||
|
||||
#endif /* __MXSSB_H__ */ |
||||
Loading…
Reference in new issue