Add a MISC driver with read and write access to BSEC IP (Boot and Security and OTP control) - offset 0: shadowed values - offset 0x80000000: OTP fuse box values (SAFMEM) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>lime2-spi
Patrick Delaunay
7 years ago
committed by
Tom Rini
parent
de20e43794
commit
19f589923a
@ -0,0 +1,431 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <misc.h> |
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#include <asm/io.h> |
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#include <linux/iopoll.h> |
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#define BSEC_OTP_MAX_VALUE 95 |
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#define BSEC_TIMEOUT_US 10000 |
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/* BSEC REGISTER OFFSET (base relative) */ |
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#define BSEC_OTP_CONF_OFF 0x000 |
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#define BSEC_OTP_CTRL_OFF 0x004 |
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#define BSEC_OTP_WRDATA_OFF 0x008 |
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#define BSEC_OTP_STATUS_OFF 0x00C |
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#define BSEC_OTP_LOCK_OFF 0x010 |
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#define BSEC_DISTURBED_OFF 0x01C |
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#define BSEC_ERROR_OFF 0x034 |
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#define BSEC_SPLOCK_OFF 0x064 /* Program safmem sticky lock */ |
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#define BSEC_SWLOCK_OFF 0x07C /* write in OTP sticky lock */ |
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#define BSEC_SRLOCK_OFF 0x094 /* shadowing sticky lock */ |
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#define BSEC_OTP_DATA_OFF 0x200 |
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/* BSEC_CONFIGURATION Register MASK */ |
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#define BSEC_CONF_POWER_UP 0x001 |
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/* BSEC_CONTROL Register */ |
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#define BSEC_READ 0x000 |
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#define BSEC_WRITE 0x100 |
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/* LOCK Register */ |
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#define OTP_LOCK_MASK 0x1F |
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#define OTP_LOCK_BANK_SHIFT 0x05 |
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#define OTP_LOCK_BIT_MASK 0x01 |
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/* STATUS Register */ |
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#define BSEC_MODE_BUSY_MASK 0x08 |
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#define BSEC_MODE_PROGFAIL_MASK 0x10 |
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#define BSEC_MODE_PWR_MASK 0x20 |
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/*
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* OTP Lock services definition |
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* Value must corresponding to the bit number in the register |
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*/ |
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#define BSEC_LOCK_PROGRAM 0x04 |
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/**
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* bsec_check_error() - Check status of one otp |
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* @base: base address of bsec IP |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* Return: 0 if no error, -EAGAIN or -ENOTSUPP |
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*/ |
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static u32 bsec_check_error(u32 base, u32 otp) |
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{ |
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u32 bit; |
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u32 bank; |
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bit = 1 << (otp & OTP_LOCK_MASK); |
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bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); |
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if (readl(base + BSEC_DISTURBED_OFF + bank) & bit) |
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return -EAGAIN; |
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else if (readl(base + BSEC_ERROR_OFF + bank) & bit) |
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return -ENOTSUPP; |
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return 0; |
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} |
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/**
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* bsec_lock() - manage lock for each type SR/SP/SW |
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* @address: address of bsec IP register |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* Return: true if locked else false |
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*/ |
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static bool bsec_read_lock(u32 address, u32 otp) |
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{ |
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u32 bit; |
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u32 bank; |
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bit = 1 << (otp & OTP_LOCK_MASK); |
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bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); |
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return !!(readl(address + bank) & bit); |
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} |
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/**
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* bsec_read_SR_lock() - read SR lock (Shadowing) |
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* @base: base address of bsec IP |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* Return: true if locked else false |
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*/ |
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static bool bsec_read_SR_lock(u32 base, u32 otp) |
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{ |
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return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp); |
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} |
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/**
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* bsec_read_SP_lock() - read SP lock (program Lock) |
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* @base: base address of bsec IP |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* Return: true if locked else false |
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*/ |
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static bool bsec_read_SP_lock(u32 base, u32 otp) |
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{ |
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return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp); |
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} |
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/**
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* bsec_SW_lock() - manage SW lock (Write in Shadow) |
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* @base: base address of bsec IP |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* Return: true if locked else false |
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*/ |
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static bool bsec_read_SW_lock(u32 base, u32 otp) |
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{ |
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return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp); |
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} |
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/**
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* bsec_power_safmem() - Activate or deactivate safmem power |
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* @base: base address of bsec IP |
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* @power: true to power up , false to power down |
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* Return: 0 if succeed |
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*/ |
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static int bsec_power_safmem(u32 base, bool power) |
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{ |
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u32 val; |
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u32 mask; |
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if (power) { |
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setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP); |
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mask = BSEC_MODE_PWR_MASK; |
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} else { |
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clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP); |
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mask = 0; |
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} |
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/* waiting loop */ |
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return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF, |
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val, (val & BSEC_MODE_PWR_MASK) == mask, |
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BSEC_TIMEOUT_US); |
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} |
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/**
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* bsec_shadow_register() - copy safmen otp to bsec data |
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* @base: base address of bsec IP |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* Return: 0 if no error |
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*/ |
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static int bsec_shadow_register(u32 base, u32 otp) |
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{ |
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u32 val; |
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int ret; |
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bool power_up = false; |
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/* check if shadowing of otp is locked */ |
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if (bsec_read_SR_lock(base, otp)) |
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pr_debug("bsec : OTP %d is locked and refreshed with 0\n", otp); |
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/* check if safemem is power up */ |
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val = readl(base + BSEC_OTP_STATUS_OFF); |
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if (!(val & BSEC_MODE_PWR_MASK)) { |
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ret = bsec_power_safmem(base, true); |
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if (ret) |
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return ret; |
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power_up = 1; |
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} |
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/* set BSEC_OTP_CTRL_OFF with the otp value*/ |
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writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF); |
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/* check otp status*/ |
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ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF, |
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val, (val & BSEC_MODE_BUSY_MASK) == 0, |
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BSEC_TIMEOUT_US); |
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if (ret) |
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return ret; |
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ret = bsec_check_error(base, otp); |
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if (power_up) |
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bsec_power_safmem(base, false); |
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return ret; |
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} |
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/**
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* bsec_read_shadow() - read an otp data value from shadow |
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* @base: base address of bsec IP |
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* @val: read value |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* Return: 0 if no error |
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*/ |
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static int bsec_read_shadow(u32 base, u32 *val, u32 otp) |
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{ |
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*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32)); |
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return bsec_check_error(base, otp); |
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} |
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/**
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* bsec_write_shadow() - write value in BSEC data register in shadow |
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* @base: base address of bsec IP |
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* @val: value to write |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* Return: 0 if no error |
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*/ |
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static int bsec_write_shadow(u32 base, u32 val, u32 otp) |
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{ |
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/* check if programming of otp is locked */ |
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if (bsec_read_SW_lock(base, otp)) |
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pr_debug("bsec : OTP %d is lock, write will be ignore\n", otp); |
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writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32)); |
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return bsec_check_error(base, otp); |
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} |
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/**
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* bsec_program_otp() - program a bit in SAFMEM |
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* @base: base address of bsec IP |
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* @val: value to program |
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE) |
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* after the function the otp data is not refreshed in shadow |
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* Return: 0 if no error |
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*/ |
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static int bsec_program_otp(long base, u32 val, u32 otp) |
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{ |
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u32 ret; |
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bool power_up = false; |
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if (bsec_read_SP_lock(base, otp)) |
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pr_debug("bsec : OTP %d locked, prog will be ignore\n", otp); |
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if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM)) |
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pr_debug("bsec : Global lock, prog will be ignore\n"); |
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/* check if safemem is power up */ |
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if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) { |
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ret = bsec_power_safmem(base, true); |
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if (ret) |
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return ret; |
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power_up = true; |
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} |
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/* set value in write register*/ |
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writel(val, base + BSEC_OTP_WRDATA_OFF); |
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/* set BSEC_OTP_CTRL_OFF with the otp value */ |
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writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF); |
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/* check otp status*/ |
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ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF, |
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val, (val & BSEC_MODE_BUSY_MASK) == 0, |
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BSEC_TIMEOUT_US); |
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if (ret) |
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return ret; |
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if (val & BSEC_MODE_PROGFAIL_MASK) |
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ret = -EACCES; |
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else |
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ret = bsec_check_error(base, otp); |
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if (power_up) |
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bsec_power_safmem(base, false); |
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return ret; |
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} |
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/* BSEC MISC driver *******************************************************/ |
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struct stm32mp_bsec_platdata { |
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u32 base; |
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}; |
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static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) |
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{ |
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struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); |
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u32 tmp_data = 0; |
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int ret; |
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/* read current shadow value */ |
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ret = bsec_read_shadow(plat->base, &tmp_data, otp); |
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if (ret) |
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return ret; |
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/* copy otp in shadow */ |
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ret = bsec_shadow_register(plat->base, otp); |
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if (ret) |
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return ret; |
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ret = bsec_read_shadow(plat->base, val, otp); |
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if (ret) |
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return ret; |
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/* restore shadow value */ |
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ret = bsec_write_shadow(plat->base, tmp_data, otp); |
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return ret; |
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} |
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static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) |
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{ |
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struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); |
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return bsec_read_shadow(plat->base, val, otp); |
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} |
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static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) |
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{ |
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struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); |
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return bsec_program_otp(plat->base, val, otp); |
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} |
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static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) |
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{ |
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struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); |
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return bsec_write_shadow(plat->base, val, otp); |
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} |
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static int stm32mp_bsec_read(struct udevice *dev, int offset, |
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void *buf, int size) |
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{ |
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int ret; |
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int i; |
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bool shadow = true; |
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int nb_otp = size / sizeof(u32); |
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int otp; |
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if (offset >= STM32_BSEC_OTP_OFFSET) { |
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offset -= STM32_BSEC_OTP_OFFSET; |
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shadow = false; |
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} |
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otp = offset / sizeof(u32); |
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if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) { |
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dev_err(dev, "wrong value for otp, max value : %i\n", |
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BSEC_OTP_MAX_VALUE); |
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return -EINVAL; |
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} |
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for (i = otp; i < (otp + nb_otp); i++) { |
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u32 *addr = &((u32 *)buf)[i - otp]; |
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if (shadow) |
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ret = stm32mp_bsec_read_shadow(dev, addr, i); |
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else |
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ret = stm32mp_bsec_read_otp(dev, addr, i); |
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if (ret) |
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break; |
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} |
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return ret; |
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} |
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static int stm32mp_bsec_write(struct udevice *dev, int offset, |
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const void *buf, int size) |
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{ |
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int ret = 0; |
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int i; |
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bool shadow = true; |
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int nb_otp = size / sizeof(u32); |
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int otp; |
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if (offset >= STM32_BSEC_OTP_OFFSET) { |
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offset -= STM32_BSEC_OTP_OFFSET; |
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shadow = false; |
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} |
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otp = offset / sizeof(u32); |
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if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) { |
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dev_err(dev, "wrong value for otp, max value : %d\n", |
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BSEC_OTP_MAX_VALUE); |
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return -EINVAL; |
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} |
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for (i = otp; i < otp + nb_otp; i++) { |
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u32 *val = &((u32 *)buf)[i - otp]; |
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if (shadow) |
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ret = stm32mp_bsec_write_shadow(dev, *val, i); |
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else |
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ret = stm32mp_bsec_write_otp(dev, *val, i); |
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if (ret) |
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break; |
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} |
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return ret; |
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} |
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static const struct misc_ops stm32mp_bsec_ops = { |
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.read = stm32mp_bsec_read, |
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.write = stm32mp_bsec_write, |
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}; |
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static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); |
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plat->base = (u32)dev_read_addr_ptr(dev); |
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return 0; |
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} |
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static const struct udevice_id stm32mp_bsec_ids[] = { |
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{ .compatible = "st,stm32mp-bsec" }, |
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{} |
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}; |
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U_BOOT_DRIVER(stm32mp_bsec) = { |
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.name = "stm32mp_bsec", |
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.id = UCLASS_MISC, |
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.of_match = stm32mp_bsec_ids, |
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.ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata, |
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.platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata), |
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.ops = &stm32mp_bsec_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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}; |
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/* bsec IP is not present in device tee, manage IP address by platdata */ |
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static struct stm32mp_bsec_platdata stm32_bsec_platdata = { |
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.base = STM32_BSEC_BASE, |
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}; |
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U_BOOT_DEVICE(stm32mp_bsec) = { |
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.name = "stm32mp_bsec", |
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.platdata = &stm32_bsec_platdata, |
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}; |
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