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@ -75,6 +75,7 @@ typedef volatile unsigned int * dv_reg_p; |
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) |
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) |
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) |
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#define DAVINCI_DDR_BASE (0x80000000) |
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#ifdef CONFIG_SOC_DM644X |
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#define DAVINCI_UART2_BASE 0x01c20800 |
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@ -99,6 +100,11 @@ typedef volatile unsigned int * dv_reg_p; |
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000 |
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#define DAVINCI_MMC_SD0_BASE 0x01e11000 |
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#elif defined(CONFIG_SOC_DM365) |
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#define DAVINCI_MMC_SD1_BASE 0x01d00000 |
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 |
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#define DAVINCI_MMC_SD0_BASE 0x01d11000 |
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#endif |
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/* Power and Sleep Controller (PSC) Domains */ |
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