@ -235,17 +235,8 @@ in_flash:
bl e n a b l e _ e x t _ a d d r
/* setup the bats */
bl s e t u p _ b a t s
sync
# if ( C F G _ C C S R B A R _ D E F A U L T ! = C F G _ C C S R B A R )
/* setup ccsrbar */
bl s e t u p _ c c s r b a r
# endif
bl e a r l y _ b a t s
/* setup the law entries */
bl l a w _ e n t r y
sync
/ *
* Cache m u s t b e e n a b l e d h e r e f o r s t a c k - i n - c a c h e t r i c k .
* This m e a n s w e n e e d t o e n a b l e t h e B A T S .
@ -282,6 +273,19 @@ in_flash:
GET_ G O T / * i n i t i a l i z e G O T a c c e s s * /
/* setup the rest of the bats */
bl s e t u p _ b a t s
bl c l e a r _ t l b s
sync
# if ( C F G _ C C S R B A R _ D E F A U L T ! = C F G _ C C S R B A R )
/* setup ccsrbar */
bl s e t u p _ c c s r b a r
# endif
bl l a w _ e n t r y
sync
/* run low-level CPU init code (from Flash) */
bl c p u _ i n i t _ f
sync
@ -359,6 +363,7 @@ invalidate_bats:
/* setup_bats - set them up to some initial state */
/* Skip any BATS setup in early_bats */
.globl setup_bats
setup_bats :
@ -454,42 +459,6 @@ setup_bats:
mtspr D B A T 4 U , r3
isync
/* IBAT 5 */
addis r4 , r0 , C F G _ I B A T 5 L @h
ori r4 , r4 , C F G _ I B A T 5 L @l
addis r3 , r0 , C F G _ I B A T 5 U @h
ori r3 , r3 , C F G _ I B A T 5 U @l
mtspr I B A T 5 L , r4
mtspr I B A T 5 U , r3
isync
/* DBAT 5 */
addis r4 , r0 , C F G _ D B A T 5 L @h
ori r4 , r4 , C F G _ D B A T 5 L @l
addis r3 , r0 , C F G _ D B A T 5 U @h
ori r3 , r3 , C F G _ D B A T 5 U @l
mtspr D B A T 5 L , r4
mtspr D B A T 5 U , r3
isync
/* IBAT 6 */
addis r4 , r0 , C F G _ I B A T 6 L @h
ori r4 , r4 , C F G _ I B A T 6 L @l
addis r3 , r0 , C F G _ I B A T 6 U @h
ori r3 , r3 , C F G _ I B A T 6 U @l
mtspr I B A T 6 L , r4
mtspr I B A T 6 U , r3
isync
/* DBAT 6 */
addis r4 , r0 , C F G _ D B A T 6 L @h
ori r4 , r4 , C F G _ D B A T 6 L @l
addis r3 , r0 , C F G _ D B A T 6 U @h
ori r3 , r3 , C F G _ D B A T 6 U @l
mtspr D B A T 6 L , r4
mtspr D B A T 6 U , r3
isync
/* IBAT 7 */
addis r4 , r0 , C F G _ I B A T 7 L @h
ori r4 , r4 , C F G _ I B A T 7 L @l
@ -508,18 +477,65 @@ setup_bats:
mtspr D B A T 7 U , r3
isync
1 :
addis r3 , 0 , 0 x00 0 0
addis r5 , 0 , 0 x4 / * u p p e r b o u n d o f 0 x00 0 4 0 0 0 0 f o r 7 4 0 0 / 7 5 0 * /
sync
blr
/ *
* early_bats :
*
* Set u p b a t s n e e d e d e a r l y o n - t h i s i s u s u a l l y t h e B A T f o r t h e
* stack- i n - c a c h e a n d t h e F l a s h
* /
.globl early_bats
early_bats :
/* IBAT 5 */
lis r4 , C F G _ I B A T 5 L @h
ori r4 , r4 , C F G _ I B A T 5 L @l
lis r3 , C F G _ I B A T 5 U @h
ori r3 , r3 , C F G _ I B A T 5 U @l
mtspr I B A T 5 L , r4
mtspr I B A T 5 U , r3
isync
/* DBAT 5 */
lis r4 , C F G _ D B A T 5 L @h
ori r4 , r4 , C F G _ D B A T 5 L @l
lis r3 , C F G _ D B A T 5 U @h
ori r3 , r3 , C F G _ D B A T 5 U @l
mtspr D B A T 5 L , r4
mtspr D B A T 5 U , r3
isync
/* IBAT 6 */
lis r4 , C F G _ I B A T 6 L @h
ori r4 , r4 , C F G _ I B A T 6 L @l
lis r3 , C F G _ I B A T 6 U @h
ori r3 , r3 , C F G _ I B A T 6 U @l
mtspr I B A T 6 L , r4
mtspr I B A T 6 U , r3
isync
/* DBAT 6 */
lis r4 , C F G _ D B A T 6 L @h
ori r4 , r4 , C F G _ D B A T 6 L @l
lis r3 , C F G _ D B A T 6 U @h
ori r3 , r3 , C F G _ D B A T 6 U @l
mtspr D B A T 6 L , r4
mtspr D B A T 6 U , r3
isync
blr
.globl clear_tlbs
clear_tlbs :
addis r3 , 0 , 0 x00 0 0
addis r5 , 0 , 0 x4
isync
tlblp :
tlbie r3
tlbie r3
sync
addi r3 , r3 , 0 x10 0 0
cmp 0 , 0 , r3 , r5
addi r3 , r3 , 0 x10 0 0
cmp 0 , 0 , r3 , r5
blt t l b l p
blr
.globl enable_addr_trans