* Add i.MX7D SABRESD target board support with enabled modules: UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX. Build target: mx7dsabresd_config Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>master
Adrian Alonso
9 years ago
committed by
Stefano Babic
parent
cd562c8d07
commit
1a8150d4b1
@ -0,0 +1,27 @@ |
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if ARCH_MX7 |
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config MX7 |
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bool |
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default y |
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config MX7D |
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bool |
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choice |
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prompt "MX7 board select" |
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optional |
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config TARGET_MX7DSABRESD |
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bool "mx7dsabresd" |
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select CPU_V7 |
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select DM |
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select DM_THERMAL |
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endchoice |
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config SYS_SOC |
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default "mx7" |
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source "board/freescale/mx7dsabresd/Kconfig" |
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endif |
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@ -0,0 +1,15 @@ |
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if TARGET_MX7DSABRESD |
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config SYS_BOARD |
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default "mx7dsabresd" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_SOC |
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default "mx7" |
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config SYS_CONFIG_NAME |
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default "mx7dsabresd" |
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endif |
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@ -0,0 +1,6 @@ |
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MX7DSABRESD BOARD |
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M: Adrian Alonso <aalonso@freescale.com> |
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S: Maintained |
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F: board/freescale/mx7dsabresd |
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F: include/configs/mx7dsabresd.h |
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F: configs/mx7dsabresd_defconfig |
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@ -0,0 +1,6 @@ |
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# (C) Copyright 2015 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx7dsabresd.o
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@ -0,0 +1,94 @@ |
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/* |
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer docs/README.imxmage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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#define __ASSEMBLY__ |
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#include <config.h> |
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/* image version */ |
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IMAGE_VERSION 2 |
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/* |
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* Boot Device : sd |
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*/ |
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BOOT_FROM sd |
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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DATA 4 0x30340004 0x4F400005 |
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DATA 4 0x30391000 0x00000002 |
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DATA 4 0x307a0000 0x01040001 |
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DATA 4 0x307a01a0 0x80400003 |
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DATA 4 0x307a01a4 0x00100020 |
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DATA 4 0x307a01a8 0x80100004 |
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DATA 4 0x307a0064 0x00400046 |
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DATA 4 0x307a0490 0x00000001 |
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DATA 4 0x307a00d0 0x00020083 |
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DATA 4 0x307a00d4 0x00690000 |
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DATA 4 0x307a00dc 0x09300004 |
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DATA 4 0x307a00e0 0x04080000 |
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DATA 4 0x307a00e4 0x00100004 |
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DATA 4 0x307a00f4 0x0000033f |
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DATA 4 0x307a0100 0x09081109 |
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DATA 4 0x307a0104 0x0007020d |
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DATA 4 0x307a0108 0x03040407 |
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DATA 4 0x307a010c 0x00002006 |
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DATA 4 0x307a0110 0x04020205 |
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DATA 4 0x307a0114 0x03030202 |
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DATA 4 0x307a0120 0x00000803 |
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DATA 4 0x307a0180 0x00800020 |
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DATA 4 0x307a0184 0x02000100 |
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DATA 4 0x307a0190 0x02098204 |
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DATA 4 0x307a0194 0x00030303 |
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DATA 4 0x307a0200 0x00000016 |
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DATA 4 0x307a0204 0x00171717 |
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DATA 4 0x307a0214 0x04040404 |
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DATA 4 0x307a0218 0x0f040404 |
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DATA 4 0x307a0240 0x06000604 |
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DATA 4 0x307a0244 0x00000001 |
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DATA 4 0x30391000 0x00000000 |
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DATA 4 0x30790000 0x17420f40 |
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DATA 4 0x30790004 0x10210100 |
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DATA 4 0x30790010 0x00060807 |
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DATA 4 0x307900b0 0x1010007e |
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DATA 4 0x3079009c 0x00000d6e |
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DATA 4 0x30790020 0x08080808 |
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DATA 4 0x30790030 0x08080808 |
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DATA 4 0x30790050 0x01000010 |
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DATA 4 0x30790050 0x00000010 |
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DATA 4 0x307900c0 0x0e407304 |
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DATA 4 0x307900c0 0x0e447304 |
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DATA 4 0x307900c0 0x0e447306 |
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CHECK_BITS_SET 4 0x307900c4 0x1 |
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DATA 4 0x307900c0 0x0e447304 |
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DATA 4 0x307900c0 0x0e407304 |
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DATA 4 0x30384130 0x00000000 |
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DATA 4 0x30340020 0x00000178 |
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DATA 4 0x30384130 0x00000002 |
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DATA 4 0x30790018 0x0000000f |
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CHECK_BITS_SET 4 0x307a0004 0x1 |
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@ -0,0 +1,555 @@ |
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/mx7-pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/boot_mode.h> |
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#include <asm/io.h> |
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#include <linux/sizes.h> |
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#include <common.h> |
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#include <fsl_esdhc.h> |
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#include <mmc.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <power/pmic.h> |
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#include <power/pfuze3000_pmic.h> |
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#include "../common/pfuze.h" |
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#include <i2c.h> |
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#include <asm/imx-common/mxc_i2c.h> |
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#include <asm/arch/crm_regs.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ |
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) |
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ |
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) |
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) |
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) |
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) |
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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ |
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) |
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#ifdef CONFIG_SYS_I2C_MXC |
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
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/* I2C1 for PMIC */ |
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struct i2c_pads_info i2c_pad_info1 = { |
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.scl = { |
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.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, |
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.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, |
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.gp = IMX_GPIO_NR(4, 8), |
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}, |
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.sda = { |
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.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, |
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.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, |
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.gp = IMX_GPIO_NR(4, 9), |
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}, |
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}; |
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#endif |
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int dram_init(void) |
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{ |
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gd->ram_size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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static iomux_v3_cfg_t const wdog_pads[] = { |
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const uart1_pads[] = { |
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const usdhc1_pads[] = { |
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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { |
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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#define IOX_SDI IMX_GPIO_NR(1, 9) |
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#define IOX_STCP IMX_GPIO_NR(1, 12) |
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#define IOX_SHCP IMX_GPIO_NR(1, 13) |
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static iomux_v3_cfg_t const iox_pads[] = { |
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/* IOX_SDI */ |
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MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* IOX_STCP */ |
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MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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/* IOX_SHCP */ |
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MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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/*
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* PCIE_DIS_B --> Q0 |
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* PCIE_RST_B --> Q1 |
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* HDMI_RST_B --> Q2 |
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* PERI_RST_B --> Q3 |
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* SENSOR_RST_B --> Q4 |
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* ENET_RST_B --> Q5 |
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* PERI_3V3_EN --> Q6 |
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* LCD_PWR_EN --> Q7 |
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*/ |
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enum qn { |
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PCIE_DIS_B, |
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PCIE_RST_B, |
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HDMI_RST_B, |
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PERI_RST_B, |
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SENSOR_RST_B, |
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ENET_RST_B, |
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PERI_3V3_EN, |
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LCD_PWR_EN, |
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}; |
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enum qn_func { |
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qn_reset, |
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qn_enable, |
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qn_disable, |
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}; |
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enum qn_level { |
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qn_low = 0, |
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qn_high = 1, |
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}; |
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static enum qn_level seq[3][2] = { |
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{0, 1}, {1, 1}, {0, 0} |
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}; |
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static enum qn_func qn_output[8] = { |
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qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, |
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qn_enable |
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}; |
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void iox74lv_init(void) |
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{ |
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int i; |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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}; |
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void iox74lv_set(int index) |
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{ |
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int i; |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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if (i == index) |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); |
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else |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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}; |
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#ifdef CONFIG_FEC_MXC |
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static iomux_v3_cfg_t const fec1_pads[] = { |
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), |
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MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), |
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}; |
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static void setup_iomux_fec(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); |
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} |
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#endif |
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|
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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} |
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|
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#ifdef CONFIG_FSL_ESDHC |
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|
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#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) |
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#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) |
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#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) |
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|
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static struct fsl_esdhc_cfg usdhc_cfg[3] = { |
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{USDHC1_BASE_ADDR, 0, 4}, |
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{USDHC3_BASE_ADDR}, |
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}; |
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|
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static int mmc_get_env_devno(void) |
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{ |
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struct bootrom_sw_info **p = |
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR; |
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|
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u8 boot_type = (*p)->boot_dev_type; |
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u8 dev_no = (*p)->boot_dev_instance; |
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|
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/* If not boot from sd/mmc, use default value */ |
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if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) |
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return CONFIG_SYS_MMC_ENV_DEV; |
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|
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if (dev_no == 2) |
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dev_no--; |
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|
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return dev_no; |
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} |
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|
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static int mmc_map_to_kernel_blk(int dev_no) |
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{ |
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if (dev_no == 1) |
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dev_no++; |
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|
||||
return dev_no; |
||||
} |
||||
|
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
int ret = 0; |
||||
|
||||
switch (cfg->esdhc_base) { |
||||
case USDHC1_BASE_ADDR: |
||||
ret = !gpio_get_value(USDHC1_CD_GPIO); |
||||
break; |
||||
case USDHC3_BASE_ADDR: |
||||
ret = 1; /* Assume uSDHC3 emmc is always present */ |
||||
break; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int i, ret; |
||||
/*
|
||||
* According to the board_mmc_init() the following map is done: |
||||
* (U-boot device node) (Physical Port) |
||||
* mmc0 USDHC1 |
||||
* mmc2 USDHC3 (eMMC) |
||||
*/ |
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
||||
switch (i) { |
||||
case 0: |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
||||
gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); |
||||
gpio_direction_input(USDHC1_CD_GPIO); |
||||
gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); |
||||
gpio_direction_output(USDHC1_PWR_GPIO, 0); |
||||
udelay(500); |
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1); |
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
||||
break; |
||||
case 1: |
||||
imx_iomux_v3_setup_multiple_pads( |
||||
usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); |
||||
gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); |
||||
gpio_direction_output(USDHC3_PWR_GPIO, 0); |
||||
udelay(500); |
||||
gpio_direction_output(USDHC3_PWR_GPIO, 1); |
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
||||
break; |
||||
default: |
||||
printf("Warning: you configured more USDHC controllers" |
||||
"(%d) than supported by the board\n", i + 1); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int check_mmc_autodetect(void) |
||||
{ |
||||
char *autodetect_str = getenv("mmcautodetect"); |
||||
|
||||
if ((autodetect_str != NULL) && |
||||
(strcmp(autodetect_str, "yes") == 0)) { |
||||
return 1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void mmc_late_init(void) |
||||
{ |
||||
char cmd[32]; |
||||
char mmcblk[32]; |
||||
u32 dev_no = mmc_get_env_devno(); |
||||
|
||||
if (!check_mmc_autodetect()) |
||||
return; |
||||
|
||||
setenv_ulong("mmcdev", dev_no); |
||||
|
||||
/* Set mmcblk env */ |
||||
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", |
||||
mmc_map_to_kernel_blk(dev_no)); |
||||
setenv("mmcroot", mmcblk); |
||||
|
||||
sprintf(cmd, "mmc dev %d", dev_no); |
||||
run_command(cmd, 0); |
||||
} |
||||
|
||||
#endif |
||||
|
||||
#ifdef CONFIG_FEC_MXC |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int ret; |
||||
|
||||
setup_iomux_fec(); |
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0, |
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); |
||||
if (ret) |
||||
printf("FEC1 MXC: %s:failed\n", __func__); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int setup_fec(void) |
||||
{ |
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs |
||||
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; |
||||
|
||||
/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ |
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], |
||||
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | |
||||
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); |
||||
|
||||
return set_clk_enet(ENET_125MHz); |
||||
} |
||||
|
||||
|
||||
int board_phy_config(struct phy_device *phydev) |
||||
{ |
||||
/* enable rgmii rxc skew and phy mode select to RGMII copper */ |
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); |
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); |
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); |
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); |
||||
|
||||
if (phydev->drv->config) |
||||
phydev->drv->config(phydev); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_iomux_uart(); |
||||
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); |
||||
|
||||
iox74lv_init(); |
||||
|
||||
#ifdef CONFIG_FEC_MXC |
||||
setup_fec(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
static const struct boot_mode board_boot_modes[] = { |
||||
/* 4 bit bus width */ |
||||
{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, |
||||
{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, |
||||
{NULL, 0}, |
||||
}; |
||||
#endif |
||||
|
||||
#ifdef CONFIG_POWER |
||||
#define I2C_PMIC 0 |
||||
int power_init_board(void) |
||||
{ |
||||
struct pmic *p; |
||||
int ret; |
||||
unsigned int reg, rev_id; |
||||
|
||||
ret = power_pfuze3000_init(I2C_PMIC); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
p = pmic_get("PFUZE3000"); |
||||
ret = pmic_probe(p); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
pmic_reg_read(p, PFUZE3000_DEVICEID, ®); |
||||
pmic_reg_read(p, PFUZE3000_REVID, &rev_id); |
||||
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); |
||||
|
||||
/* disable Low Power Mode during standby mode */ |
||||
pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); |
||||
reg |= 0x1; |
||||
pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
#ifdef CONFIG_CMD_BMODE |
||||
add_board_boot_modes(board_boot_modes); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC |
||||
mmc_late_init(); |
||||
#endif |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
||||
|
||||
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
return get_cpu_rev(); |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: i.MX7D SABRESD\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX7 |
||||
iomux_v3_cfg_t const usb_otg1_pads[] = { |
||||
MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const usb_otg2_pads[] = { |
||||
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
int board_ehci_hcd_init(int port) |
||||
{ |
||||
switch (port) { |
||||
case 0: |
||||
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, |
||||
ARRAY_SIZE(usb_otg1_pads)); |
||||
break; |
||||
case 1: |
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, |
||||
ARRAY_SIZE(usb_otg2_pads)); |
||||
break; |
||||
default: |
||||
printf("MXC USB port %d not yet supported\n", port); |
||||
return -EINVAL; |
||||
} |
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,14 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D" |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX7=y |
||||
CONFIG_TARGET_MX7DSABRESD=y |
||||
CONFIG_SYS_MALLOC_F=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x400 |
||||
CONFIG_CMD_NET=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_DHCP=y |
||||
# CONFIG_CMD_BOOTD is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
@ -0,0 +1,95 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for the Freescale i.MX7. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __MX7_COMMON_H |
||||
#define __MX7_COMMON_H |
||||
|
||||
#include <linux/sizes.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/imx-common/gpio.h> |
||||
|
||||
#ifndef CONFIG_MX7 |
||||
#define CONFIG_MX7 |
||||
#endif |
||||
|
||||
/* Timer settings */ |
||||
#define CONFIG_MXC_GPT_HCLK |
||||
#define CONFIG_SYSCOUNTER_TIMER |
||||
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ |
||||
|
||||
/* Enable iomux-lpsr support */ |
||||
#define CONFIG_IOMUX_LPSR |
||||
#define CONFIG_IMX_FIXED_IVT_OFFSET |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
#define CONFIG_ROM_UNIFIED_SECTIONS |
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
#define CONFIG_LOADADDR 0x80800000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x87800000 |
||||
|
||||
#ifndef CONFIG_BOOTDELAY |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#endif |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Filesystems and image support */ |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_EXT4 |
||||
#define CONFIG_CMD_EXT4_WRITE |
||||
#define CONFIG_CMD_FAT |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 512 |
||||
#define CONFIG_SYS_MAXARGS 32 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_CMD_CACHE |
||||
#endif |
||||
|
||||
/* GPIO */ |
||||
#define CONFIG_MXC_GPIO |
||||
#define CONFIG_CMD_GPIO |
||||
|
||||
/* UART */ |
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR |
||||
|
||||
/* MMC */ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_FSL_USDHC |
||||
|
||||
/* Fuses */ |
||||
#define CONFIG_CMD_FUSE |
||||
#define CONFIG_MXC_OCOTP |
||||
|
||||
#endif |
||||
@ -0,0 +1,194 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for the Freescale i.MX7D SABRESD board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __MX7D_SABRESD_CONFIG_H |
||||
#define __MX7D_SABRESD_CONFIG_H |
||||
|
||||
#include "mx7_common.h" |
||||
|
||||
#define CONFIG_DBG_MONITOR |
||||
#define PHYS_SDRAM_SIZE SZ_1G |
||||
|
||||
/* Network */ |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_MII |
||||
#define CONFIG_FEC_XCV_TYPE RGMII |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
#define CONFIG_FEC_MXC_PHYADDR 0 |
||||
|
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_BROADCOM |
||||
#define CONFIG_FEC_DMA_MINALIGN 64 |
||||
/* ENET1 */ |
||||
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR |
||||
|
||||
/* MMC Config*/ |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
|
||||
/* PMIC */ |
||||
#define CONFIG_POWER |
||||
#define CONFIG_POWER_I2C |
||||
#define CONFIG_POWER_PFUZE3000 |
||||
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 |
||||
|
||||
#undef CONFIG_BOOTM_NETBSD |
||||
#undef CONFIG_BOOTM_PLAN9 |
||||
#undef CONFIG_BOOTM_RTEMS |
||||
|
||||
#undef CONFIG_CMD_EXPORTENV |
||||
#undef CONFIG_CMD_IMPORTENV |
||||
|
||||
/* I2C configs */ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_MXC_I2C1 |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ |
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 |
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \ |
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
"clk_ignore_unused "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx7d-sdb.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi" |
||||
|
||||
#define CONFIG_CMD_MEMTEST |
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
#define CONFIG_STACKSIZE SZ_128K |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_SIZE SZ_8K |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K) |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2 |
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ |
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ |
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ |
||||
|
||||
#define CONFIG_CMD_BMODE |
||||
|
||||
/* USB Configs */ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_MX7 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_USB_HOST_ETHER |
||||
#define CONFIG_USB_ETHER_ASIX |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
|
||||
#define CONFIG_IMX_THERMAL |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue