The IGEP module is a low-power, high performance production-ready system-on-module (SOM) based on TI's OMAP3 family.The IGEP module solution based upon TI OMAP3 provides a low-power/low-cost platform for a variety of consumer/industrial/medical devices. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>master
Enric Balletbo i Serra
14 years ago
committed by
Wolfgang Denk
parent
8a3f6bb6fb
commit
1a832dc4f8
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := igep0030.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,34 @@ |
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#
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# (C) Copyright 2009
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# ISEE 2007 SL, <www.iseebcn.com>
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#
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# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# Physical Address:
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# 8000'0000 (bank0)
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# A000/0000 (bank1)
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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# For use with external or internal boots.
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TEXT_BASE = 0x80008000
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@ -0,0 +1,71 @@ |
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/*
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* (C) Copyright 2010 |
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* ISEE 2007 SL, <www.iseebcn.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <twl4030.h> |
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#include <asm/io.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/mux.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/mach-types.h> |
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#include "igep0030.h" |
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/*
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* Routine: board_init |
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* Description: Early hardware init. |
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*/ |
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int board_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
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/* board id for Linux */ |
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gd->bd->bi_arch_number = MACH_TYPE_IGEP0030; |
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/* boot param addr */ |
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
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return 0; |
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} |
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/*
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* Routine: misc_init_r |
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* Description: Configure board specific parts |
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*/ |
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int misc_init_r(void) |
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{ |
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twl4030_power_init(); |
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dieid_num_r(); |
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return 0; |
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} |
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/*
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* Routine: set_muxconf_regs |
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* Description: Setting up the configuration Mux registers specific to the |
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* hardware. Many pins need to be moved from protect to primary |
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* mode. |
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*/ |
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void set_muxconf_regs(void) |
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{ |
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MUX_DEFAULT(); |
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} |
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@ -0,0 +1,147 @@ |
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/*
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* (C) Copyright 2010 |
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* ISEE 2007 SL, <www.iseebcn.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _IGEP0030_H_ |
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#define _IGEP0030_H_ |
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const omap3_sysinfo sysinfo = { |
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DDR_STACKED, |
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"OMAP3 IGEP module", |
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"ONENAND", |
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}; |
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/*
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* IEN - Input Enable |
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* IDIS - Input Disable |
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* PTD - Pull type Down |
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* PTU - Pull type Up |
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* DIS - Pull type selection is inactive |
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* EN - Pull type selection is active |
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* M0 - Mode 0 |
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* The commented string gives the final mux configuration for that pin |
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*/ |
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#define MUX_DEFAULT()\ |
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
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MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
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MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
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MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
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MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
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MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
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MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
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MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
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MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
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MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
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MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
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MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
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MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
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MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
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MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
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MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
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MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
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MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
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MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
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MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
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MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
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MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
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MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
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MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
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MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
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MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
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MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
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MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
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MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
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MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
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MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
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MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
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MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
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MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
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MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
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MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
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MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
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MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
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MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
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MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
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MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
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MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
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MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
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MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
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MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
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MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
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MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
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MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
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MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
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MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
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MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
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MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
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MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ |
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#endif |
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@ -0,0 +1,215 @@ |
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/*
|
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* (C) Copyright 2010 |
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* ISEE 2007 SL, <www.iseebcn.com> |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
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* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/sizes.h> |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ |
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#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */ |
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#define CONFIG_OMAP3430 1 /* which is in a 3430 */ |
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#define CONFIG_OMAP3_IGEP0030 1 /* working with IGEP0030 */ |
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#define CONFIG_SDRC /* The chip has SDRC controller */ |
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#include <asm/arch/cpu.h> |
||||
#include <asm/arch/omap3.h> |
||||
|
||||
/*
|
||||
* Display CPU and Board information |
||||
*/ |
||||
#define CONFIG_DISPLAY_CPUINFO 1 |
||||
#define CONFIG_DISPLAY_BOARDINFO 1 |
||||
|
||||
/* Clock Defines */ |
||||
#define V_OSCK 26000000 /* Clock output from T2 */ |
||||
#define V_SCLK (V_OSCK >> 1) |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
#define CONFIG_REVISION_TAG 1 |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
|
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
||||
|
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
||||
|
||||
/* select serial console configuration */ |
||||
#define CONFIG_CONS_INDEX 3 |
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
||||
#define CONFIG_SERIAL3 3 |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} |
||||
#define CONFIG_MMC 1 |
||||
#define CONFIG_OMAP3_MMC 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
/* DDR */ |
||||
#define CONFIG_OMAP3_NUMONYX_DDR 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_MUSB_UDC 1 |
||||
#define CONFIG_USB_OMAP3 1 |
||||
#define CONFIG_TWL4030_USB 1 |
||||
|
||||
/* USB device configuration */ |
||||
#define CONFIG_USB_DEVICE 1 |
||||
#define CONFIG_USB_TTY 1 |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
||||
|
||||
/* Change these to suit your needs */ |
||||
#define CONFIG_USBD_VENDORID 0x0451 |
||||
#define CONFIG_USBD_PRODUCTID 0x5678 |
||||
#define CONFIG_USBD_MANUFACTURER "Texas Instruments" |
||||
#define CONFIG_USBD_PRODUCT_NAME "IGEP" |
||||
|
||||
/* commands to include */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */ |
||||
#define CONFIG_CMD_FAT /* FAT support */ |
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */ |
||||
#define CONFIG_CMD_MMC /* MMC support */ |
||||
#define CONFIG_CMD_ONENAND /* ONENAND support */ |
||||
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
||||
#define CONFIG_MTD_DEVICE |
||||
|
||||
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
||||
#undef CONFIG_CMD_IMLS /* List all found images */ |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_I2C_SLAVE 1 |
||||
#define CONFIG_SYS_I2C_BUS 0 |
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1 |
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1 |
||||
|
||||
/*
|
||||
* TWL4030 |
||||
*/ |
||||
#define CONFIG_TWL4030_POWER 1 |
||||
|
||||
/* Environment information */ |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0" |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"usbtty=cdc_acm\0" |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_SYS_PROMPT "U-Boot # " |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ |
||||
/* works on */ |
||||
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ |
||||
0x01F00000) /* 31MB */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
||||
/* load address */ |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) |
||||
|
||||
/*
|
||||
* OMAP3 has 12 GP timers, they can be driven by the system clock |
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
||||
* This rate is divided by a local divisor. |
||||
*/ |
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
* |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
||||
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ |
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
||||
|
||||
/* SDRAM Bank Allocation method */ |
||||
#define SDRC_R_B_C 1 |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ |
||||
|
||||
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
||||
|
||||
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_ONENAND 1 |
||||
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ |
||||
#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes for initial data */ |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue