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@ -10,7 +10,6 @@ |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/boot_mode.h> |
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#include <asm/io.h> |
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#include <linux/sizes.h> |
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#include <common.h> |
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@ -24,6 +23,7 @@ |
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#include <i2c.h> |
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#include <asm/imx-common/mxc_i2c.h> |
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#include <asm/arch/crm_regs.h> |
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#include <usb/ehci-fsl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR; |
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#ifdef CONFIG_SYS_I2C_MXC |
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
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/* I2C1 for PMIC */ |
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struct i2c_pads_info i2c_pad_info1 = { |
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static struct i2c_pads_info i2c_pad_info1 = { |
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.scl = { |
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.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, |
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.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, |
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@ -156,7 +156,7 @@ static enum qn_func qn_output[8] = { |
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qn_enable |
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}; |
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void iox74lv_init(void) |
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static void iox74lv_init(void) |
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{ |
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int i; |
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@ -190,44 +190,6 @@ void iox74lv_init(void) |
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gpio_direction_output(IOX_STCP, 1); |
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}; |
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void iox74lv_set(int index) |
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{ |
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int i; |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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if (i == index) |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); |
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else |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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for (i = 7; i >= 0; i--) { |
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gpio_direction_output(IOX_SHCP, 0); |
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); |
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udelay(500); |
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gpio_direction_output(IOX_SHCP, 1); |
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udelay(500); |
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} |
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gpio_direction_output(IOX_STCP, 0); |
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udelay(500); |
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/*
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* shift register will be output to pins |
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*/ |
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gpio_direction_output(IOX_STCP, 1); |
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}; |
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#ifdef CONFIG_FEC_MXC |
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static iomux_v3_cfg_t const fec1_pads[] = { |
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
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@ -458,15 +420,6 @@ int board_init(void) |
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return 0; |
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} |
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#ifdef CONFIG_CMD_BMODE |
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static const struct boot_mode board_boot_modes[] = { |
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/* 4 bit bus width */ |
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{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, |
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{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, |
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{NULL, 0}, |
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}; |
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#endif |
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#ifdef CONFIG_POWER |
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#define I2C_PMIC 0 |
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int power_init_board(void) |
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@ -499,9 +452,7 @@ int power_init_board(void) |
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int board_late_init(void) |
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{ |
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#ifdef CONFIG_CMD_BMODE |
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add_board_boot_modes(board_boot_modes); |
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#endif |
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
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#ifdef CONFIG_ENV_IS_IN_MMC |
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mmc_late_init(); |
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@ -509,14 +460,15 @@ int board_late_init(void) |
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
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set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); |
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set_wdog_reset(wdog); |
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return 0; |
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} |
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/*
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* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), |
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* since we use PMIC_PWRON to reset the board. |
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*/ |
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clrsetbits_le16(&wdog->wcr, 0, 0x10); |
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u32 get_board_rev(void) |
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{ |
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return get_cpu_rev(); |
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return 0; |
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} |
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int checkboard(void) |
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@ -527,11 +479,11 @@ int checkboard(void) |
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} |
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#ifdef CONFIG_USB_EHCI_MX7 |
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iomux_v3_cfg_t const usb_otg1_pads[] = { |
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static iomux_v3_cfg_t const usb_otg1_pads[] = { |
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MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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iomux_v3_cfg_t const usb_otg2_pads[] = { |
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static iomux_v3_cfg_t const usb_otg2_pads[] = { |
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MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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Tom Rini
9 years ago