arm: fsl-layerscape: Move QSGMII wriop_init to SoC file

MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

@@ -23,6 +23,11 @@ int xfi_dpmac[XFI8 + 1];
 int sgmii_dpmac[SGMII16 + 1];
 #endif
 
+__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+	return;
+}
+
 int is_serdes_configured(enum srds_prtcl device)
 {
 	int ret = 0;
@@ -106,28 +111,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 #ifdef CONFIG_FSL_MC_ENET
 			switch (lane_prtcl) {
 			case QSGMII_A:
-				wriop_init_dpmac(sd, 5, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 6, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 7, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 8, (int)lane_prtcl);
-				break;
 			case QSGMII_B:
-				wriop_init_dpmac(sd, 1, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 2, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 3, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 4, (int)lane_prtcl);
-				break;
 			case QSGMII_C:
-				wriop_init_dpmac(sd, 13, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 14, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 15, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 16, (int)lane_prtcl);
-				break;
 			case QSGMII_D:
-				wriop_init_dpmac(sd, 9, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 10, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 11, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 12, (int)lane_prtcl);
+				wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
 				break;
 			default:
 				if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)

arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h

@@ -48,10 +48,10 @@ enum srds_prtcl {
 	SGMII14,
 	SGMII15,
 	SGMII16,
-	QSGMII_A, /* A indicates MACs 1-4 */
-	QSGMII_B, /* B indicates MACs 5-8 */
-	QSGMII_C, /* C indicates MACs 9-12 */
-	QSGMII_D, /* D indicates MACs 12-16 */
+	QSGMII_A,
+	QSGMII_B,
+	QSGMII_C,
+	QSGMII_D,
 	SERDES_PRCTL_COUNT
 };
 

drivers/net/ldpaa_eth/ls2080a.c

@@ -79,3 +79,33 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
 
 	return PHY_INTERFACE_MODE_NONE;
 }
+
+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+	switch (lane_prtcl) {
+	case QSGMII_A:
+		wriop_init_dpmac(sd, 5, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 6, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 7, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 8, (int)lane_prtcl);
+		break;
+	case QSGMII_B:
+		wriop_init_dpmac(sd, 1, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 2, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 3, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 4, (int)lane_prtcl);
+		break;
+	case QSGMII_C:
+		wriop_init_dpmac(sd, 13, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 14, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 15, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 16, (int)lane_prtcl);
+		break;
+	case QSGMII_D:
+		wriop_init_dpmac(sd, 9, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 10, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 11, (int)lane_prtcl);
+		wriop_init_dpmac(sd, 12, (int)lane_prtcl);
+		break;
+	}
+}

include/fsl-mc/ldpaa_wriop.h

@@ -68,4 +68,5 @@ phy_interface_t wriop_get_enet_if(int);
 void wriop_dpmac_disable(int);
 void wriop_dpmac_enable(int);
 phy_interface_t wriop_dpmac_enet_if(int, int);
+void wriop_init_dpmac_qsgmii(int, int);
 #endif	/* __LDPAA_WRIOP_H */