This patch adds SPI driver for EXYNOS. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: jy0922.shim@samsung.com Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>master
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/*
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* (C) Copyright 2012 SAMSUNG Electronics |
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* Padmavathi Venna <padma.v@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_ |
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#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_ |
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#ifndef __ASSEMBLY__ |
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/* SPI peripheral register map; padded to 64KB */ |
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struct exynos_spi { |
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unsigned int ch_cfg; /* 0x00 */ |
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unsigned char reserved0[4]; |
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unsigned int mode_cfg; /* 0x08 */ |
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unsigned int cs_reg; /* 0x0c */ |
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unsigned char reserved1[4]; |
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unsigned int spi_sts; /* 0x14 */ |
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unsigned int tx_data; /* 0x18 */ |
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unsigned int rx_data; /* 0x1c */ |
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unsigned int pkt_cnt; /* 0x20 */ |
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unsigned char reserved2[4]; |
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unsigned char reserved3[4]; |
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unsigned int fb_clk; /* 0x2c */ |
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unsigned char padding[0xffd0]; |
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}; |
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#define EXYNOS_SPI_MAX_FREQ 50000000 |
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#define SPI_TIMEOUT_MS 10 |
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/* SPI_CHCFG */ |
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#define SPI_CH_HS_EN (1 << 6) |
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#define SPI_CH_RST (1 << 5) |
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#define SPI_SLAVE_MODE (1 << 4) |
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#define SPI_CH_CPOL_L (1 << 3) |
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#define SPI_CH_CPHA_B (1 << 2) |
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#define SPI_RX_CH_ON (1 << 1) |
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#define SPI_TX_CH_ON (1 << 0) |
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/* SPI_MODECFG */ |
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#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29) |
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#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17) |
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/* SPI_CSREG */ |
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#define SPI_SLAVE_SIG_INACT (1 << 0) |
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/* SPI_STS */ |
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#define SPI_ST_TX_DONE (1 << 25) |
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#define SPI_FIFO_LVL_MASK 0x1ff |
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#define SPI_TX_LVL_OFFSET 6 |
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#define SPI_RX_LVL_OFFSET 15 |
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/* Feedback Delay */ |
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#define SPI_CLK_BYPASS (0 << 0) |
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#define SPI_FB_DELAY_90 (1 << 0) |
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#define SPI_FB_DELAY_180 (2 << 0) |
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#define SPI_FB_DELAY_270 (3 << 0) |
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/* Packet Count */ |
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#define SPI_PACKET_CNT_EN (1 << 16) |
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#endif /* __ASSEMBLY__ */ |
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#endif |
@ -0,0 +1,367 @@ |
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/*
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* (C) Copyright 2012 SAMSUNG Electronics |
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* Padmavathi Venna <padma.v@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <spi.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/pinmux.h> |
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#include <asm/arch-exynos/spi.h> |
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#include <asm/io.h> |
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/* Information about each SPI controller */ |
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struct spi_bus { |
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enum periph_id periph_id; |
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s32 frequency; /* Default clock frequency, -1 for none */ |
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struct exynos_spi *regs; |
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int inited; /* 1 if this bus is ready for use */ |
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}; |
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/* A list of spi buses that we know about */ |
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static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS]; |
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struct exynos_spi_slave { |
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struct spi_slave slave; |
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struct exynos_spi *regs; |
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unsigned int freq; /* Default frequency */ |
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unsigned int mode; |
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enum periph_id periph_id; /* Peripheral ID for this device */ |
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unsigned int fifo_size; |
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}; |
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static struct spi_bus *spi_get_bus(unsigned dev_index) |
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{ |
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if (dev_index < EXYNOS5_SPI_NUM_CONTROLLERS) |
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return &spi_bus[dev_index]; |
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debug("%s: invalid bus %d", __func__, dev_index); |
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return NULL; |
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} |
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static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave) |
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{ |
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return container_of(slave, struct exynos_spi_slave, slave); |
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} |
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/**
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* Setup the driver private data |
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* |
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* @param bus ID of the bus that the slave is attached to |
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* @param cs ID of the chip select connected to the slave |
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* @param max_hz Required spi frequency |
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* @param mode Required spi mode (clk polarity, clk phase and |
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* master or slave) |
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* @return new device or NULL |
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*/ |
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struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs, |
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unsigned int max_hz, unsigned int mode) |
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{ |
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struct exynos_spi_slave *spi_slave; |
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struct spi_bus *bus; |
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if (!spi_cs_is_valid(busnum, cs)) { |
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debug("%s: Invalid bus/chip select %d, %d\n", __func__, |
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busnum, cs); |
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return NULL; |
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} |
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spi_slave = malloc(sizeof(*spi_slave)); |
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if (!spi_slave) { |
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debug("%s: Could not allocate spi_slave\n", __func__); |
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return NULL; |
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} |
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bus = &spi_bus[busnum]; |
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spi_slave->slave.bus = busnum; |
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spi_slave->slave.cs = cs; |
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spi_slave->regs = bus->regs; |
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spi_slave->mode = mode; |
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spi_slave->periph_id = bus->periph_id; |
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if (bus->periph_id == PERIPH_ID_SPI1 || |
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bus->periph_id == PERIPH_ID_SPI2) |
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spi_slave->fifo_size = 64; |
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else |
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spi_slave->fifo_size = 256; |
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spi_slave->freq = bus->frequency; |
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if (max_hz) |
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spi_slave->freq = min(max_hz, spi_slave->freq); |
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return &spi_slave->slave; |
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} |
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/**
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* Free spi controller |
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* |
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* @param slave Pointer to spi_slave to which controller has to |
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* communicate with |
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*/ |
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void spi_free_slave(struct spi_slave *slave) |
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{ |
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struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); |
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free(spi_slave); |
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} |
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/**
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* Flush spi tx, rx fifos and reset the SPI controller |
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* |
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* @param slave Pointer to spi_slave to which controller has to |
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* communicate with |
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*/ |
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static void spi_flush_fifo(struct spi_slave *slave) |
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{ |
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struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); |
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struct exynos_spi *regs = spi_slave->regs; |
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clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); |
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clrbits_le32(®s->ch_cfg, SPI_CH_RST); |
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setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); |
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} |
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/**
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* Initialize the spi base registers, set the required clock frequency and |
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* initialize the gpios |
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* |
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* @param slave Pointer to spi_slave to which controller has to |
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* communicate with |
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* @return zero on success else a negative value |
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*/ |
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int spi_claim_bus(struct spi_slave *slave) |
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{ |
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struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); |
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struct exynos_spi *regs = spi_slave->regs; |
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u32 reg = 0; |
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int ret; |
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ret = set_spi_clk(spi_slave->periph_id, |
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spi_slave->freq); |
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if (ret < 0) { |
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debug("%s: Failed to setup spi clock\n", __func__); |
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return ret; |
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} |
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exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE); |
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spi_flush_fifo(slave); |
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reg = readl(®s->ch_cfg); |
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reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L); |
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if (spi_slave->mode & SPI_CPHA) |
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reg |= SPI_CH_CPHA_B; |
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if (spi_slave->mode & SPI_CPOL) |
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reg |= SPI_CH_CPOL_L; |
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writel(reg, ®s->ch_cfg); |
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writel(SPI_FB_DELAY_180, ®s->fb_clk); |
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return 0; |
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} |
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/**
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* Reset the spi H/W and flush the tx and rx fifos |
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* |
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* @param slave Pointer to spi_slave to which controller has to |
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* communicate with |
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*/ |
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void spi_release_bus(struct spi_slave *slave) |
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{ |
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spi_flush_fifo(slave); |
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} |
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static void spi_get_fifo_levels(struct exynos_spi *regs, |
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int *rx_lvl, int *tx_lvl) |
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{ |
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uint32_t spi_sts = readl(®s->spi_sts); |
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*rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; |
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*tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; |
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} |
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/**
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* If there's something to transfer, do a software reset and set a |
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* transaction size. |
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* |
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* @param regs SPI peripheral registers |
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* @param count Number of bytes to transfer |
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*/ |
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static void spi_request_bytes(struct exynos_spi *regs, int count) |
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{ |
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assert(count && count < (1 << 16)); |
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setbits_le32(®s->ch_cfg, SPI_CH_RST); |
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clrbits_le32(®s->ch_cfg, SPI_CH_RST); |
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writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt); |
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} |
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static void spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, |
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void **dinp, void const **doutp) |
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{ |
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struct exynos_spi *regs = spi_slave->regs; |
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uchar *rxp = *dinp; |
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const uchar *txp = *doutp; |
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int rx_lvl, tx_lvl; |
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uint out_bytes, in_bytes; |
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out_bytes = in_bytes = todo; |
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/*
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* If there's something to send, do a software reset and set a |
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* transaction size. |
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*/ |
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spi_request_bytes(regs, todo); |
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/*
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* Bytes are transmitted/received in pairs. Wait to receive all the |
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* data because then transmission will be done as well. |
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*/ |
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while (in_bytes) { |
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int temp; |
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/* Keep the fifos full/empty. */ |
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spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); |
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if (tx_lvl < spi_slave->fifo_size && out_bytes) { |
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temp = txp ? *txp++ : 0xff; |
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writel(temp, ®s->tx_data); |
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out_bytes--; |
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} |
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if (rx_lvl > 0 && in_bytes) { |
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temp = readl(®s->rx_data); |
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if (rxp) |
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*rxp++ = temp; |
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in_bytes--; |
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} |
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} |
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*dinp = rxp; |
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*doutp = txp; |
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} |
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/**
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* Transfer and receive data |
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* |
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* @param slave Pointer to spi_slave to which controller has to |
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* communicate with |
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* @param bitlen No of bits to tranfer or receive |
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* @param dout Pointer to transfer buffer |
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* @param din Pointer to receive buffer |
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* @param flags Flags for transfer begin and end |
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* @return zero on success else a negative value |
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*/ |
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
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void *din, unsigned long flags) |
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{ |
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struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); |
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int upto, todo; |
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int bytelen; |
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/* spi core configured to do 8 bit transfers */ |
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if (bitlen % 8) { |
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debug("Non byte aligned SPI transfer.\n"); |
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return -1; |
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} |
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/* Start the transaction, if necessary. */ |
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if ((flags & SPI_XFER_BEGIN)) |
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spi_cs_activate(slave); |
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/* Exynos SPI limits each transfer to 65535 bytes */ |
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bytelen = bitlen / 8; |
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for (upto = 0; upto < bytelen; upto += todo) { |
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todo = min(bytelen - upto, (1 << 16) - 1); |
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spi_rx_tx(spi_slave, todo, &din, &dout); |
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} |
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/* Stop the transaction, if necessary. */ |
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if ((flags & SPI_XFER_END)) |
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spi_cs_deactivate(slave); |
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return 0; |
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} |
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/**
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* Validates the bus and chip select numbers |
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* |
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* @param bus ID of the bus that the slave is attached to |
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* @param cs ID of the chip select connected to the slave |
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* @return one on success else zero |
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*/ |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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return spi_get_bus(bus) && cs == 0; |
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} |
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/**
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* Activate the CS by driving it LOW |
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* |
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* @param slave Pointer to spi_slave to which controller has to |
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* communicate with |
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*/ |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); |
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clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); |
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debug("Activate CS, bus %d\n", spi_slave->slave.bus); |
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} |
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/**
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* Deactivate the CS by driving it HIGH |
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* |
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* @param slave Pointer to spi_slave to which controller has to |
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* communicate with |
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*/ |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); |
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setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); |
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debug("Deactivate CS, bus %d\n", spi_slave->slave.bus); |
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} |
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static inline struct exynos_spi *get_spi_base(int dev_index) |
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{ |
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if (dev_index < 3) |
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return (struct exynos_spi *)samsung_get_base_spi() + dev_index; |
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else |
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return (struct exynos_spi *)samsung_get_base_spi_isp() + |
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(dev_index - 3); |
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} |
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/* Sadly there is no error return from this function */ |
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void spi_init(void) |
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{ |
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int i; |
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struct spi_bus *bus; |
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for (i = 0; i < EXYNOS5_SPI_NUM_CONTROLLERS; i++) { |
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bus = &spi_bus[i]; |
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bus->regs = get_spi_base(i); |
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bus->periph_id = PERIPH_ID_SPI0 + i; |
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/* Although Exynos5 supports upto 50Mhz speed,
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* we are setting it to 10Mhz for safe side |
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*/ |
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bus->frequency = 10000000; |
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bus->inited = 1; |
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} |
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} |
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