MPC8323E based board with 64MB fixed SDRAM, 16MB flash, five 10/100 ethernet ports connected via an ICPlus IP175C switch, one PCI slot, and serial. Features not supported in this patch are SD card interface, 2 USB ports, and the two phone ports. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>master
Kim Phillips
18 years ago
parent
343d91009d
commit
1c274c4e05
@ -0,0 +1,50 @@ |
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#
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# (C) Copyright 2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,28 @@ |
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#
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# (C) Copyright 2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# MPC8323ERDB
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#
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TEXT_BASE = 0xFE000000
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@ -0,0 +1,217 @@ |
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. |
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* |
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* Michael Barkowski <michael.barkowski@freescale.com> |
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* Based on mpc832xmds file by Dave Liu <daveliu@freescale.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <i2c.h> |
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#include <spd.h> |
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#include <miiphy.h> |
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#include <command.h> |
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#include <libfdt.h> |
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#include <libfdt_env.h> |
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#if defined(CONFIG_PCI) |
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#include <pci.h> |
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#endif |
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#if defined(CONFIG_SPD_EEPROM) |
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#include <spd_sdram.h> |
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#else |
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#include <asm/mmu.h> |
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#endif |
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const qe_iop_conf_t qe_iop_conf_tab[] = { |
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/* UCC3 */ |
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{1, 0, 1, 0, 1}, /* TxD0 */ |
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{1, 1, 1, 0, 1}, /* TxD1 */ |
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{1, 2, 1, 0, 1}, /* TxD2 */ |
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{1, 3, 1, 0, 1}, /* TxD3 */ |
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{1, 9, 1, 0, 1}, /* TxER */ |
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{1, 12, 1, 0, 1}, /* TxEN */ |
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{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ |
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{1, 4, 2, 0, 1}, /* RxD0 */ |
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{1, 5, 2, 0, 1}, /* RxD1 */ |
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{1, 6, 2, 0, 1}, /* RxD2 */ |
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{1, 7, 2, 0, 1}, /* RxD3 */ |
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{1, 8, 2, 0, 1}, /* RxER */ |
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{1, 10, 2, 0, 1}, /* RxDV */ |
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{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ |
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{1, 11, 2, 0, 1}, /* COL */ |
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{1, 13, 2, 0, 1}, /* CRS */ |
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/* UCC2 */ |
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{0, 18, 1, 0, 1}, /* TxD0 */ |
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{0, 19, 1, 0, 1}, /* TxD1 */ |
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{0, 20, 1, 0, 1}, /* TxD2 */ |
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{0, 21, 1, 0, 1}, /* TxD3 */ |
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{0, 27, 1, 0, 1}, /* TxER */ |
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{0, 30, 1, 0, 1}, /* TxEN */ |
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{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ |
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{0, 22, 2, 0, 1}, /* RxD0 */ |
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{0, 23, 2, 0, 1}, /* RxD1 */ |
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{0, 24, 2, 0, 1}, /* RxD2 */ |
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{0, 25, 2, 0, 1}, /* RxD3 */ |
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{0, 26, 1, 0, 1}, /* RxER */ |
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{0, 28, 2, 0, 1}, /* Rx_DV */ |
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{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ |
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{0, 29, 2, 0, 1}, /* COL */ |
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{0, 31, 2, 0, 1}, /* CRS */ |
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{3, 4, 3, 0, 2}, /* MDIO */ |
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{3, 5, 1, 0, 2}, /* MDC */ |
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ |
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}; |
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int board_early_init_f(void) |
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{ |
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return 0; |
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} |
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int fixed_sdram(void); |
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long int initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMR; |
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u32 msize = 0; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
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msize = fixed_sdram(); |
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puts("\n DDR RAM: "); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return (msize * 1024 * 1024); |
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} |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMR; |
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u32 msize = 0; |
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u32 ddr_size; |
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u32 ddr_size_log2; |
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msize = CFG_DDR_SIZE; |
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for (ddr_size = msize << 20, ddr_size_log2 = 0; |
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { |
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if (ddr_size & 1) { |
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return -1; |
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} |
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} |
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im->sysconf.ddrlaw[0].ar = |
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
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im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; |
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im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; |
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im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; |
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; |
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; |
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; |
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im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; |
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im->ddr.sdram_mode = CFG_DDR_MODE; |
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im->ddr.sdram_mode2 = CFG_DDR_MODE2; |
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im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
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__asm__ __volatile__ ("sync"); |
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udelay(200); |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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__asm__ __volatile__ ("sync"); |
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return msize; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: Freescale MPC8323ERDB\n"); |
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return 0; |
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} |
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static struct pci_region pci_regions[] = { |
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{ |
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bus_start: CFG_PCI1_MEM_BASE, |
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phys_start: CFG_PCI1_MEM_PHYS, |
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size: CFG_PCI1_MEM_SIZE, |
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
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}, |
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{ |
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bus_start: CFG_PCI1_MMIO_BASE, |
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phys_start: CFG_PCI1_MMIO_PHYS, |
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size: CFG_PCI1_MMIO_SIZE, |
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flags: PCI_REGION_MEM |
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}, |
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{ |
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bus_start: CFG_PCI1_IO_BASE, |
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phys_start: CFG_PCI1_IO_PHYS, |
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size: CFG_PCI1_IO_SIZE, |
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flags: PCI_REGION_IO |
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} |
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}; |
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void pci_init_board(void) |
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{ |
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volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; |
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; |
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw; |
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struct pci_region *reg[] = { pci_regions }; |
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/* Enable all 3 PCI_CLK_OUTPUTs. */ |
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clk->occr |= 0xe0000000; |
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/* Configure PCI Local Access Windows */ |
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pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; |
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; |
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pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; |
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; |
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mpc83xx_pci_init(1, reg, 0); |
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} |
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#if defined(CONFIG_OF_BOARD_SETUP) |
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/*
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* Prototypes of functions that we use. |
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*/ |
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void ft_cpu_setup(void *blob, bd_t *bd); |
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#ifdef CONFIG_PCI |
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void ft_pci_setup(void *blob, bd_t *bd); |
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#endif |
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void |
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ft_board_setup(void *blob, bd_t *bd) |
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{ |
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int nodeoffset; |
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int tmp[2]; |
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nodeoffset = fdt_find_node_by_path(blob, "/memory"); |
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if (nodeoffset >= 0) { |
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tmp[0] = cpu_to_be32(bd->bi_memstart); |
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tmp[1] = cpu_to_be32(bd->bi_memsize); |
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fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); |
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} |
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ft_cpu_setup(blob, bd); |
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#ifdef CONFIG_PCI |
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ft_pci_setup(blob, bd); |
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#endif |
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} |
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#endif /* CONFIG_OF_BOARD_SETUP */ |
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@ -0,0 +1,71 @@ |
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Freescale MPC8323ERDB Board |
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----------------------------------------- |
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1. Memory Map |
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The memory map looks like this: |
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0x0000_0000 0x03ff_ffff DDR 64M |
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0x8000_0000 0x8fff_ffff PCI MEM 256M |
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0x9000_0000 0x9fff_ffff PCI_MMIO 256M |
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0xe000_0000 0xe00f_ffff IMMR 1M |
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0xd000_0000 0xd3ff_ffff PCI IO 64M |
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0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M |
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2. Compilation |
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Assuming you're using BASH (or similar) as your shell: |
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export CROSS_COMPILE=your-cross-compiler-prefix- |
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make distclean |
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make MPC8323ERDB_config |
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make |
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3. Downloading and Flashing Images |
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3.1 Reflash U-boot Image using U-boot |
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N.b, have an alternate means of programming |
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the flash available if the new u-boot doesn't boot. |
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First try a: |
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tftpboot $loadaddr $uboot |
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to make sure that the TFTP load will succeed before |
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an erase goes ahead and wipes out your current firmware. |
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Then do a: |
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run tftpflash |
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which is a shorter version of the manual sequence: |
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tftp $loadaddr u-boot.bin |
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protect off fe000000 +$filesize |
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erase fe000000 +$filesize |
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cp.b $loadaddr fe000000 $filesize |
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To keep your old u-boot's environment variables, do a: |
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saveenv |
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prior to resetting the board. |
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3.2 Downloading and Booting Linux Kernel |
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Ensure that all networking-related environment variables are set |
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properly (including ipaddr, serverip, gatewayip (if needed), |
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netmask, ethaddr, eth1addr, rootpath (if using NFS root), |
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fdtfile, and bootfile). |
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Then, do one of the following, depending on whether you |
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want an NFS root or a ramdisk root: |
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run nfsboot |
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or |
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run ramboot |
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4 Notes |
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The console baudrate for MPC8323ERDB is 115200bps. |
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@ -0,0 +1,583 @@ |
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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*/ |
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|
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#undef DEBUG |
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|
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_E300 1 /* E300 family */ |
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#define CONFIG_QE 1 /* Has QE */ |
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#define CONFIG_MPC83XX 1 /* MPC83xx family */ |
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#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ |
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|
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#define CONFIG_PCI 1 |
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#define CONFIG_83XX_GENERIC_PCI 1 |
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|
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/*
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* System Clock Setup |
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*/ |
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
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|
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#ifndef CONFIG_SYS_CLK_FREQ |
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN |
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#endif |
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|
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/*
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* Hardware Reset Configuration Word |
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*/ |
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#define CFG_HRCW_LOW (\ |
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_VCO_1X2 |\
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HRCWL_CSB_TO_CLKIN_2X1 |\
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HRCWL_CORE_TO_CSB_2_5X1 |\
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HRCWL_CE_PLL_VCO_DIV_2 |\
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HRCWL_CE_PLL_DIV_1X1 |\
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HRCWL_CE_TO_PLL_1X3) |
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|
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#define CFG_HRCW_HIGH (\ |
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LALE_NORMAL) |
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|
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/*
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* System IO Config |
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*/ |
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#define CFG_SICRL 0x00000000 |
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|
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
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|
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/*
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* IMMR new address |
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*/ |
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#define CFG_IMMR 0xE0000000 |
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|
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/*
|
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* DDR Setup |
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*/ |
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ |
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#define CFG_SDRAM_BASE CFG_DDR_BASE |
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
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#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ |
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|
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#undef CONFIG_SPD_EEPROM |
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#if defined(CONFIG_SPD_EEPROM) |
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/* Determine DDR configuration from I2C interface
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*/ |
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ |
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#else |
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/* Manually set up DDR parameters
|
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*/ |
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#define CFG_DDR_SIZE 64 /* MB */ |
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#define CFG_DDR_CS0_CONFIG 0x80840101 |
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#define CFG_DDR_TIMING_0 0x00220802 |
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#define CFG_DDR_TIMING_1 0x3935d322 |
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#define CFG_DDR_TIMING_2 0x0f9048ca |
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#define CFG_DDR_TIMING_3 0x00000000 |
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#define CFG_DDR_CLK_CNTL 0x02000000 |
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#define CFG_DDR_MODE 0x44400232 |
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#define CFG_DDR_MODE2 0x8000c000 |
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#define CFG_DDR_INTERVAL 0x03200064 |
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#define CFG_DDR_CS0_BNDS 0x00000003 |
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#define CFG_DDR_SDRAM_CFG 0x43080000 |
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#define CFG_DDR_SDRAM_CFG2 0x00401000 |
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#endif |
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|
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/*
|
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* Memory test |
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*/ |
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#undef CFG_DRAM_TEST /* memory test, takes time */ |
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#define CFG_MEMTEST_START 0x00030000 /* memtest region */ |
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#define CFG_MEMTEST_END 0x03f00000 |
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|
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/*
|
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* The reserved memory |
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*/ |
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
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|
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
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#define CFG_RAMBOOT |
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#else |
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#undef CFG_RAMBOOT |
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#endif |
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|
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
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|
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/*
|
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* Initial RAM Base Address Setup |
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*/ |
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#define CFG_INIT_RAM_LOCK 1 |
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#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ |
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#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ |
||||
|
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ |
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_V) /* valid */ |
||||
#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ |
||||
|
||||
#ifdef CFG_LB_SDRAM |
||||
#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE |
||||
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ |
||||
|
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
||||
* |
||||
* CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
||||
* the top 17 bits of BR2. |
||||
*/ |
||||
|
||||
#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ |
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR2, need: |
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100 |
||||
* XAM, OR2[17:18] = 11 |
||||
* 9 columns OR2[19-21] = 010 |
||||
* 13 rows OR2[23-25] = 100 |
||||
* EAD set for extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
||||
*/ |
||||
|
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
|
||||
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
#define CFG_LBC_LSDMR_COMMON 0x0063b723 |
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_PCHALL) |
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_MRW) |
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_NORMAL) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Windows to access PIB via local bus |
||||
*/ |
||||
#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ |
||||
#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
#define OF_CPU "PowerPC,8323@0" |
||||
#define OF_SOC "soc8323@e0000000" |
||||
#define OF_QE "qe@e0100000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
|
||||
/*
|
||||
* Config on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_MMIO_BASE 0x90000000 |
||||
#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE |
||||
#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_IO_BASE 0xd0000000 |
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE |
||||
#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */ |
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* QE UEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_UEC_ETH |
||||
#define CONFIG_ETHPRIME "Freescale GETH" |
||||
|
||||
#define CONFIG_UEC_ETH1 /* ETH3 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH1 |
||||
#define CFG_UEC1_UCC_NUM 2 /* UCC3 */ |
||||
#define CFG_UEC1_RX_CLK QE_CLK9 |
||||
#define CFG_UEC1_TX_CLK QE_CLK10 |
||||
#define CFG_UEC1_ETH_TYPE FAST_ETH |
||||
#define CFG_UEC1_PHY_ADDR 4 |
||||
#define CFG_UEC1_INTERFACE_MODE ENET_100_MII |
||||
#endif |
||||
|
||||
#define CONFIG_UEC_ETH2 /* ETH4 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH2 |
||||
#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ |
||||
#define CFG_UEC2_RX_CLK QE_CLK16 |
||||
#define CFG_UEC2_TX_CLK QE_CLK3 |
||||
#define CFG_UEC2_ETH_TYPE FAST_ETH |
||||
#define CFG_UEC2_PHY_ADDR 0 |
||||
#define CFG_UEC2_INTERFACE_MODE ENET_100_MII |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_ASKENV |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
#if defined(CFG_RAMBOOT) |
||||
#undef CONFIG_CMD_ENV |
||||
#undef CONFIG_CMD_LOADS |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CFG_HID0_INIT 0x000000000 |
||||
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK |
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* Cache Config |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
|
||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ |
||||
#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
#define CFG_IBAT3L (0) |
||||
#define CFG_IBAT3U (0) |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10) |
||||
#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
|
||||
#ifdef CONFIG_PCI |
||||
/* PCI MEM space: cacheable */ |
||||
#define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
/* PCI MMIO space: cache-inhibit and guarded */ |
||||
#define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#else |
||||
#define CFG_IBAT5L (0) |
||||
#define CFG_IBAT5U (0) |
||||
#define CFG_IBAT6L (0) |
||||
#define CFG_IBAT6U (0) |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#endif |
||||
|
||||
/* Nothing in BAT7 */ |
||||
#define CFG_IBAT7L (0) |
||||
#define CFG_IBAT7U (0) |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_ETHADDR 00:04:9f:ef:03:01 |
||||
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ |
||||
#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 |
||||
|
||||
#define CONFIG_IPADDR 10.0.0.2 |
||||
#define CONFIG_SERVERIP 10.0.0.1 |
||||
#define CONFIG_GATEWAYIP 10.0.0.1 |
||||
#define CONFIG_NETMASK 255.0.0.0 |
||||
#define CONFIG_NETDEV eth1 |
||||
|
||||
#define CONFIG_HOSTNAME mpc8323erdb |
||||
#define CONFIG_ROOTPATH /nfsroot |
||||
#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot |
||||
#define CONFIG_BOOTFILE uImage |
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
||||
#define CONFIG_FDTFILE mpc832x_rdb.dtb |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define XMK_STR(x) #x |
||||
#define MK_STR(x) XMK_STR(x) |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftp $loadaddr $uboot;" \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
|
||||
"console=ttyS0\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setbootargs;" \
|
||||
"run setipargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv rootdev /dev/ram;" \
|
||||
"run setbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#undef MK_STR |
||||
#undef XMK_STR |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue