Add emulator support for T4240. Emulator has limited peripherals and interfaces. Difference between emulator and T4240QDS includes: ECC for DDR is disabled due the procedure to load images No board FPGA (QIXIS) NOR flash has 32-bit port for higher loading speed IFC and I2C timing don't really matter, so set them fast No ethernet Signed-off-by: York Sun <yorksun@freescale.com>master
York Sun
11 years ago
parent
f165bc3528
commit
1cb19fbb31
@ -0,0 +1,122 @@ |
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/*
|
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#ifndef __DDR_H__ |
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#define __DDR_H__ |
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struct board_specific_parameters { |
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u32 n_ranks; |
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u32 datarate_mhz_high; |
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u32 rank_gb; |
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u32 clk_adjust; |
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u32 wrlvl_start; |
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u32 wrlvl_ctl_2; |
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u32 wrlvl_ctl_3; |
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u32 cpo; |
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u32 write_data_delay; |
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u32 force_2T; |
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}; |
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|
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/*
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* These tables contain all valid speeds we want to override with board |
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* specific parameters. datarate_mhz_high values need to be in ascending order |
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* for each n_ranks group. |
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*/ |
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|
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#ifdef CONFIG_T4240QDS |
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static const struct board_specific_parameters udimm0[] = { |
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/*
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* memory controller 0 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
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*/ |
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{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
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{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, |
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{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, |
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{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, |
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{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
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{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
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{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
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{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
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{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, |
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{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
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{} |
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}; |
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static const struct board_specific_parameters rdimm0[] = { |
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/*
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* memory controller 0 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
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*/ |
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{4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0}, |
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{4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0}, |
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{4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0}, |
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{2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, |
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{2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
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{2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
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{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
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{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
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{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, |
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{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
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{} |
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}; |
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|
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#else /* CONFIG_T4240EMU */ |
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static const struct board_specific_parameters udimm0[] = { |
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/*
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* memory controller 0 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
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*/ |
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{2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, |
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{1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, |
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{} |
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}; |
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static const struct board_specific_parameters rdimm0[] = { |
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/*
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* memory controller 0 |
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
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*/ |
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{4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0}, |
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{2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0}, |
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{1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, |
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{} |
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}; |
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#endif /* CONFIG_T4240EMU */ |
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|
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/*
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* The three slots have slightly different timing. The center values are good |
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* for all slots. We use identical speed tables for them. In future use, if |
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* DIMMs require separated tables, make more entries as needed. |
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*/ |
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static const struct board_specific_parameters *udimms[] = { |
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udimm0, |
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}; |
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|
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/*
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* The three slots have slightly different timing. See comments above. |
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*/ |
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static const struct board_specific_parameters *rdimms[] = { |
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rdimm0, |
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}; |
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#endif |
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@ -0,0 +1,96 @@ |
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <i2c.h> |
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#include <netdev.h> |
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#include <linux/compiler.h> |
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#include <asm/mmu.h> |
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#include <asm/processor.h> |
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#include <asm/cache.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/fsl_law.h> |
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#include <asm/fsl_serdes.h> |
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#include <asm/fsl_portals.h> |
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#include <asm/fsl_liodn.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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struct cpu_type *cpu = gd->arch.cpu; |
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printf("Board: %sEMU\n", cpu->name); |
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return 0; |
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} |
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int board_early_init_r(void) |
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{ |
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); |
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited |
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* so that flash can be erased properly. |
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*/ |
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/* Flush d-cache and invalidate i-cache of any FLASH data */ |
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flush_dcache(); |
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invalidate_icache(); |
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/* invalidate existing TLB entry for flash */ |
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disable_tlb(flash_esel); |
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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0, flash_esel, BOOKE_PAGESZ_256M, 1); |
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set_liodns(); |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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setup_portals(); |
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#endif |
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return 0; |
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} |
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int misc_init_r(void) |
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{ |
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return 0; |
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} |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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phys_addr_t base; |
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phys_size_t size; |
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ft_cpu_setup(blob, bd); |
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base = getenv_bootm_low(); |
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size = getenv_bootm_size(); |
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fdt_fixup_memory(blob, (u64)base, (u64)size); |
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fdt_fixup_liodn(blob); |
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fdt_fixup_dr_usb(blob, bd); |
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} |
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@ -0,0 +1,185 @@ |
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* T4240 EMU board configuration file |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_T4240EMU |
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#define CONFIG_PHYS_64BIT |
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#define CONFIG_SYS_NO_FLASH 1 |
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#define CONFIG_SYS_FSL_DDR_EMU 1 |
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#define CONFIG_SYS_FSL_NO_QIXIS 1 |
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#define CONFIG_SYS_FSL_NO_SERDES 1 |
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#include "t4qds.h" |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_CACHE_FLUSH |
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#define CONFIG_ENV_IS_NOWHERE |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_SYS_CLK_FREQ 100000000 |
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#define CONFIG_DDR_CLK_FREQ 133333333 |
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#define CONFIG_FSL_TBCLK_EXTRA_DIV 100 |
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/*
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* DDR Setup |
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*/ |
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#define CONFIG_SYS_SPD_BUS_NUM 1 |
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#define SPD_EEPROM_ADDRESS1 0x51 |
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#define SPD_EEPROM_ADDRESS2 0x52 |
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#define SPD_EEPROM_ADDRESS3 0x53 |
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#define SPD_EEPROM_ADDRESS4 0x54 |
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#define SPD_EEPROM_ADDRESS5 0x55 |
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#define SPD_EEPROM_ADDRESS6 0x56 |
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
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#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
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/*
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* IFC Definitions |
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*/ |
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#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) |
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
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/* NOR Flash Timing Params */ |
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
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+ 0x8000000) | \
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CSPR_PORT_SIZE_32 | \
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CSPR_MSEL_NOR | \
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CSPR_V) |
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0) |
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ |
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FTIM0_NOR_TEADC(0x1) | \
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FTIM0_NOR_TEAHC(0x1)) |
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ |
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FTIM1_NOR_TRAD_NOR(0x1)) |
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ |
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FTIM2_NOR_TCH(0x0) | \
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FTIM2_NOR_TWP(0x1)) |
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#define CONFIG_SYS_NOR_FTIM3 0x04000000 |
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#define CONFIG_SYS_IFC_CCR 0x01000000 |
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
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/* I2C */ |
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#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */ |
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#define CONFIG_SYS_FSL_I2C2_SPEED 4000000 |
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/* Qman/Bman */ |
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#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
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#define CONFIG_SYS_BMAN_NUM_PORTALS 50 |
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#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
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#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
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#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
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#define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
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#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
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#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
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#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
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#define CONFIG_SYS_DPAA_FMAN |
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#define CONFIG_SYS_DPAA_PME |
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#define CONFIG_SYS_PMAN |
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#define CONFIG_SYS_DPAA_DCE |
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#define CONFIG_SYS_INTERLAKEN |
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
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#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 |
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
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#define CONFIG_BOOTDELAY 0 |
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/*
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* T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be |
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* 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way |
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* interleaving. It can be cacheline, page, bank, superbank. |
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* See doc/README.fsl-ddr for details. |
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*/ |
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#ifdef CONFIG_PPC_T4240 |
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#define CTRL_INTLV_PREFERED 3way_4KB |
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#else |
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#define CTRL_INTLV_PREFERED cacheline |
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#endif |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"hwconfig=fsl_ddr:" \
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"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
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"bank_intlv=auto;" \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=t4240emu/ramdisk.uboot\0" \
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"fdtaddr=c00000\0" \
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"fdtfile=t4240emu/t4240emu.dtb\0" \
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"bdev=sda3\0" \
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"c=ffe\0" |
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/*
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* For emulation this causes u-boot to jump to the start of the proof point |
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* app code automatically |
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*/ |
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#define CONFIG_PROOF_POINTS \ |
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"setenv bootargs root=/dev/$bdev rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"cpu 1 release 0x29000000 - - -;" \
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"cpu 2 release 0x29000000 - - -;" \
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"cpu 3 release 0x29000000 - - -;" \
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"cpu 4 release 0x29000000 - - -;" \
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"cpu 5 release 0x29000000 - - -;" \
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"cpu 6 release 0x29000000 - - -;" \
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"cpu 7 release 0x29000000 - - -;" \
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"go 0x29000000" |
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|
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#define CONFIG_HVBOOT \ |
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"setenv bootargs config-addr=0x60000000; " \
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"bootm 0x01000000 - 0x00f00000" |
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|
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#define CONFIG_LINUX \ |
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"errata;" \
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"setenv othbootargs ignore_loglevel;" \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"setenv ramdiskaddr 0x02000000;" \
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"setenv fdtaddr 0x00c00000;" \
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"setenv loadaddr 0x1000000;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr" |
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|
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#define CONFIG_BOOTCOMMAND CONFIG_LINUX |
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#endif /* __CONFIG_H */ |
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Reference in new issue