- minimal setup for CardBus bridges - add EEPROM read/write support in the CS8900 driver - add support for the builtin I2C controller in the Samsung s3c24x0 chips - add support for MPL's VCMA9 (Samsung s3c2410 based) board * Patch by Steven Scholz, 04 Feb 2003: add support for RTC DS1307 * Patch by Reinhard Meyer, 5 Feb 2003: fix PLPRCR/SCCR init sequence on 8xx to allow for changes of EBDF by software * Patch by Vladimir Gurevich, 07 Feb 2003: "API-compatibility patch" for 4xx I2C drivermaster
wdenk
22 years ago
parent
500545cc6b
commit
1cb8e980c4
@ -0,0 +1,49 @@ |
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := vcma9.o flash.o cmd_vcma9.o
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OBJS += ../common/common_util.o ../common/memtst.o
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SOBJS := memsetup.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,144 @@ |
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/*
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* (C) Copyright 2002 |
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch |
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* |
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* adapted for VCMA9 |
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include "vcma9.h" |
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#include "../common/common_util.h" |
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#if defined(CONFIG_DRIVER_CS8900) |
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#include <../drivers/cs8900.h> |
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static uchar cs8900_chksum(ushort data) |
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{ |
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return((data >> 8) & 0x00FF) + (data & 0x00FF); |
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} |
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#endif |
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extern void print_vcma9_info(void); |
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extern int vcma9_cantest(void); |
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extern int vcma9_nandtest(void); |
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extern int vcma9_dactest(void); |
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extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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/* ------------------------------------------------------------------------- */ |
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int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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if (strcmp(argv[1], "info") == 0) |
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{ |
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print_vcma9_info(); |
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return 0; |
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} |
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#if defined(CONFIG_DRIVER_CS8900) |
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if (strcmp(argv[1], "cs8900_eeprom") == 0) { |
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if (strcmp(argv[2], "read") == 0) { |
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uchar addr; ushort data; |
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addr = simple_strtoul(argv[3], NULL, 16); |
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cs8900_e2prom_read(addr, &data); |
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printf("0x%2.2X: 0x%4.4X\n", addr, data); |
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} else if (strcmp(argv[2], "write") == 0) { |
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uchar addr; ushort data; |
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addr = simple_strtoul(argv[3], NULL, 16); |
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data = simple_strtoul(argv[4], NULL, 16); |
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cs8900_e2prom_write(addr, data); |
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} else if (strcmp(argv[2], "setaddr") == 0) { |
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uchar addr, i, csum; ushort data; |
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/* check for valid ethaddr */ |
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for (i = 0; i < 6; i++) |
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if (gd->bd->bi_enetaddr[i] != 0) |
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break; |
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if (i < 6) { |
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addr = 1; |
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data = 0x2158; |
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cs8900_e2prom_write(addr, data); |
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csum = cs8900_chksum(data); |
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addr++; |
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for (i = 0; i < 6; i+=2) { |
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data = gd->bd->bi_enetaddr[i+1] << 8 | |
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gd->bd->bi_enetaddr[i]; |
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cs8900_e2prom_write(addr, data); |
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csum += cs8900_chksum(data); |
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addr++; |
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} |
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/* calculate header link byte */ |
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data = 0xA100 | (addr * 2); |
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cs8900_e2prom_write(0, data); |
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csum += cs8900_chksum(data); |
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/* write checksum word */ |
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cs8900_e2prom_write(addr, (0 - csum) << 8); |
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} else { |
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printf("\nplease defined 'ethaddr'\n"); |
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} |
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} else if (strcmp(argv[2], "dump") == 0) { |
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uchar addr, endaddr, csum; ushort data; |
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printf("Dump of CS8900 config device: "); |
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cs8900_e2prom_read(addr, &data); |
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if ((data & 0xE000) == 0xA000) { |
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endaddr = (data & 0x00FF) / 2; |
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csum = cs8900_chksum(data); |
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for (addr = 1; addr <= endaddr; addr++) { |
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cs8900_e2prom_read(addr, &data); |
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printf("\n0x%2.2X: 0x%4.4X", addr, data); |
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csum += cs8900_chksum(data); |
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} |
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printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong"); |
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} else { |
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printf("no valid config found"); |
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} |
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printf("\n"); |
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} |
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return 0; |
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} |
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#endif |
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#if 0 |
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if (strcmp(argv[1], "cantest") == 0) { |
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vcma9_cantest(); |
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return 0; |
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} |
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if (strcmp(argv[1], "nandtest") == 0) { |
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vcma9_nandtest(); |
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return 0; |
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} |
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if (strcmp(argv[1], "dactest") == 0) { |
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vcma9_dactest(); |
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return 0; |
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} |
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#endif |
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return (do_mplcommon(cmdtp, flag, argc, argv)); |
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} |
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@ -0,0 +1,24 @@ |
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#
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# (C) Copyright 2002
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# MPL VCMA9 board with S3C2410X (ARM920T) cpu
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#
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# see http://www.mpl.ch/ for more information about the MPL VCMA9
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#
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#
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# MPL VCMA9 has 1 bank of 64 MB DRAM
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#
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# 3000'0000 to 3400'0000
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#
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# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
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# optionally with a ramdisk at 3080'0000
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#
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# we load ourself to 33F0'0000
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#
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# download area is 3300'0000
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#
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TEXT_BASE = 0x33F00000
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@ -0,0 +1,445 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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ulong myflush(void); |
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#define FLASH_BANK_SIZE PHYS_FLASH_SIZE |
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#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
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#define CMD_READ_ARRAY 0x000000F0 |
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#define CMD_UNLOCK1 0x000000AA |
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#define CMD_UNLOCK2 0x00000055 |
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#define CMD_ERASE_SETUP 0x00000080 |
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#define CMD_ERASE_CONFIRM 0x00000030 |
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#define CMD_PROGRAM 0x000000A0 |
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#define CMD_UNLOCK_BYPASS 0x00000020 |
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#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) |
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#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) |
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#define BIT_ERASE_DONE 0x00000080 |
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#define BIT_RDY_MASK 0x00000080 |
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#define BIT_PROGRAM_ERROR 0x00000020 |
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#define BIT_TIMEOUT 0x80000000 /* our flag */ |
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#define READY 1 |
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#define ERR 2 |
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#define TMO 4 |
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/*-----------------------------------------------------------------------
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*/ |
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ulong flash_init(void) |
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{ |
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int i, j; |
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ulong size = 0; |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) |
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{ |
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ulong flashbase = 0; |
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flash_info[i].flash_id = |
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#if defined(CONFIG_AMD_LV400) |
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(AMD_MANUFACT & FLASH_VENDMASK) | |
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(AMD_ID_LV400B & FLASH_TYPEMASK); |
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#elif defined(CONFIG_AMD_LV800) |
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(AMD_MANUFACT & FLASH_VENDMASK) | |
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(AMD_ID_LV800B & FLASH_TYPEMASK); |
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#else |
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#error "Unknown flash configured" |
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#endif |
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flash_info[i].size = FLASH_BANK_SIZE; |
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flash_info[i].sector_count = CFG_MAX_FLASH_SECT; |
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memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); |
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if (i == 0) |
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flashbase = PHYS_FLASH_1; |
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else |
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panic("configured to many flash banks!\n"); |
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for (j = 0; j < flash_info[i].sector_count; j++) |
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{ |
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if (j <= 3) |
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{ |
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/* 1st one is 16 KB */ |
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if (j == 0) |
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{ |
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flash_info[i].start[j] = flashbase + 0; |
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} |
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|
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/* 2nd and 3rd are both 8 KB */ |
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if ((j == 1) || (j == 2)) |
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{ |
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flash_info[i].start[j] = flashbase + 0x4000 + (j-1)*0x2000; |
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} |
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/* 4th 32 KB */ |
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if (j == 3) |
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{ |
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flash_info[i].start[j] = flashbase + 0x8000; |
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} |
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} |
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else |
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{ |
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flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE; |
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} |
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} |
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size += flash_info[i].size; |
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} |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_FLASH_BASE, |
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CFG_FLASH_BASE + _armboot_end - _armboot_start, |
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&flash_info[0]); |
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|
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flash_protect(FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, |
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&flash_info[0]); |
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return size; |
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} |
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|
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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|
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switch (info->flash_id & FLASH_VENDMASK) |
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{ |
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case (AMD_MANUFACT & FLASH_VENDMASK): |
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printf("AMD: "); |
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break; |
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default: |
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printf("Unknown Vendor "); |
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break; |
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} |
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|
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switch (info->flash_id & FLASH_TYPEMASK) |
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{ |
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case (AMD_ID_LV400B & FLASH_TYPEMASK): |
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printf("1x Amd29LV400BB (4Mbit)\n"); |
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break; |
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case (AMD_ID_LV800B & FLASH_TYPEMASK): |
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printf("1x Amd29LV800BB (8Mbit)\n"); |
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break; |
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default: |
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printf("Unknown Chip Type\n"); |
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goto Done; |
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break; |
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} |
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|
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printf(" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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|
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printf(" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; i++) |
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{ |
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if ((i % 5) == 0) |
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{ |
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printf ("\n "); |
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} |
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printf (" %08lX%s", info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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|
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Done: |
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} |
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|
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/*-----------------------------------------------------------------------
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*/ |
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|
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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ushort result; |
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int iflag, cflag, prot, sect; |
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int rc = ERR_OK; |
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int chip; |
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|
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/* first look for protection bits */ |
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|
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if (info->flash_id == FLASH_UNKNOWN) |
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return ERR_UNKNOWN_FLASH_TYPE; |
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|
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if ((s_first < 0) || (s_first > s_last)) { |
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return ERR_INVAL; |
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} |
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|
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if ((info->flash_id & FLASH_VENDMASK) != |
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(AMD_MANUFACT & FLASH_VENDMASK)) { |
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return ERR_UNKNOWN_FLASH_VENDOR; |
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} |
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|
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) |
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return ERR_PROTECTED; |
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|
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/*
|
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* Disable interrupts which might cause a timeout |
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* here. Remember that our exception vectors are |
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* at address 0 in the flash, and we don't want a |
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* (ticker) exception to happen while the flash |
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* chip is in programming mode. |
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*/ |
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cflag = icache_status(); |
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icache_disable(); |
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iflag = disable_interrupts(); |
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|
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect<=s_last && !ctrlc(); sect++) |
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{ |
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printf("Erasing sector %2d ... ", sect); |
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|
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked(); |
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|
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if (info->protect[sect] == 0) |
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{ /* not protected */ |
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vu_short *addr = (vu_short *)(info->start[sect]); |
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|
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MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
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MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
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MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; |
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|
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MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
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MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
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*addr = CMD_ERASE_CONFIRM; |
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|
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/* wait until flash is ready */ |
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chip = 0; |
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|
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do |
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{ |
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result = *addr; |
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|
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/* check timeout */ |
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if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) |
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{ |
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY; |
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chip = TMO; |
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break; |
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} |
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|
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if (!chip && (result & 0xFFFF) & BIT_ERASE_DONE) |
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chip = READY; |
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|
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if (!chip && (result & 0xFFFF) & BIT_PROGRAM_ERROR) |
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chip = ERR; |
||||
|
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} while (!chip); |
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|
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY; |
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|
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if (chip == ERR) |
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{ |
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rc = ERR_PROG_ERROR; |
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goto outahere; |
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} |
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if (chip == TMO) |
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{ |
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rc = ERR_TIMOUT; |
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goto outahere; |
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} |
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|
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printf("ok.\n"); |
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} |
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else /* it was protected */ |
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{ |
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printf("protected!\n"); |
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} |
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} |
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|
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if (ctrlc()) |
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printf("User Interrupt!\n"); |
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|
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outahere: |
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/* allow flash to settle - wait 10 ms */ |
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udelay_masked(10000); |
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|
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if (iflag) |
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enable_interrupts(); |
||||
|
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if (cflag) |
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icache_enable(); |
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|
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return rc; |
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} |
||||
|
||||
/*-----------------------------------------------------------------------
|
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* Copy memory to flash |
||||
*/ |
||||
|
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volatile static int write_hword (flash_info_t *info, ulong dest, ushort data) |
||||
{ |
||||
vu_short *addr = (vu_short *)dest; |
||||
ushort result; |
||||
int rc = ERR_OK; |
||||
int cflag, iflag; |
||||
int chip; |
||||
|
||||
/*
|
||||
* Check if Flash is (sufficiently) erased |
||||
*/ |
||||
result = *addr; |
||||
if ((result & data) != data) |
||||
return ERR_NOT_ERASED; |
||||
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout |
||||
* here. Remember that our exception vectors are |
||||
* at address 0 in the flash, and we don't want a |
||||
* (ticker) exception to happen while the flash |
||||
* chip is in programming mode. |
||||
*/ |
||||
cflag = icache_status(); |
||||
icache_disable(); |
||||
iflag = disable_interrupts(); |
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM; |
||||
*addr = data; |
||||
|
||||
/* arm simple, non interrupt dependent timer */ |
||||
reset_timer_masked(); |
||||
|
||||
/* wait until flash is ready */ |
||||
chip = 0; |
||||
do |
||||
{ |
||||
result = *addr; |
||||
|
||||
/* check timeout */ |
||||
if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) |
||||
{ |
||||
chip = ERR | TMO; |
||||
break; |
||||
} |
||||
if (!chip && ((result & 0x80) == (data & 0x80))) |
||||
chip = READY; |
||||
|
||||
if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) |
||||
{ |
||||
result = *addr; |
||||
|
||||
if ((result & 0x80) == (data & 0x80)) |
||||
chip = READY; |
||||
else |
||||
chip = ERR; |
||||
} |
||||
|
||||
} while (!chip); |
||||
|
||||
*addr = CMD_READ_ARRAY; |
||||
|
||||
if (chip == ERR || *addr != data) |
||||
rc = ERR_PROG_ERROR; |
||||
|
||||
if (iflag) |
||||
enable_interrupts(); |
||||
|
||||
if (cflag) |
||||
icache_enable(); |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash. |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp; |
||||
int l; |
||||
int i, rc; |
||||
ushort data; |
||||
|
||||
wp = (addr & ~1); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data >> 8) | (*(uchar *)cp << 8); |
||||
} |
||||
for (; i<2 && cnt>0; ++i) { |
||||
data = (data >> 8) | (*src++ << 8); |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<2; ++i, ++cp) { |
||||
data = (data >> 8) | (*(uchar *)cp << 8); |
||||
} |
||||
|
||||
if ((rc = write_hword(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 2; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 2) { |
||||
data = *((vu_short*)src); |
||||
if ((rc = write_hword(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
src += 2; |
||||
wp += 2; |
||||
cnt -= 2; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return ERR_OK; |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { |
||||
data = (data >> 8) | (*src++ << 8); |
||||
--cnt; |
||||
} |
||||
for (; i<2; ++i, ++cp) { |
||||
data = (data >> 8) | (*(uchar *)cp << 8); |
||||
} |
||||
|
||||
return write_hword(info, wp, data); |
||||
} |
||||
@ -0,0 +1,160 @@ |
||||
/* |
||||
* Memory Setup stuff - taken from blob memsetup.S |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
|
||||
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
|
||||
* |
||||
* Modified for the Samsung SMDK2410 by |
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
|
||||
/* some parameters for the board */ |
||||
|
||||
#define BWSCON 0x48000000 |
||||
|
||||
/* BWSCON */ |
||||
#define DW8 (0x0) |
||||
#define DW16 (0x1) |
||||
#define DW32 (0x2) |
||||
#define WAIT (0x1<<2) |
||||
#define UBLB (0x1<<3) |
||||
|
||||
#define B1_BWSCON (DW16) |
||||
#define B2_BWSCON (DW32) |
||||
#define B3_BWSCON (DW32) |
||||
#define B4_BWSCON (DW16 + WAIT + UBLB) |
||||
#define B5_BWSCON (DW8 + UBLB) |
||||
#define B6_BWSCON (DW32) |
||||
#define B7_BWSCON (DW32) |
||||
|
||||
/* BANK0CON */ |
||||
#define B0_Tacs 0x0 /* 0clk */ |
||||
#define B0_Tcos 0x0 /* 0clk */ |
||||
#define B0_Tacc 0x5 /* 8clk */ |
||||
#define B0_Tcoh 0x0 /* 0clk */ |
||||
#define B0_Tah 0x0 /* 0clk */ |
||||
#define B0_Tacp 0x0 /* page mode is not used */ |
||||
#define B0_PMC 0x0 /* page mode disabled */ |
||||
|
||||
/* BANK1CON */ |
||||
#define B1_Tacs 0x0 /* 0clk */ |
||||
#define B1_Tcos 0x0 /* 0clk */ |
||||
#define B1_Tacc 0x5 /* 8clk */ |
||||
#define B1_Tcoh 0x0 /* 0clk */ |
||||
#define B1_Tah 0x0 /* 0clk */ |
||||
#define B1_Tacp 0x0 /* page mode is not used */ |
||||
#define B1_PMC 0x0 /* page mode disabled */ |
||||
|
||||
#define B2_Tacs 0x3 /* 4clk */ |
||||
#define B2_Tcos 0x3 /* 4clk */ |
||||
#define B2_Tacc 0x7 /* 14clk */ |
||||
#define B2_Tcoh 0x3 /* 4clk */ |
||||
#define B2_Tah 0x3 /* 4clk */ |
||||
#define B2_Tacp 0x0 /* page mode is not used */ |
||||
#define B2_PMC 0x0 /* page mode disabled */ |
||||
|
||||
#define B3_Tacs 0x3 /* 4clk */ |
||||
#define B3_Tcos 0x3 /* 4clk */ |
||||
#define B3_Tacc 0x7 /* 14clk */ |
||||
#define B3_Tcoh 0x3 /* 4clk */ |
||||
#define B3_Tah 0x3 /* 4clk */ |
||||
#define B3_Tacp 0x0 /* page mode is not used */ |
||||
#define B3_PMC 0x0 /* page mode disabled */ |
||||
|
||||
#define B4_Tacs 0x3 /* 4clk */ |
||||
#define B4_Tcos 0x1 /* 1clk */ |
||||
#define B4_Tacc 0x7 /* 14clk */ |
||||
#define B4_Tcoh 0x1 /* 1clk */ |
||||
#define B4_Tah 0x0 /* 0clk */ |
||||
#define B4_Tacp 0x0 /* page mode is not used */ |
||||
#define B4_PMC 0x0 /* page mode disabled */ |
||||
|
||||
#define B5_Tacs 0x0 /* 0clk */ |
||||
#define B5_Tcos 0x3 /* 4clk */ |
||||
#define B5_Tacc 0x5 /* 8clk */ |
||||
#define B5_Tcoh 0x2 /* 2clk */ |
||||
#define B5_Tah 0x1 /* 1clk */ |
||||
#define B5_Tacp 0x0 /* page mode is not used */ |
||||
#define B5_PMC 0x0 /* page mode disabled */ |
||||
|
||||
#define B6_MT 0x3 /* SDRAM */ |
||||
#define B6_Trcd 0x1 /* 3clk */ |
||||
#define B6_SCAN 0x2 /* 10bit */ |
||||
|
||||
#define B7_MT 0x3 /* SDRAM */ |
||||
#define B7_Trcd 0x1 /* 3clk */ |
||||
#define B7_SCAN 0x2 /* 10bit */ |
||||
|
||||
/* REFRESH parameter */ |
||||
#define REFEN 0x1 /* Refresh enable */ |
||||
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ |
||||
#define Trp 0x0 /* 2clk */ |
||||
#define Trc 0x3 /* 7clk */ |
||||
#define Tchr 0x2 /* 3clk */ |
||||
#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ |
||||
/**************************************/ |
||||
|
||||
_TEXT_BASE: |
||||
.word TEXT_BASE
|
||||
|
||||
.globl memsetup
|
||||
memsetup: |
||||
/* memory control configuration */ |
||||
/* make r0 relative the current location so that it */ |
||||
/* reads SMRDATA out of FLASH rather than memory ! */ |
||||
ldr r0, =SMRDATA |
||||
ldr r1, _TEXT_BASE |
||||
sub r0, r0, r1 |
||||
ldr r1, =BWSCON /* Bus Width Status Controller */ |
||||
add r2, r0, #13*4 |
||||
0: |
||||
ldr r3, [r0], #4 |
||||
str r3, [r1], #4 |
||||
cmp r2, r0 |
||||
bne 0b |
||||
|
||||
/* everything is fine now */ |
||||
mov pc, lr |
||||
|
||||
.ltorg |
||||
/* the literal pools origin */ |
||||
|
||||
SMRDATA: |
||||
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) |
||||
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) |
||||
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) |
||||
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) |
||||
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) |
||||
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) |
||||
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) |
||||
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) |
||||
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) |
||||
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) |
||||
.word 0x32
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
@ -0,0 +1,54 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm920t/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
armboot_end_data = .; |
||||
|
||||
. = ALIGN(4); |
||||
.bss : { *(.bss) } |
||||
|
||||
armboot_end = .; |
||||
} |
||||
@ -0,0 +1,248 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <s3c2410.h> |
||||
#include <i2c.h> |
||||
|
||||
#include "vcma9.h" |
||||
#include "../common/common_util.h" |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#define FCLK_SPEED 1 |
||||
|
||||
#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ |
||||
#define M_MDIV 0xC3 |
||||
#define M_PDIV 0x4 |
||||
#define M_SDIV 0x1 |
||||
#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ |
||||
#define M_MDIV 0xA1 |
||||
#define M_PDIV 0x3 |
||||
#define M_SDIV 0x1 |
||||
#endif |
||||
|
||||
#define USB_CLOCK 1 |
||||
|
||||
#if USB_CLOCK==0 |
||||
#define U_M_MDIV 0xA1 |
||||
#define U_M_PDIV 0x3 |
||||
#define U_M_SDIV 0x1 |
||||
#elif USB_CLOCK==1 |
||||
#define U_M_MDIV 0x48 |
||||
#define U_M_PDIV 0x3 |
||||
#define U_M_SDIV 0x2 |
||||
#endif |
||||
|
||||
static inline void delay(unsigned long loops) |
||||
{ |
||||
__asm__ volatile ("1:\n" |
||||
"subs %0, %1, #1\n" |
||||
"bne 1b":"=r" (loops):"0" (loops)); |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* to reduce PLL lock time, adjust the LOCKTIME register */ |
||||
rLOCKTIME = 0xFFFFFF; |
||||
|
||||
/* configure MPLL */ |
||||
rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); |
||||
|
||||
/* some delay between MPLL and UPLL */ |
||||
delay (4000); |
||||
|
||||
/* configure UPLL */ |
||||
rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); |
||||
|
||||
/* some delay between MPLL and UPLL */ |
||||
delay (8000); |
||||
|
||||
/* set up the I/O ports */ |
||||
rGPACON = 0x007FFFFF; |
||||
rGPBCON = 0x002AAAAA; |
||||
rGPBUP = 0x000002BF; |
||||
rGPCCON = 0xAAAAAAAA; |
||||
rGPCUP = 0x0000FFFF; |
||||
rGPDCON = 0xAAAAAAAA; |
||||
rGPDUP = 0x0000FFFF; |
||||
rGPECON = 0xAAAAAAAA; |
||||
rGPEUP = 0x000037F7; |
||||
rGPFCON = 0x00000000; |
||||
rGPFUP = 0x00000000; |
||||
rGPGCON = 0xFFEAFF5A; |
||||
rGPGUP = 0x0000F0DC; |
||||
rGPHCON = 0x0028AAAA; |
||||
rGPHUP = 0x00000656; |
||||
|
||||
/* setup correct IRQ modes for NIC */ |
||||
rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */ |
||||
|
||||
/* init serial */ |
||||
gd->baudrate = CONFIG_BAUDRATE; |
||||
gd->have_console = 1; |
||||
serial_init(); |
||||
|
||||
/* arch number of VCMA9-Board */ |
||||
gd->bd->bi_arch_number = 227; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x30000100; |
||||
|
||||
icache_enable(); |
||||
dcache_enable(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Get some Board/PLD Info |
||||
*/ |
||||
|
||||
static uchar Get_PLD_ID(void) |
||||
{ |
||||
return(*(volatile uchar *)PLD_ID_REG); |
||||
} |
||||
|
||||
static uchar Get_PLD_BOARD(void) |
||||
{ |
||||
return(*(volatile uchar *)PLD_BOARD_REG); |
||||
} |
||||
|
||||
static uchar Get_PLD_Version(void) |
||||
{ |
||||
return((Get_PLD_ID() >> 4) & 0x0F); |
||||
} |
||||
|
||||
static uchar Get_PLD_Revision(void) |
||||
{ |
||||
return(Get_PLD_ID() & 0x0F); |
||||
} |
||||
|
||||
static int Get_Board_Config(void) |
||||
{ |
||||
uchar config = Get_PLD_BOARD() & 0x03; |
||||
|
||||
if (config == 3) |
||||
return 1; |
||||
else |
||||
return 0; |
||||
} |
||||
|
||||
static uchar Get_Board_PCB(void) |
||||
{ |
||||
return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
*/ |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
unsigned char s[50]; |
||||
unsigned char bc, var, rc; |
||||
int i; |
||||
backup_t *b = (backup_t *) s; |
||||
|
||||
puts("Board: "); |
||||
|
||||
i = getenv_r("serial#", s, 32); |
||||
if ((i < 0) || strncmp (s, "VCMA9", 5)) { |
||||
get_backup_values (b); |
||||
if (strncmp (b->signature, "MPL\0", 4) != 0) { |
||||
puts ("### No HW ID - assuming VCMA9"); |
||||
} else { |
||||
b->serial_name[5] = 0; |
||||
printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(), |
||||
Get_Board_PCB(), &b->serial_name[6]); |
||||
} |
||||
} else { |
||||
s[5] = 0; |
||||
printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(), |
||||
&s[6]); |
||||
} |
||||
printf("\n"); |
||||
return(0); |
||||
} |
||||
|
||||
|
||||
|
||||
void print_vcma9_rev(void) |
||||
{ |
||||
printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n", |
||||
Get_Board_Config(), Get_Board_PCB(), |
||||
Get_PLD_Version(), Get_PLD_Revision()); |
||||
} |
||||
|
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
print_vcma9_rev(); |
||||
show_stdio_dev(); |
||||
check_env(); |
||||
return 0; |
||||
} |
||||
|
||||
/***************************************************************************
|
||||
* some helping routines |
||||
*/ |
||||
|
||||
int overwrite_console(void) |
||||
{ |
||||
/* return TRUE if console should be overwritten */ |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
/************************************************************************
|
||||
* Print VCMA9 Info |
||||
************************************************************************/ |
||||
void print_vcma9_info(void) |
||||
{ |
||||
print_vcma9_rev(); |
||||
} |
||||
|
||||
|
||||
@ -0,0 +1,43 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, d.mueller@elsoft.ch |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
/****************************************************************************
|
||||
* Global routines used for VCMA9 |
||||
*****************************************************************************/ |
||||
|
||||
|
||||
extern int mem_test(unsigned long start, unsigned long ramsize,int mode); |
||||
|
||||
void print_vcma9_info(void); |
||||
|
||||
|
||||
#define PLD_BASE_ADDRESS 0x2C000100 |
||||
#define PLD_ID_REG (PLD_BASE_ADDRESS + 0) |
||||
#define PLD_NIC_REG (PLD_BASE_ADDRESS + 1) |
||||
#define PLD_CAN_REG (PLD_BASE_ADDRESS + 2) |
||||
#define PLD_MISC_REG (PLD_BASE_ADDRESS + 3) |
||||
#define PLD_GPCD_REG (PLD_BASE_ADDRESS + 4) |
||||
#define PLD_BOARD_REG (PLD_BASE_ADDRESS + 5) |
||||
|
||||
|
||||
|
||||
@ -0,0 +1,409 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, d.mueller@elsoft.ch |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* This code should work for both the S3C2400 and the S3C2410
|
||||
* as they seem to have the same I2C controller inside. |
||||
* The different address mapping is handled by the s3c24xx.h files below. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CONFIG_DRIVER_S3C24X0_I2C |
||||
|
||||
#if defined(CONFIG_S3C2400) |
||||
#include <s3c2400.h> |
||||
#elif defined(CONFIG_S3C2410) |
||||
#include <s3c2410.h> |
||||
#endif |
||||
#include <i2c.h> |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
|
||||
#define IIC_WRITE 0 |
||||
#define IIC_READ 1 |
||||
|
||||
#define IIC_OK 0 |
||||
#define IIC_NOK 1 |
||||
#define IIC_NACK 2 |
||||
#define IIC_NOK_LA 3 /* Lost arbitration */ |
||||
#define IIC_NOK_TOUT 4 /* time out */ |
||||
|
||||
#define IICSTAT_BSY 0x20 /* Busy bit */ |
||||
#define IICSTAT_NACK 0x01 /* Nack bit */ |
||||
#define IICCON_IRPND 0x10 /* Interrupt pending bit */ |
||||
#define IIC_MODE_MT 0xC0 /* Master Transmit Mode */ |
||||
#define IIC_MODE_MR 0x80 /* Master Receive Mode */ |
||||
#define IIC_START_STOP 0x20 /* START / STOP */ |
||||
#define IIC_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ |
||||
|
||||
#define IIC_TIMEOUT 1 /* 1 seconde */ |
||||
|
||||
|
||||
static int GetIICSDA(void) |
||||
{ |
||||
return (rGPEDAT & 0x8000) >> 15; |
||||
} |
||||
|
||||
static void SetIICSDA(int x) |
||||
{ |
||||
rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; |
||||
} |
||||
|
||||
static void SetIICSCL(int x) |
||||
{ |
||||
rGPEDAT = (rGPEDAT & ~0x4000) | (x&1) << 14; |
||||
} |
||||
|
||||
|
||||
static int WaitForXfer(void) |
||||
{ |
||||
int i, status; |
||||
|
||||
i = IIC_TIMEOUT * 1000; |
||||
status = rIICCON; |
||||
while ((i > 0) && !(status & IICCON_IRPND)) { |
||||
udelay(1000); |
||||
status = rIICCON; |
||||
i--; |
||||
} |
||||
|
||||
return(status & IICCON_IRPND) ? IIC_OK : IIC_NOK_TOUT; |
||||
} |
||||
|
||||
static int IsACK(void) |
||||
{ |
||||
return(!(rIICSTAT & IICSTAT_NACK)); |
||||
} |
||||
|
||||
static void ReadWriteByte(void) |
||||
{ |
||||
rIICCON &= ~IICCON_IRPND; |
||||
} |
||||
|
||||
void i2c_init (int speed, int slaveadd) |
||||
{ |
||||
ulong freq, pres = 16, div; |
||||
int i, status; |
||||
|
||||
/* wait for some time to give previous transfer a chance to finish */ |
||||
|
||||
i = IIC_TIMEOUT * 1000; |
||||
status = rIICSTAT; |
||||
while ((i > 0) && (status & IICSTAT_BSY)) { |
||||
udelay(1000); |
||||
status = rIICSTAT; |
||||
i--; |
||||
} |
||||
|
||||
if ((status & IICSTAT_BSY) || GetIICSDA() == 0) { |
||||
ulong old_gpecon = rGPECON; |
||||
/* bus still busy probably by (most) previously interrupted transfer */ |
||||
|
||||
/* set IICSDA and IICSCL (GPE15, GPE14) to GPIO */ |
||||
rGPECON = (rGPECON & ~0xF0000000) | 0x10000000; |
||||
|
||||
/* toggle IICSCL until bus idle */ |
||||
SetIICSCL(0); udelay(1000); |
||||
i = 10; |
||||
while ((i > 0) && (GetIICSDA() != 1)) { |
||||
SetIICSCL(1); udelay(1000); |
||||
SetIICSCL(0); udelay(1000); |
||||
i--; |
||||
} |
||||
SetIICSCL(1); udelay(1000); |
||||
|
||||
/* restore pin functions */ |
||||
rGPECON = old_gpecon; |
||||
} |
||||
|
||||
/* calculate prescaler and divisor values */ |
||||
freq = get_PCLK(); |
||||
if ((freq / pres / (16+1)) > speed) |
||||
/* set prescaler to 512 */ |
||||
pres = 512; |
||||
|
||||
div = 0; |
||||
while ((freq / pres / (div+1)) > speed) |
||||
div++; |
||||
|
||||
/* set prescaler, divisor according to freq, also set
|
||||
ACKGEN, IRQ */ |
||||
rIICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); |
||||
|
||||
/* init to SLAVE REVEIVE and set slaveaddr */ |
||||
rIICSTAT = 0; |
||||
rIICADD = slaveadd; |
||||
/* program Master Transmit (and implicit STOP) */ |
||||
rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA; |
||||
|
||||
} |
||||
|
||||
/*
|
||||
cmd_type is 0 for write 1 for read. |
||||
|
||||
addr_len can take any value from 0-255, it is only limited |
||||
by the char, we could make it larger if needed. If it is |
||||
0 we skip the address write cycle. |
||||
|
||||
*/ |
||||
static |
||||
int i2c_transfer(unsigned char cmd_type, |
||||
unsigned char chip, |
||||
unsigned char addr[], |
||||
unsigned char addr_len, |
||||
unsigned char data[], |
||||
unsigned short data_len) |
||||
{ |
||||
int i, status, result; |
||||
|
||||
if (data == 0 || data_len == 0) { |
||||
/*Don't support data transfer of no length or to address 0*/ |
||||
printf( "i2c_transfer: bad call\n" ); |
||||
return IIC_NOK; |
||||
} |
||||
|
||||
//CheckDelay();
|
||||
|
||||
/* Check I2C bus idle */ |
||||
i = IIC_TIMEOUT * 1000; |
||||
status = rIICSTAT; |
||||
while ((i > 0) && (status & IICSTAT_BSY)) { |
||||
udelay(1000); |
||||
status = rIICSTAT; |
||||
i--; |
||||
} |
||||
|
||||
|
||||
if (status & IICSTAT_BSY) { |
||||
result = IIC_NOK_TOUT; |
||||
return(result); |
||||
} |
||||
|
||||
rIICCON |= 0x80; |
||||
|
||||
result = IIC_OK; |
||||
|
||||
switch (cmd_type) { |
||||
case IIC_WRITE: |
||||
if (addr && addr_len) { |
||||
rIICDS = chip; |
||||
/* send START */ |
||||
rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP; |
||||
i = 0; |
||||
while ((i < addr_len) && (result == IIC_OK)) { |
||||
result = WaitForXfer(); |
||||
rIICDS = addr[i]; |
||||
ReadWriteByte(); |
||||
i++; |
||||
} |
||||
i = 0; |
||||
while ((i < data_len) && (result == IIC_OK)) { |
||||
result = WaitForXfer(); |
||||
rIICDS = data[i]; |
||||
ReadWriteByte(); |
||||
i++; |
||||
} |
||||
} else { |
||||
rIICDS = chip; |
||||
/* send START */ |
||||
rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP; |
||||
i = 0; |
||||
while ((i < data_len) && (result = IIC_OK)) { |
||||
result = WaitForXfer(); |
||||
rIICDS = data[i]; |
||||
ReadWriteByte(); |
||||
i++; |
||||
} |
||||
} |
||||
|
||||
if (result == IIC_OK) |
||||
result = WaitForXfer(); |
||||
|
||||
/* send STOP */ |
||||
rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA; |
||||
ReadWriteByte(); |
||||
break; |
||||
|
||||
case IIC_READ: |
||||
if (addr && addr_len) { |
||||
rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA; |
||||
rIICDS = chip; |
||||
/* send START */ |
||||
rIICSTAT |= IIC_START_STOP; |
||||
result = WaitForXfer(); |
||||
if (IsACK()) { |
||||
i = 0; |
||||
while ((i < addr_len) && (result == IIC_OK)) { |
||||
rIICDS = addr[i]; |
||||
ReadWriteByte(); |
||||
result = WaitForXfer(); |
||||
i++; |
||||
} |
||||
|
||||
rIICDS = chip; |
||||
/* resend START */ |
||||
rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA | IIC_START_STOP; |
||||
ReadWriteByte(); |
||||
result = WaitForXfer(); |
||||
i = 0; |
||||
while ((i < data_len) && (result == IIC_OK)) { |
||||
/* disable ACK for final READ */ |
||||
if (i == data_len - 1) |
||||
rIICCON &= ~0x80; |
||||
ReadWriteByte(); |
||||
result = WaitForXfer(); |
||||
data[i] = rIICDS; |
||||
i++; |
||||
} |
||||
} else { |
||||
result = IIC_NACK; |
||||
} |
||||
|
||||
} else { |
||||
rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA; |
||||
rIICDS = chip; |
||||
/* send START */ |
||||
rIICSTAT |= IIC_START_STOP; |
||||
result = WaitForXfer(); |
||||
|
||||
if (IsACK()) { |
||||
i = 0; |
||||
while ((i < data_len) && (result == IIC_OK)) { |
||||
/* disable ACK for final READ */ |
||||
if (i == data_len - 1) |
||||
rIICCON &= ~0x80; |
||||
ReadWriteByte(); |
||||
result = WaitForXfer(); |
||||
data[i] = rIICDS; |
||||
i++; |
||||
} |
||||
} else { |
||||
result = IIC_NACK; |
||||
} |
||||
} |
||||
|
||||
/* send STOP */ |
||||
rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA; |
||||
ReadWriteByte(); |
||||
break; |
||||
|
||||
default: |
||||
printf( "i2c_transfer: bad call\n" ); |
||||
result = IIC_NOK; |
||||
break; |
||||
} |
||||
|
||||
return (result); |
||||
} |
||||
|
||||
int i2c_probe (uchar chip) |
||||
{ |
||||
uchar buf[1]; |
||||
|
||||
buf[0] = 0; |
||||
|
||||
/*
|
||||
* What is needed is to send the chip address and verify that the |
||||
* address was <ACK>ed (i.e. there was a chip at that address which |
||||
* drove the data line low). |
||||
*/ |
||||
return(i2c_transfer (IIC_READ, chip << 1, 0, 0, buf, 1) != IIC_OK); |
||||
} |
||||
|
||||
int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) |
||||
{ |
||||
uchar xaddr[4]; |
||||
int ret; |
||||
|
||||
if ( alen > 4 ) { |
||||
printf ("I2C read: addr len %d not supported\n", alen); |
||||
return 1; |
||||
} |
||||
|
||||
if ( alen > 0 ) { |
||||
xaddr[0] = (addr >> 24) & 0xFF; |
||||
xaddr[1] = (addr >> 16) & 0xFF; |
||||
xaddr[2] = (addr >> 8) & 0xFF; |
||||
xaddr[3] = addr & 0xFF; |
||||
} |
||||
|
||||
|
||||
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW |
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones |
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
||||
* address and the extra bits end up in the "chip address" |
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like |
||||
* four 256 byte chips. |
||||
* |
||||
* Note that we consider the length of the address field to |
||||
* still be one byte because the extra address bits are |
||||
* hidden in the chip address. |
||||
*/ |
||||
if( alen > 0 ) |
||||
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); |
||||
#endif |
||||
if( (ret = i2c_transfer(IIC_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { |
||||
printf( "I2c read: failed %d\n", ret); |
||||
return 1; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) |
||||
{ |
||||
uchar xaddr[4]; |
||||
|
||||
if ( alen > 4 ) { |
||||
printf ("I2C write: addr len %d not supported\n", alen); |
||||
return 1; |
||||
} |
||||
|
||||
if ( alen > 0 ) { |
||||
xaddr[0] = (addr >> 24) & 0xFF; |
||||
xaddr[1] = (addr >> 16) & 0xFF; |
||||
xaddr[2] = (addr >> 8) & 0xFF; |
||||
xaddr[3] = addr & 0xFF; |
||||
} |
||||
|
||||
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW |
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones |
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
||||
* address and the extra bits end up in the "chip address" |
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like |
||||
* four 256 byte chips. |
||||
* |
||||
* Note that we consider the length of the address field to |
||||
* still be one byte because the extra address bits are |
||||
* hidden in the chip address. |
||||
*/ |
||||
if( alen > 0 ) |
||||
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); |
||||
#endif |
||||
return (i2c_transfer(IIC_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); |
||||
} |
||||
|
||||
#endif /* CONFIG_HARD_I2C */ |
||||
|
||||
#endif /* CONFIG_DRIVER_S3C24X0_I2C */ |
||||
@ -0,0 +1,113 @@ |
||||
/*
|
||||
* FILE bitfield.h |
||||
* |
||||
* Version 1.1 |
||||
* Author Copyright (c) Marc A. Viredaz, 1998 |
||||
* DEC Western Research Laboratory, Palo Alto, CA |
||||
* Date April 1998 (April 1997) |
||||
* System Advanced RISC Machine (ARM) |
||||
* Language C or ARM Assembly |
||||
* Purpose Definition of macros to operate on bit fields. |
||||
*/ |
||||
|
||||
|
||||
|
||||
#ifndef __BITFIELD_H |
||||
#define __BITFIELD_H |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
#define UData(Data) ((unsigned long) (Data)) |
||||
#else |
||||
#define UData(Data) (Data) |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* MACRO: Fld |
||||
* |
||||
* Purpose |
||||
* The macro "Fld" encodes a bit field, given its size and its shift value |
||||
* with respect to bit 0. |
||||
* |
||||
* Note |
||||
* A more intuitive way to encode bit fields would have been to use their |
||||
* mask. However, extracting size and shift value information from a bit |
||||
* field's mask is cumbersome and might break the assembler (255-character |
||||
* line-size limit). |
||||
* |
||||
* Input |
||||
* Size Size of the bit field, in number of bits. |
||||
* Shft Shift value of the bit field with respect to bit 0. |
||||
* |
||||
* Output |
||||
* Fld Encoded bit field. |
||||
*/ |
||||
|
||||
#define Fld(Size, Shft) (((Size) << 16) + (Shft)) |
||||
|
||||
|
||||
/*
|
||||
* MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit |
||||
* |
||||
* Purpose |
||||
* The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return |
||||
* the size, shift value, mask, aligned mask, and first bit of a |
||||
* bit field. |
||||
* |
||||
* Input |
||||
* Field Encoded bit field (using the macro "Fld"). |
||||
* |
||||
* Output |
||||
* FSize Size of the bit field, in number of bits. |
||||
* FShft Shift value of the bit field with respect to bit 0. |
||||
* FMsk Mask for the bit field. |
||||
* FAlnMsk Mask for the bit field, aligned on bit 0. |
||||
* F1stBit First bit of the bit field. |
||||
*/ |
||||
|
||||
#define FSize(Field) ((Field) >> 16) |
||||
#define FShft(Field) ((Field) & 0x0000FFFF) |
||||
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) |
||||
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) |
||||
#define F1stBit(Field) (UData (1) << FShft (Field)) |
||||
|
||||
|
||||
/*
|
||||
* MACRO: FInsrt |
||||
* |
||||
* Purpose |
||||
* The macro "FInsrt" inserts a value into a bit field by shifting the |
||||
* former appropriately. |
||||
* |
||||
* Input |
||||
* Value Bit-field value. |
||||
* Field Encoded bit field (using the macro "Fld"). |
||||
* |
||||
* Output |
||||
* FInsrt Bit-field value positioned appropriately. |
||||
*/ |
||||
|
||||
#define FInsrt(Value, Field) \ |
||||
(UData (Value) << FShft (Field)) |
||||
|
||||
|
||||
/*
|
||||
* MACRO: FExtr |
||||
* |
||||
* Purpose |
||||
* The macro "FExtr" extracts the value of a bit field by masking and |
||||
* shifting it appropriately. |
||||
* |
||||
* Input |
||||
* Data Data containing the bit-field to be extracted. |
||||
* Field Encoded bit field (using the macro "Fld"). |
||||
* |
||||
* Output |
||||
* FExtr Bit-field value. |
||||
*/ |
||||
|
||||
#define FExtr(Data, Field) \ |
||||
((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) |
||||
|
||||
|
||||
#endif /* __BITFIELD_H */ |
||||
@ -0,0 +1,153 @@ |
||||
/*
|
||||
* linux/include/asm-arm/arch-pxa/hardware.h |
||||
* |
||||
* Author: Nicolas Pitre |
||||
* Created: Jun 15, 2001 |
||||
* Copyright: MontaVista Software Inc. |
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* Note: This file was taken from linux-2.4.19-rmk4-pxa1 |
||||
* |
||||
* - 2003/01/20 implementation specifics activated |
||||
* Robert Schwebel <r.schwebel@pengutronix.de> |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_H |
||||
#define __ASM_ARCH_HARDWARE_H |
||||
|
||||
#include <linux/config.h> |
||||
#include <asm/mach-types.h> |
||||
|
||||
|
||||
/*
|
||||
* These are statically mapped PCMCIA IO space for designs using it as a |
||||
* generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. |
||||
* The actual PCMCIA code is mapping required IO region at run time. |
||||
*/ |
||||
#define PCMCIA_IO_0_BASE 0xf6000000 |
||||
#define PCMCIA_IO_1_BASE 0xf7000000 |
||||
|
||||
|
||||
/*
|
||||
* We requires absolute addresses. |
||||
*/ |
||||
#define PCIO_BASE 0 |
||||
|
||||
/*
|
||||
* Workarounds for at least 2 errata so far require this. |
||||
* The mapping is set in mach-pxa/generic.c. |
||||
*/ |
||||
#define UNCACHED_PHYS_0 0xff000000 |
||||
#define UNCACHED_ADDR UNCACHED_PHYS_0 |
||||
|
||||
/*
|
||||
* Intel PXA internal I/O mappings: |
||||
* |
||||
* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff |
||||
* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff |
||||
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff |
||||
*/ |
||||
|
||||
/* FIXME: Only this does work for u-boot... find out why... [RS] */ |
||||
#define UBOOT_REG_FIX 1 |
||||
|
||||
#ifndef UBOOT_REG_FIX |
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) |
||||
#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) |
||||
|
||||
/*
|
||||
* This __REG() version gives the same results as the one above, except |
||||
* that we are fooling gcc somehow so it generates far better and smaller |
||||
* assembly code for access to contigous registers. It's a shame that gcc |
||||
* doesn't guess this by itself. |
||||
*/ |
||||
#include <asm/types.h> |
||||
typedef struct { volatile u32 offset[4096]; } __regbase; |
||||
# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] |
||||
# define __REG(x) __REGP(io_p2v(x)) |
||||
#endif |
||||
|
||||
/* Let's kick gcc's ass again... */ |
||||
# define __REG2(x,y) \ |
||||
( __builtin_constant_p(y) ? (__REG((x) + (y))) \
|
||||
: (*(volatile u32 *)((u32)&__REG(x) + (y))) ) |
||||
|
||||
# define __PREG(x) (io_v2p((u32)&(x))) |
||||
|
||||
#else |
||||
|
||||
# define __REG(x) io_p2v(x) |
||||
# define __PREG(x) io_v2p(x) |
||||
|
||||
#endif |
||||
#endif /* UBOOT_REG_FIX */ |
||||
|
||||
#ifdef UBOOT_REG_FIX |
||||
# undef io_p2v |
||||
# undef __REG |
||||
# ifndef __ASSEMBLY__ |
||||
# define io_p2v(PhAdd) (PhAdd) |
||||
# define __REG(x) (*((volatile u32 *)io_p2v(x))) |
||||
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) |
||||
# else |
||||
# define __REG(x) (x) |
||||
#endif /* UBOOT_REG_FIX */ |
||||
|
||||
#include "pxa-regs.h" |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
/*
|
||||
* GPIO edge detection for IRQs: |
||||
* IRQs are generated on Falling-Edge, Rising-Edge, or both. |
||||
* This must be called *before* the corresponding IRQ is registered. |
||||
* Use this instead of directly setting GRER/GFER. |
||||
*/ |
||||
#define GPIO_FALLING_EDGE 1 |
||||
#define GPIO_RISING_EDGE 2 |
||||
#define GPIO_BOTH_EDGES 3 |
||||
extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask ); |
||||
|
||||
/*
|
||||
* Handy routine to set GPIO alternate functions |
||||
*/ |
||||
extern void set_GPIO_mode( int gpio_mode ); |
||||
|
||||
/*
|
||||
* return current lclk frequency in units of 10kHz |
||||
*/ |
||||
extern unsigned int get_lclk_frequency_10khz(void); |
||||
|
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Implementation specifics |
||||
*/ |
||||
|
||||
#ifdef CONFIG_ARCH_LUBBOCK |
||||
#include "lubbock.h" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ARCH_PXA_IDP |
||||
#include "idp.h" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ARCH_PXA_CERF |
||||
#include "cerf.h" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ARCH_CSB226 |
||||
#include "csb226.h" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ARCH_INNOKOM |
||||
#include "innokom.h" |
||||
#endif |
||||
|
||||
#endif /* _ASM_ARCH_HARDWARE_H */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,209 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* Gary Jennejohn <gj@denx.de> |
||||
* David Mueller <d.mueller@elsoft.ch> |
||||
* |
||||
* Configuation settings for the MPL VCMA9 board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram |
||||
* so we MUST NOT initialize critical regs like mem-timing ... |
||||
*/ |
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ |
||||
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ |
||||
#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ |
||||
|
||||
/* input clock of PLL */ |
||||
#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ |
||||
|
||||
#define USE_920T_MMU 1 |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
/***********************************************************
|
||||
* Command definition |
||||
***********************************************************/ |
||||
#define CONFIG_COMMANDS \ |
||||
(CONFIG_CMD_DFL | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_BSP) |
||||
|
||||
/* this must be included after the definiton of CONFIG_COMMANDS */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
/***********************************************************
|
||||
* I2C stuff: |
||||
* the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at |
||||
* address 0x50 with 16bit addressing |
||||
***********************************************************/ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CFG_I2C_SPEED 100000 /* I2C speed */ |
||||
#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CFG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ |
||||
#define CFG_ENV_SIZE 0x800 /* 2KB should be more than enough */ |
||||
|
||||
#undef CFG_I2C_EEPROM_ADDR_OVERFLOW |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) |
||||
#define CFG_MALLOC_LEN (128 * 1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ |
||||
#define CS8900_BASE 0x20000300 |
||||
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ |
||||
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_IPADDR 10.0.0.110 |
||||
#define CONFIG_SERVERIP 10.0.0.1 |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||
/* what's this ? it's not used anywhere */ |
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "VCMA9 # " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ |
||||
#define CFG_ALT_MEMTEST |
||||
#define CFG_LOAD_ADDR 0x33000000 /* default load address */ |
||||
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
|
||||
/* we configure PWM Timer 4 to 1us ~ 1MHz */ |
||||
/*#define CFG_HZ 1000000 */ |
||||
#define CFG_HZ 1562500 |
||||
|
||||
/* valid baudrates */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ |
||||
#if 0 |
||||
#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ |
||||
#endif |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#ifdef CONFIG_AMD_LV800 |
||||
#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ |
||||
#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ |
||||
#endif |
||||
#ifdef CONFIG_AMD_LV400 |
||||
#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ |
||||
#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ |
||||
#endif |
||||
|
||||
/* timeout values are in ticks */ |
||||
#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#if 0 |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
#endif |
||||
|
||||
#define MULTI_PURPOSE_SOCKET_ADDR 0 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,203 @@ |
||||
/*
|
||||
* (C) Copyright 2001, 2002, 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* Keith Outwater, keith_outwater@mvis.com` |
||||
* Steven Scholz, steven.scholz@imc-berlin.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) |
||||
* DS1307 Real Time Clock (RTC). |
||||
* |
||||
* based on ds1337.c |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <rtc.h> |
||||
#include <i2c.h> |
||||
|
||||
#if defined(CONFIG_RTC_DS1307) && (CONFIG_COMMANDS & CFG_CMD_DATE) |
||||
|
||||
/*---------------------------------------------------------------------*/ |
||||
#undef DEBUG_RTC |
||||
|
||||
#ifdef DEBUG_RTC |
||||
#define DEBUGR(fmt,args...) printf(fmt ,##args) |
||||
#else |
||||
#define DEBUGR(fmt,args...) |
||||
#endif |
||||
/*---------------------------------------------------------------------*/ |
||||
|
||||
#ifndef CFG_I2C_RTC_ADDR |
||||
# define CFG_I2C_RTC_ADDR 0x68 |
||||
#endif |
||||
|
||||
#if CFG_I2C_SPEED > 100000 |
||||
# error The DS1307 is specified only up to 100kHz! |
||||
#endif |
||||
|
||||
/*
|
||||
* RTC register addresses |
||||
*/ |
||||
#define RTC_SEC_REG_ADDR 0x00 |
||||
#define RTC_MIN_REG_ADDR 0x01 |
||||
#define RTC_HR_REG_ADDR 0x02 |
||||
#define RTC_DAY_REG_ADDR 0x03 |
||||
#define RTC_DATE_REG_ADDR 0x04 |
||||
#define RTC_MON_REG_ADDR 0x05 |
||||
#define RTC_YR_REG_ADDR 0x06 |
||||
#define RTC_CTL_REG_ADDR 0x07 |
||||
|
||||
#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ |
||||
|
||||
#define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ |
||||
#define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ |
||||
#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ |
||||
#define RTC_CTL_BIT_OUT 0x80 /* Output Control */ |
||||
|
||||
static uchar rtc_read (uchar reg); |
||||
static void rtc_write (uchar reg, uchar val); |
||||
static uchar bin2bcd (unsigned int n); |
||||
static unsigned bcd2bin (uchar c); |
||||
|
||||
/*
|
||||
* Get the current time from the RTC |
||||
*/ |
||||
void rtc_get (struct rtc_time *tmp) |
||||
{ |
||||
uchar sec, min, hour, mday, wday, mon, year; |
||||
|
||||
sec = rtc_read (RTC_SEC_REG_ADDR); |
||||
min = rtc_read (RTC_MIN_REG_ADDR); |
||||
hour = rtc_read (RTC_HR_REG_ADDR); |
||||
wday = rtc_read (RTC_DAY_REG_ADDR); |
||||
mday = rtc_read (RTC_DATE_REG_ADDR); |
||||
mon = rtc_read (RTC_MON_REG_ADDR); |
||||
year = rtc_read (RTC_YR_REG_ADDR); |
||||
|
||||
DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " |
||||
"hr: %02x min: %02x sec: %02x\n", |
||||
year, mon, mday, wday, hour, min, sec); |
||||
|
||||
if (sec & RTC_SEC_BIT_CH) { |
||||
printf ("### Warning: RTC oscillator has stopped\n"); |
||||
/* clear the CH flag */ |
||||
rtc_write (RTC_SEC_REG_ADDR, |
||||
rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); |
||||
} |
||||
|
||||
tmp->tm_sec = bcd2bin (sec & 0x7F); |
||||
tmp->tm_min = bcd2bin (min & 0x7F); |
||||
tmp->tm_hour = bcd2bin (hour & 0x3F); |
||||
tmp->tm_mday = bcd2bin (mday & 0x3F); |
||||
tmp->tm_mon = bcd2bin (mon & 0x1F); |
||||
tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000); |
||||
tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); |
||||
tmp->tm_yday = 0; |
||||
tmp->tm_isdst= 0; |
||||
|
||||
DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
||||
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
||||
tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Set the RTC |
||||
*/ |
||||
void rtc_set (struct rtc_time *tmp) |
||||
{ |
||||
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
||||
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
||||
tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
||||
|
||||
if (tmp->tm_year < 1970 || tmp->tm_year > 2069) |
||||
printf("WARNING: year should be between 1970 and 2069!\n"); |
||||
|
||||
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); |
||||
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); |
||||
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); |
||||
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); |
||||
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); |
||||
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); |
||||
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Reset the RTC. We setting the date back to 1970-01-01.
|
||||
* We also enable the oscillator output on the SQW/OUT pin and program
|
||||
* it for 32,768 Hz output. Note that according to the datasheet, turning |
||||
* on the square wave output increases the current drain on the backup |
||||
* battery to something between 480nA and 800nA. |
||||
*/ |
||||
void rtc_reset (void) |
||||
{ |
||||
struct rtc_time tmp; |
||||
|
||||
rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */ |
||||
rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0); |
||||
|
||||
tmp.tm_year = 1970; |
||||
tmp.tm_mon = 1; |
||||
tmp.tm_mday= 1; |
||||
tmp.tm_hour = 0; |
||||
tmp.tm_min = 0; |
||||
tmp.tm_sec = 0; |
||||
|
||||
rtc_set(&tmp); |
||||
|
||||
printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", |
||||
tmp.tm_year, tmp.tm_mon, tmp.tm_mday, |
||||
tmp.tm_hour, tmp.tm_min, tmp.tm_sec); |
||||
|
||||
return; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Helper functions |
||||
*/ |
||||
|
||||
static |
||||
uchar rtc_read (uchar reg) |
||||
{ |
||||
return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); |
||||
} |
||||
|
||||
|
||||
static void rtc_write (uchar reg, uchar val) |
||||
{ |
||||
i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); |
||||
} |
||||
|
||||
static unsigned bcd2bin (uchar n) |
||||
{ |
||||
return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); |
||||
} |
||||
|
||||
static unsigned char bin2bcd (unsigned int n) |
||||
{ |
||||
return (((n / 10) << 4) | (n % 10)); |
||||
} |
||||
|
||||
#endif /* CONFIG_RTC_DS1307 && (CFG_COMMANDS & CFG_CMD_DATE) */ |
||||
Loading…
Reference in new issue