Tom Rini
9 years ago
commit
1cb9cb3ec0
@ -0,0 +1,212 @@ |
||||
/* |
||||
* dts file for Xilinx ZynqMP zc1751-xm018-dc4 |
||||
* |
||||
* (C) Copyright 2015 - 2016, Xilinx, Inc. |
||||
* |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include "zynqmp.dtsi" |
||||
#include "zynqmp-clk.dtsi" |
||||
|
||||
/ { |
||||
model = "ZynqMP zc1751-xm018-dc4"; |
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; |
||||
|
||||
aliases { |
||||
can0 = &can0; |
||||
can1 = &can1; |
||||
ethernet0 = &gem0; |
||||
ethernet1 = &gem1; |
||||
ethernet2 = &gem2; |
||||
ethernet3 = &gem3; |
||||
gpio0 = &gpio; |
||||
i2c0 = &i2c0; |
||||
i2c1 = &i2c1; |
||||
rtc0 = &rtc; |
||||
serial0 = &uart0; |
||||
serial1 = &uart1; |
||||
spi0 = &qspi; |
||||
}; |
||||
|
||||
chosen { |
||||
bootargs = "earlycon"; |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
memory { |
||||
device_type = "memory"; |
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
||||
}; |
||||
}; |
||||
|
||||
&can0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&can1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
/* fpd_dma clk 667MHz, lpd_dma 500MHz */ |
||||
&fpd_dma_chan1 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
xlnx,overfetch; /* for testing purpose */ |
||||
xlnx,ratectrl = <0>; /* for testing purpose */ |
||||
xlnx,src-issue = <31>; |
||||
}; |
||||
|
||||
&fpd_dma_chan2 { |
||||
status = "okay"; |
||||
xlnx,ratectrl = <100>; /* for testing purpose */ |
||||
xlnx,src-issue = <4>; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan3 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan4 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan5 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan6 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan7 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan8 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&lpd_dma_chan1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&lpd_dma_chan2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&lpd_dma_chan3 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&lpd_dma_chan4 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&lpd_dma_chan5 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&lpd_dma_chan6 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&lpd_dma_chan7 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&lpd_dma_chan8 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&xlnx_dp { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&xlnx_dpdma { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gem0 { |
||||
status = "okay"; |
||||
local-mac-address = [00 0a 35 00 02 90]; |
||||
phy-mode = "rgmii-id"; |
||||
phy-handle = <ðernet_phy0>; |
||||
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ |
||||
reg = <0>; |
||||
}; |
||||
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ |
||||
reg = <7>; |
||||
}; |
||||
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ |
||||
reg = <3>; |
||||
}; |
||||
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ |
||||
reg = <8>; |
||||
}; |
||||
}; |
||||
|
||||
&gem1 { |
||||
status = "okay"; |
||||
local-mac-address = [00 0a 35 00 02 91]; |
||||
phy-mode = "rgmii-id"; |
||||
phy-handle = <ðernet_phy7>; |
||||
}; |
||||
|
||||
&gem2 { |
||||
status = "okay"; |
||||
local-mac-address = [00 0a 35 00 02 92]; |
||||
phy-mode = "rgmii-id"; |
||||
phy-handle = <ðernet_phy3>; |
||||
}; |
||||
|
||||
&gem3 { |
||||
status = "okay"; |
||||
local-mac-address = [00 0a 35 00 02 93]; |
||||
phy-mode = "rgmii-id"; |
||||
phy-handle = <ðernet_phy8>; |
||||
}; |
||||
|
||||
&gpio { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpu { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c0 { |
||||
clock-frequency = <400000>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c1 { |
||||
clock-frequency = <400000>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&rtc { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&watchdog0 { |
||||
status = "okay"; |
||||
}; |
||||
@ -1,16 +1,20 @@ |
||||
#
|
||||
# (C) Copyright 2007 Michal Simek
|
||||
# (C) Copyright 2007 - 2016 Michal Simek
|
||||
#
|
||||
# Michal SIMEK <monstr@monstr.eu>
|
||||
# Michal SIMEK <monstr@monstr.eu>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# CAUTION: This file is a faked configuration !!!
|
||||
# There is no real target for the microblaze-generic
|
||||
# configuration. You have to replace this file with
|
||||
# the generated file from your Xilinx design flow.
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
|
||||
PLATFORM_CPPFLAGS += -mno-xl-soft-div
|
||||
PLATFORM_CPPFLAGS += -mxl-barrel-shift
|
||||
CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
|
||||
|
||||
# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
|
||||
CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high |
||||
CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
|
||||
CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
|
||||
CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
|
||||
CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
|
||||
|
||||
CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
|
||||
|
||||
PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
|
||||
|
||||
@ -0,0 +1,43 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4" |
||||
CONFIG_ARCH_ZYNQMP=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000 |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_SYS_TEXT_BASE=0x8000000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SPL_LOAD_FIT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="ZynqMP> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_TIMER=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_CLK=y |
||||
CONFIG_SPL_CLK=y |
||||
CONFIG_SYS_I2C_CADENCE=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_ZYNQ_SDHCI=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ZYNQ_GEM=y |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_DEBUG_UART_ZYNQ=y |
||||
CONFIG_DEBUG_UART_BASE=0xff000000 |
||||
CONFIG_DEBUG_UART_CLOCK=100000000 |
||||
CONFIG_DEBUG_UART_ANNOUNCE=y |
||||
@ -0,0 +1,17 @@ |
||||
/*
|
||||
* Configuration for Xilinx ZynqMP zc1751 XM018 DC4 |
||||
* |
||||
* (C) Copyright 2015 Xilinx, Inc. |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H |
||||
#define __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H |
||||
|
||||
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm018 dc4" |
||||
|
||||
#include <configs/xilinx_zynqmp.h> |
||||
|
||||
#endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */ |
||||
Loading…
Reference in new issue