Wolfgang Denk
16 years ago
commit
1ea0823786
@ -0,0 +1,6 @@ |
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#ifndef __BOARD_MPC837XEMDS_PCI_H |
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#define __BOARD_MPC837XEMDS_PCI_H |
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|
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extern void ft_pcie_fixup(void *blob, bd_t *bd); |
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#endif /* __BOARD_MPC837XEMDS_PCI_H */ |
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@ -0,0 +1,50 @@ |
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#
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# (C) Copyright 2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
|
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o sdram.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,13 @@ |
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ifndef NAND_SPL |
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp |
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endif |
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|
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ifndef TEXT_BASE |
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TEXT_BASE = 0x00100000
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endif |
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|
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ifdef CONFIG_NAND_LP |
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PAD_TO = 0xFFF20000
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else |
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PAD_TO = 0xFFF04000
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endif |
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@ -0,0 +1,193 @@ |
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007 |
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* Copyright (C) Sheldon Instruments, Inc. 2008 |
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* |
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* Author: Ron Madrid <info@sheldoninst.com> |
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* |
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* (C) Copyright 2006 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <mpc83xx.h> |
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#include <spd_sdram.h> |
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#include <asm/bitops.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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#include <asm/mmu.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static long fixed_sdram(void); |
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#if defined(CONFIG_NAND_SPL) |
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void si_wait_i2c(void) |
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{ |
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
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while (!(__raw_readb(&im->i2c[0].sr) & 0x02)) |
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; |
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__raw_writeb(0x00, &im->i2c[0].sr); |
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sync(); |
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return; |
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} |
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void si_read_i2c(u32 lbyte, int count, u8 *buffer) |
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{ |
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
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u32 i; |
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u8 chip = 0x50 << 1; /* boot sequencer I2C */ |
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u32 ubyte = (lbyte & 0xff00) >> 8; |
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lbyte &= 0xff; |
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/*
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* Set up controller |
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*/ |
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__raw_writeb(0x3f, &im->i2c[0].fdr); |
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__raw_writeb(0x00, &im->i2c[0].adr); |
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__raw_writeb(0x00, &im->i2c[0].sr); |
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__raw_writeb(0x00, &im->i2c[0].dr); |
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while (__raw_readb(&im->i2c[0].sr) & 0x20) |
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; |
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|
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/*
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* Writing address to device |
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*/ |
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__raw_writeb(0xb0, &im->i2c[0].cr); |
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sync(); |
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__raw_writeb(chip, &im->i2c[0].dr); |
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si_wait_i2c(); |
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|
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__raw_writeb(0xb0, &im->i2c[0].cr); |
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sync(); |
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__raw_writeb(ubyte, &im->i2c[0].dr); |
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si_wait_i2c(); |
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__raw_writeb(lbyte, &im->i2c[0].dr); |
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si_wait_i2c(); |
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__raw_writeb(0xb4, &im->i2c[0].cr); |
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sync(); |
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__raw_writeb(chip + 1, &im->i2c[0].dr); |
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si_wait_i2c(); |
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__raw_writeb(0xa0, &im->i2c[0].cr); |
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sync(); |
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/*
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* Dummy read |
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*/ |
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__raw_readb(&im->i2c[0].dr); |
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si_wait_i2c(); |
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/*
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* Read actual data |
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*/ |
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for (i = 0; i < count; i++) |
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{ |
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if (i == (count - 2)) /* Reached next to last byte, No ACK */ |
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__raw_writeb(0xa8, &im->i2c[0].cr); |
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if (i == (count - 1)) /* Reached last byte, STOP */ |
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__raw_writeb(0x88, &im->i2c[0].cr); |
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/* Read byte of data */ |
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buffer[i] = __raw_readb(&im->i2c[0].dr); |
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if (i == (count - 1)) |
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break; |
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si_wait_i2c(); |
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} |
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return; |
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} |
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#endif /* CONFIG_NAND_SPL */ |
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phys_size_t initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
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volatile fsl_lbus_t *lbc= &im->lbus; |
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u32 msize; |
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if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar); |
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msize = fixed_sdram(); |
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/* Local Bus setup lbcr and mrtpr */ |
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__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr); |
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__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr); |
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sync(); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return (msize * 1024 * 1024); |
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} |
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|
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/*************************************************************************
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* fixed sdram init -- reads values from boot sequencer I2C |
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************************************************************************/ |
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static long fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
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u32 msizelog2, msize = 1; |
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#if defined(CONFIG_NAND_SPL) |
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u32 i; |
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const u8 bytecount = 135; |
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u8 buffer[bytecount]; |
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u32 addr, data; |
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si_read_i2c(0, bytecount, buffer); |
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for (i = 18; i < bytecount; i += 7){ |
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addr = (u32)buffer[i]; |
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addr <<= 8; |
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addr |= (u32)buffer[i + 1]; |
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addr <<= 2; |
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data = (u32)buffer[i + 2]; |
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data <<= 8; |
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data |= (u32)buffer[i + 3]; |
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data <<= 8; |
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data |= (u32)buffer[i + 4]; |
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data <<= 8; |
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data |= (u32)buffer[i + 5]; |
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__raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr)); |
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} |
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sync(); |
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/* enable DDR controller */ |
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__raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg); |
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#endif /* (CONFIG_NAND_SPL) */ |
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msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1); |
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msize <<= (msizelog2 - 20); |
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return msize; |
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} |
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@ -0,0 +1,134 @@ |
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007 |
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* Copyright (C) Sheldon Instruments, Inc. 2008 |
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* |
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* Author: Ron Madrid <info@sheldoninst.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <libfdt.h> |
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#include <pci.h> |
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#include <mpc83xx.h> |
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#include <ns16550.h> |
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#include <nand.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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puts("Board: Sheldon Instruments SIMPC8313\n"); |
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return 0; |
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} |
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#ifndef CONFIG_NAND_SPL |
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static struct pci_region pci_regions[] = { |
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{ |
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bus_start: CONFIG_SYS_PCI1_MEM_BASE, |
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS, |
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size: CONFIG_SYS_PCI1_MEM_SIZE, |
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
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}, |
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{ |
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE, |
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, |
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size: CONFIG_SYS_PCI1_MMIO_SIZE, |
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flags: PCI_REGION_MEM |
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}, |
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{ |
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bus_start: CONFIG_SYS_PCI1_IO_BASE, |
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phys_start: CONFIG_SYS_PCI1_IO_PHYS, |
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size: CONFIG_SYS_PCI1_IO_SIZE, |
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flags: PCI_REGION_IO |
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} |
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}; |
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void pci_init_board(void) |
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{ |
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; |
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; |
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw; |
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struct pci_region *reg[] = { pci_regions }; |
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int warmboot; |
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/* Enable all 3 PCI_CLK_OUTPUTs. */ |
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clk->occr |= 0xe0000000; |
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|
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/*
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* Configure PCI Local Access Windows |
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*/ |
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; |
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; |
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; |
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; |
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warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; |
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mpc83xx_pci_init(1, reg, warmboot); |
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} |
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|
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/*
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* Miscellaneous late-boot configurations |
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*/ |
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int misc_init_r(void) |
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{ |
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int rc = 0; |
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return rc; |
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} |
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|
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#if defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup(blob, bd); |
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#ifdef CONFIG_PCI |
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ft_pci_setup(blob, bd); |
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#endif |
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} |
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#endif |
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#else /* CONFIG_NAND_SPL */ |
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void board_init_f(ulong bootflag) |
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{ |
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NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), |
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); |
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puts("NAND boot... "); |
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init_timebase(); |
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initdram(0); |
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, |
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CONFIG_SYS_NAND_U_BOOT_RELOC); |
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} |
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|
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void board_init_r(gd_t *gd, ulong dest_addr) |
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{ |
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nand_boot(); |
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} |
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|
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void putc(char c) |
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{ |
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if (gd->flags & GD_FLG_SILENT) |
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return; |
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|
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if (c == '\n') |
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); |
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|
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); |
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} |
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#endif |
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@ -0,0 +1,314 @@ |
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/*
|
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* Copyright (C) 2007-2009 Freescale Semiconductor, Inc. |
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* Copyright (C) 2008-2009 MontaVista Software, Inc. |
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* |
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* Authors: Tony Li <tony.li@freescale.com> |
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* Anton Vorontsov <avorontsov@ru.mvista.com> |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <pci.h> |
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#include <mpc83xx.h> |
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#include <asm/io.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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#define PCIE_MAX_BUSES 2 |
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|
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#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES |
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|
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static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) |
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{ |
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int bus = PCI_BUS(dev) - hose->first_busno; |
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
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pex83xx_t *pex = &immr->pciexp[bus]; |
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struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; |
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u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); |
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u32 dev_base = bus << 24 | devfn << 16; |
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|
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if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK) |
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return -1; |
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/*
|
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* Workaround for the HW bug: for Type 0 configure transactions the |
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* PCI-E controller does not check the device number bits and just |
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* assumes that the device number bits are 0. |
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*/ |
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if (devfn & 0xf8) |
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return -1; |
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|
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out_le32(&out_win->tarl, dev_base); |
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return 0; |
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} |
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|
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#define cfg_read(val, addr, type, op) \ |
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do { *val = op((type)(addr)); } while (0) |
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#define cfg_write(val, addr, type, op) \ |
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do { op((type *)(addr), (val)); } while (0) |
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|
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#define PCIE_OP(rw, size, type, op) \ |
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static int pcie_##rw##_config_##size(struct pci_controller *hose, \
|
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pci_dev_t dev, int offset, \
|
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type val) \
|
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{ \
|
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int ret; \
|
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\
|
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ret = mpc83xx_pcie_remap_cfg(hose, dev); \
|
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if (ret) \
|
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return ret; \
|
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cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
|
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return 0; \
|
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} |
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|
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PCIE_OP(read, byte, u8 *, in_8) |
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PCIE_OP(read, word, u16 *, in_le16) |
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PCIE_OP(read, dword, u32 *, in_le32) |
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PCIE_OP(write, byte, u8, out_8) |
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PCIE_OP(write, word, u16, out_le16) |
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PCIE_OP(write, dword, u32, out_le32) |
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|
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static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, |
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u8 link) |
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{ |
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extern void disable_addr_trans(void); /* start.S */ |
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static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; |
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static int max_bus; |
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struct pci_controller *hose = &pcie_hose[bus]; |
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int i; |
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|
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/*
|
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* There are no spare BATs to remap all PCI-E windows for U-Boot, so |
||||
* disable translations. In general, this is not great solution, and |
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* that's why we don't register PCI-E hoses by default. |
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*/ |
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disable_addr_trans(); |
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|
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for (i = 0; i < 2; i++, reg++) { |
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if (reg->size == 0) |
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break; |
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|
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hose->regions[i] = *reg; |
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hose->region_count++; |
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} |
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|
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i = hose->region_count++; |
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hose->regions[i].bus_start = 0; |
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hose->regions[i].phys_start = 0; |
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hose->regions[i].size = gd->ram_size; |
||||
hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; |
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|
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i = hose->region_count++; |
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hose->regions[i].bus_start = CONFIG_SYS_IMMR; |
||||
hose->regions[i].phys_start = CONFIG_SYS_IMMR; |
||||
hose->regions[i].size = 0x100000; |
||||
hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; |
||||
|
||||
hose->first_busno = max_bus; |
||||
hose->last_busno = 0xff; |
||||
|
||||
if (bus == 0) |
||||
hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE; |
||||
else |
||||
hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE; |
||||
|
||||
pci_set_ops(hose, |
||||
pcie_read_config_byte, |
||||
pcie_read_config_word, |
||||
pcie_read_config_dword, |
||||
pcie_write_config_byte, |
||||
pcie_write_config_word, |
||||
pcie_write_config_dword); |
||||
|
||||
if (!link) |
||||
hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK; |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
#ifdef CONFIG_PCI_SCAN_SHOW |
||||
printf("PCI: Bus Dev VenId DevId Class Int\n"); |
||||
#endif |
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
max_bus = hose->last_busno + 1; |
||||
} |
||||
|
||||
#else |
||||
|
||||
static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, |
||||
u8 link) {} |
||||
|
||||
#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */ |
||||
|
||||
static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) |
||||
{ |
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
||||
pex83xx_t *pex = &immr->pciexp[bus]; |
||||
struct pex_outbound_window *out_win; |
||||
struct pex_inbound_window *in_win; |
||||
void *hose_cfg_base; |
||||
unsigned int ram_sz; |
||||
unsigned int barl; |
||||
unsigned int tar; |
||||
u16 reg16; |
||||
int i; |
||||
|
||||
/* Enable pex csb bridge inbound & outbound transactions */ |
||||
out_le32(&pex->bridge.pex_csb_ctrl, |
||||
in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE | |
||||
PEX_CSB_CTRL_IBPIOE); |
||||
|
||||
/* Enable bridge outbound */ |
||||
out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE | |
||||
PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE | |
||||
PEX_CSB_OBCTRL_CFGWE); |
||||
|
||||
out_win = &pex->bridge.pex_outbound_win[0]; |
||||
if (bus) { |
||||
out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | |
||||
CONFIG_SYS_PCIE2_CFG_SIZE); |
||||
out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE); |
||||
} else { |
||||
out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | |
||||
CONFIG_SYS_PCIE1_CFG_SIZE); |
||||
out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE); |
||||
} |
||||
out_le32(&out_win->tarl, 0); |
||||
out_le32(&out_win->tarh, 0); |
||||
|
||||
for (i = 0; i < 2; i++, reg++) { |
||||
u32 ar; |
||||
|
||||
if (reg->size == 0) |
||||
break; |
||||
|
||||
out_win = &pex->bridge.pex_outbound_win[i + 1]; |
||||
out_le32(&out_win->bar, reg->phys_start); |
||||
out_le32(&out_win->tarl, reg->bus_start); |
||||
out_le32(&out_win->tarh, 0); |
||||
ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE); |
||||
if (reg->flags & PCI_REGION_IO) |
||||
ar |= PEX_OWAR_TYPE_IO; |
||||
else |
||||
ar |= PEX_OWAR_TYPE_MEM; |
||||
out_le32(&out_win->ar, ar); |
||||
} |
||||
|
||||
out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE); |
||||
|
||||
ram_sz = gd->ram_size; |
||||
barl = 0; |
||||
tar = 0; |
||||
i = 0; |
||||
while (ram_sz > 0) { |
||||
in_win = &pex->bridge.pex_inbound_win[i]; |
||||
out_le32(&in_win->barl, barl); |
||||
out_le32(&in_win->barh, 0x0); |
||||
out_le32(&in_win->tar, tar); |
||||
if (ram_sz >= 0x10000000) { |
||||
/* The maxium windows size is 256M */ |
||||
out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | |
||||
PEX_IWAR_TYPE_PF | 0x0FFFF000); |
||||
barl += 0x10000000; |
||||
tar += 0x10000000; |
||||
ram_sz -= 0x10000000; |
||||
} else { |
||||
/* The UM is not clear here.
|
||||
* So, round up to even Mb boundary */ |
||||
|
||||
ram_sz = ram_sz >> (20 + |
||||
((ram_sz & 0xFFFFF) ? 1 : 0)); |
||||
if (!(ram_sz % 2)) |
||||
ram_sz -= 1; |
||||
out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | |
||||
PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000); |
||||
ram_sz = 0; |
||||
} |
||||
i++; |
||||
} |
||||
|
||||
in_win = &pex->bridge.pex_inbound_win[i]; |
||||
out_le32(&in_win->barl, CONFIG_SYS_IMMR); |
||||
out_le32(&in_win->barh, 0); |
||||
out_le32(&in_win->tar, CONFIG_SYS_IMMR); |
||||
out_le32(&in_win->ar, PEX_IWAR_EN | |
||||
PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M); |
||||
|
||||
/* Enable the host virtual INTX interrupts */ |
||||
out_le32(&pex->bridge.pex_int_axi_misc_enb, |
||||
in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0); |
||||
|
||||
/* Hose configure header is memory-mapped */ |
||||
hose_cfg_base = (void *)pex; |
||||
|
||||
get_clocks(); |
||||
/* Configure the PCIE controller core clock ratio */ |
||||
out_le32(hose_cfg_base + PEX_GCLK_RATIO, |
||||
(((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16) |
||||
/ 333); |
||||
udelay(1000000); |
||||
|
||||
/* Do Type 1 bridge configuration */ |
||||
out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0); |
||||
out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1); |
||||
out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255); |
||||
|
||||
/*
|
||||
* Write to Command register |
||||
*/ |
||||
reg16 = in_le16(hose_cfg_base + PCI_COMMAND); |
||||
reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO | |
||||
PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
||||
out_le16(hose_cfg_base + PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
out_le16(hose_cfg_base + PCI_STATUS, 0xffff); |
||||
out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80); |
||||
out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
printf("PCIE%d: ", bus); |
||||
|
||||
reg16 = in_le16(hose_cfg_base + PCI_LTSSM); |
||||
if (reg16 >= PCI_LTSSM_L0) |
||||
printf("link\n"); |
||||
else |
||||
printf("No link\n"); |
||||
|
||||
mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0); |
||||
} |
||||
|
||||
/*
|
||||
* The caller must have already set SCCR, SERDES and the PCIE_LAW BARs |
||||
* must have been set to cover all of the requested regions. |
||||
*/ |
||||
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot) |
||||
{ |
||||
int i; |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal. |
||||
* Power on to RST high must be at least 100 ms as per PCI spec. |
||||
* On warm boots only 1 ms is required. |
||||
*/ |
||||
udelay(warmboot ? 1000 : 100000); |
||||
|
||||
for (i = 0; i < num_buses; i++) |
||||
mpc83xx_pcie_init_bus(i, reg[i]); |
||||
} |
||||
@ -0,0 +1,80 @@ |
||||
Sheldon Instruments SIMPC8313 Board |
||||
----------------------------------------- |
||||
|
||||
1. Board Switches and Jumpers |
||||
|
||||
S2 is used to set CFG_RESET_SOURCE. |
||||
|
||||
To boot the image in Large page NAND flash, use these DIP |
||||
switch settings for S2: |
||||
|
||||
+----------+ ON |
||||
| * * **** | |
||||
| * * | |
||||
+----------+ |
||||
12345678 |
||||
|
||||
To boot the image in Small page NAND flash, use these DIP |
||||
switch settings for S2: |
||||
|
||||
+----------+ ON |
||||
| *** **** | |
||||
| * | |
||||
+----------+ |
||||
12345678 |
||||
(where the '*' indicates the position of the tab of the switch.) |
||||
|
||||
2. Memory Map |
||||
The memory map looks like this: |
||||
|
||||
0x0000_0000 0x1fff_ffff DDR 512M |
||||
0x8000_0000 0x8fff_ffff PCI MEM 256M |
||||
0x9000_0000 0x9fff_ffff PCI_MMIO 256M |
||||
0xe000_0000 0xe00f_ffff IMMR 1M |
||||
0xe200_0000 0xe20f_ffff PCI IO 16M |
||||
0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K |
||||
or |
||||
0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K |
||||
0xff00_0000 0xff00_7fff FPGA (CS1) 1M |
||||
|
||||
3. Compilation |
||||
|
||||
Assuming you're using BASH (or similar) as your shell: |
||||
|
||||
export CROSS_COMPILE=your-cross-compiler-prefix- |
||||
make distclean |
||||
make SIMPC8313_LP_config |
||||
(or make SIMPC8313_SP_config, depending on the page size |
||||
of your NAND flash) |
||||
make |
||||
|
||||
4. Downloading and Flashing Images |
||||
|
||||
4.1 Reflash U-boot Image using U-boot |
||||
|
||||
=>run update_uboot |
||||
|
||||
You may want to try |
||||
=>tftp $loadaddr $uboot |
||||
first, to make sure that the TFTP load will succeed before it |
||||
goes ahead and wipes out your current firmware. And of course, |
||||
if the new u-boot doesn't boot, you can plug the board into |
||||
your PCI slot and with the supplied driver and sample app |
||||
you can reburn a working u-boot. |
||||
|
||||
4.2 Downloading and Booting Linux Kernel |
||||
|
||||
Ensure that all networking-related environment variables are set |
||||
properly (including ipaddr, serverip, gatewayip (if needed), |
||||
netmask, ethaddr, eth1addr, fdtfile, and bootfile). |
||||
|
||||
=>tftp $loadaddr uImage |
||||
=>nand write $loadaddr kernel $filesize |
||||
=>tftp $loadaddr $fdtfile |
||||
=>nand write $loadaddr 7e0000 1800 |
||||
|
||||
=>boot |
||||
|
||||
5 Notes |
||||
|
||||
The console baudrate for SIMPC8313 is 115200bps. |
||||
@ -0,0 +1,544 @@ |
||||
/*
|
||||
* Copyright (C) Sheldon Instruments, Inc. 2008 |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
/*
|
||||
* simpc8313 board configuration file |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_NAND_U_BOOT |
||||
|
||||
#define CONFIG_E300 1 |
||||
#define CONFIG_MPC83XX 1 |
||||
#define CONFIG_MPC831X 1 |
||||
#define CONFIG_MPC8313 1 |
||||
|
||||
#define CONFIG_PCI |
||||
#define CONFIG_83XX_GENERIC_PCI |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* On-board devices |
||||
* |
||||
* TSEC1 is Marvell PHY 88E1118 |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_33MHZ |
||||
|
||||
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN |
||||
|
||||
#define CONFIG_SYS_IMMR 0xE0000000 |
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
||||
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00001000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x07f00000 |
||||
|
||||
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
||||
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
||||
|
||||
/*
|
||||
* Device configurations |
||||
*/ |
||||
#define CONFIG_TSEC1 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
|
||||
#define CONFIG_VERY_BIG_RAM |
||||
#define CONFIG_MAX_MEM_MAPPED (512 << 20) |
||||
|
||||
#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \ |
||||
| DDRCDR_PZ_NOMZ \
|
||||
| DDRCDR_NZ_NOMZ \
|
||||
| DDRCDR_M_ODR ) |
||||
/* 0x73000002 TODO ODR & DRN ? */ |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if !defined(CONFIG_NAND_SPL) |
||||
#define CONFIG_SYS_RAMBOOT |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs |
||||
*/ |
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) |
||||
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ |
||||
| (0xFF << LBCR_BMT_SHIFT) \
|
||||
| 0xF ) /* 0x0004ff0f */ |
||||
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ |
||||
|
||||
/* drivers/mtd/nand/nand.c */ |
||||
#ifdef CONFIG_NAND_SPL |
||||
#define CONFIG_SYS_NAND_BASE 0xFFF00000 |
||||
#else |
||||
#define CONFIG_SYS_NAND_BASE 0xE2800000 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND 1 |
||||
#define CONFIG_NAND_FSL_ELBC 1 |
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) |
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 |
||||
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 |
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 |
||||
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V ) /* valid */ |
||||
|
||||
#ifdef CONFIG_NAND_SP |
||||
#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ |
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR ) |
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */ |
||||
#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */ |
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ |
||||
#define NAND_CACHE_PAGES 32 |
||||
#elif defined(CONFIG_NAND_LP) |
||||
#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \ |
||||
| OR_FCM_PGS \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR ) |
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */ |
||||
#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */ |
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ |
||||
#define NAND_CACHE_PAGES 64 |
||||
#else |
||||
#error Page size of NAND not defined. |
||||
#endif /* CONFIG_NAND_SP */ |
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM |
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM |
||||
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE |
||||
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM |
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM |
||||
|
||||
/*
|
||||
* JFFS2 configuration |
||||
*/ |
||||
#define CONFIG_JFFS2_NAND |
||||
#define CONFIG_JFFS2_DEV "nand0" |
||||
|
||||
/* mtdparts command line support */ |
||||
#define CONFIG_JFFS2_CMDLINE |
||||
#define MTDIDS_DEFAULT "nand0=nand0" |
||||
#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)" |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000 |
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 |
||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 |
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
||||
|
||||
/*
|
||||
* TSEC |
||||
*/ |
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_GMII /* MII PHY management */ |
||||
|
||||
#ifdef CONFIG_TSEC1 |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_TSEC1_NAME "TSEC0" |
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
||||
#define TSEC1_PHY_ADDR 0x0 |
||||
#define TSEC1_FLAGS TSEC_GIGABIT |
||||
#define TSEC1_PHYIDX 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_TSEC2 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_TSEC2_NAME "TSEC1" |
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
||||
#define TSEC2_PHY_ADDR 4 |
||||
#define TSEC2_FLAGS TSEC_GIGABIT |
||||
#define TSEC2_PHYIDX 0 |
||||
#endif |
||||
|
||||
|
||||
/* Options are: TSEC[0-1] */ |
||||
#define CONFIG_ETHPRIME "TSEC1" |
||||
|
||||
/*
|
||||
* Configure on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1337 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#if defined(CONFIG_NAND_U_BOOT) |
||||
#define CONFIG_ENV_IS_IN_NAND 1 |
||||
#define CONFIG_ENV_OFFSET (768 * 1024) |
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) |
||||
#elif !defined(CONFIG_SYS_RAMBOOT) |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#else |
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_IMLS |
||||
#undef CONFIG_CMD_FLASH |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_JFFS2 |
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) |
||||
#undef CONFIG_CMD_ENV |
||||
#undef CONFIG_CMD_LOADS |
||||
#endif |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \ |
||||
+ sizeof(CONFIG_SYS_PROMPT) \
|
||||
+ 16 ) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
||||
|
||||
#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \ |
||||
| 0x20000000 /* reserved */ \
|
||||
| HRCWL_DDR_TO_SCB_CLK_2X1 \
|
||||
| HRCWL_CSB_TO_CLKIN_4X1 \
|
||||
| HRCWL_CORE_TO_CSB_2_5X1 ) |
||||
|
||||
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4) |
||||
|
||||
#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \ |
||||
| HRCWH_PCI1_ARBITER_ENABLE \
|
||||
| HRCWH_CORE_ENABLE \
|
||||
| HRCWH_BOOTSEQ_DISABLE \
|
||||
| HRCWH_SW_WATCHDOG_DISABLE \
|
||||
| HRCWH_TSEC1M_IN_RGMII \
|
||||
| HRCWH_TSEC2M_IN_RGMII \
|
||||
| HRCWH_BIG_ENDIAN \
|
||||
| HRCWH_LALE_NORMAL ) |
||||
|
||||
#ifdef CONFIG_NAND_LP |
||||
#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ |
||||
| HRCWH_FROM_0XFFF00100 \
|
||||
| HRCWH_ROM_LOC_NAND_LP_8BIT \
|
||||
| HRCWH_RL_EXT_NAND) |
||||
#else |
||||
#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ |
||||
| HRCWH_FROM_0XFFF00100 \
|
||||
| HRCWH_ROM_LOC_NAND_SP_8BIT \
|
||||
| HRCWH_RL_EXT_NAND ) |
||||
#endif |
||||
|
||||
/* System IO Config */ |
||||
#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \ |
||||
| SICRH_ETSEC2_C \
|
||||
| SICRH_ETSEC2_D \
|
||||
| SICRH_ETSEC2_E \
|
||||
| SICRH_ETSEC2_F \
|
||||
| SICRH_ETSEC2_G \
|
||||
| SICRH_TSOBI1 \
|
||||
| SICRH_TSOBI2 ) |
||||
#define CONFIG_SYS_SICRL (SICRL_USBDR \ |
||||
| SICRL_ETSEC2_A ) |
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0x000000000 |
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
||||
| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) |
||||
|
||||
#define CONFIG_SYS_HID2 HID2_HBE |
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
||||
|
||||
/* DDR @ 0x00000000 */ |
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) |
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10) |
||||
#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* PCI @ 0x80000000 */ |
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) |
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* PCI2 not supported on 8313 */ |
||||
#define CONFIG_SYS_IBAT4L (0) |
||||
#define CONFIG_SYS_IBAT4U (0) |
||||
|
||||
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ |
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
||||
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10) |
||||
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CONFIG_SYS_IBAT7L (0) |
||||
#define CONFIG_SYS_IBAT7U (0) |
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
||||
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_NETDEV eth1 |
||||
|
||||
#define CONFIG_HOSTNAME simpc8313 |
||||
#define CONFIG_ROOTPATH /tftpboot/ |
||||
#define CONFIG_BOOTFILE /tftpboot/uImage |
||||
#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */ |
||||
#define CONFIG_FDTFILE simpc8313.dtb |
||||
|
||||
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ |
||||
#define CONFIG_BOOTDELAY 5 /* 5 second delay */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define XMK_STR(x) #x |
||||
#define MK_STR(x) XMK_STR(x) |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
||||
"ethprime=TSEC1\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"fdtaddr=ae0000\0" \
|
||||
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
|
||||
"console=ttyS0\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"load_uboot=tftp 100000 u-boot-nand.bin\0" \
|
||||
"burn_uboot=nand erase u-boot 80000; " \
|
||||
"nand write 100000 u-boot $filesize\0" \
|
||||
"update_uboot=run load_uboot;run burn_uboot\0" \
|
||||
"mtdids=nand0=nand0\0" \
|
||||
"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
|
||||
"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
|
||||
"console=ttyS0,115200\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setbootargs;" \
|
||||
"run setipargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv rootdev /dev/ram;" \
|
||||
"run setbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#undef MK_STR |
||||
#undef XMK_STR |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,100 @@ |
||||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
# (C) Copyright 2008 Freescale Semiconductor
|
||||
# (C) Copyright Sheldon Instruments, Inc. 2008
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
NAND_SPL := y
|
||||
TEXT_BASE := 0xfff00000
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o ticks.o
|
||||
COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
|
||||
all: $(obj).depend $(ALL) |
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl |
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl |
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS) |
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
$(obj)start.S: |
||||
ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $<
|
||||
|
||||
$(obj)nand_boot_fsl_elbc.c: |
||||
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $<
|
||||
|
||||
$(obj)sdram.c: |
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $<
|
||||
|
||||
$(obj)$(BOARD).c: |
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $<
|
||||
|
||||
$(obj)ns16550.c: |
||||
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $<
|
||||
|
||||
$(obj)nand_init.c: |
||||
ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $<
|
||||
|
||||
$(obj)time.c: |
||||
ln -sf $(SRCTREE)/lib_ppc/time.c $<
|
||||
|
||||
$(obj)ticks.S: |
||||
ln -sf $(SRCTREE)/lib_ppc/ticks.S $<
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S |
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c |
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,52 @@ |
||||
/* |
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
. = 0xfff00000; |
||||
.text : { |
||||
*(.text*) |
||||
. = ALIGN(16); |
||||
*(.rodata*) |
||||
*(.eh_frame) |
||||
} |
||||
|
||||
. = ALIGN(8); |
||||
.data : { |
||||
*(.data*) |
||||
*(.sdata*) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
__got2_entries = (. - _GOT2_TABLE_) >> 2; |
||||
} |
||||
|
||||
. = ALIGN(8); |
||||
__bss_start = .; |
||||
.bss (NOLOAD) : { *(.*bss) } |
||||
_end = .; |
||||
} |
||||
ENTRY(_start) |
||||
ASSERT(_end <= 0xfff01000, "NAND bootstrap too big"); |
||||
Loading…
Reference in new issue