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@ -1,4 +1,8 @@ |
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/*
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* Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com> |
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* |
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* based on previous work by |
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* |
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* Ulf Samuelsson <ulf@atmel.com> |
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* Rick Bronson <rick@efn.org> |
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* |
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@ -23,40 +27,52 @@ |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#ifndef __AT91RM9200EK_CONFIG_H__ |
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#define __AT91RM9200EK_CONFIG_H__ |
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#define CONFIG_AT91_LEGACY |
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#include <asm/sizes.h> |
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/* ARM asynchronous clock */ |
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/*
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* from 18.432 MHz crystal |
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* (18432000 / 4 * 39) |
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* AT91C_XTAL_CLOCK is the frequency of external xtal in hertz |
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* AT91C_MAIN_CLOCK is the frequency of PLLA output |
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* AT91C_MASTER_CLOCK is the peripherial clock |
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* CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely |
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* set in arch/arm/cpu/arm920t/at91/timer.c) |
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* CONFIG_SYS_HZ is the tick rate for timer tc0 |
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*/ |
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#define AT91C_MAIN_CLOCK 179712000 |
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/*
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* peripheral clock |
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* (AT91C_MASTER_CLOCK / 3) |
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*/ |
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#define AT91C_MASTER_CLOCK 59904000 |
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#define AT91C_XTAL_CLOCK 18432000 |
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#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) |
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#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) |
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#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) |
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#define CONFIG_SYS_HZ 1000 |
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#define AT91_SLOW_CLOCK 32768 /* slow clock */ |
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/* CPU configuration */ |
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#define CONFIG_ARM920T |
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#define CONFIG_AT91RM9200 |
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#define CONFIG_AT91RM9200EK |
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#define CONFIG_CPUAT91 |
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#define USE_920T_MMU |
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#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ |
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#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ |
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#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */ |
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
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#define USE_920T_MMU 1 |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_INITRD_TAG |
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
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#define CONFIG_SETUP_MEMORY_TAGS 1 |
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#define CONFIG_INITRD_TAG 1 |
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/*
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* Memory Configuration |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define CONFIG_SYS_SDRAM_BASE 0x20000000 |
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#define CONFIG_SYS_SDRAM_SIZE SZ_32M |
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
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#define CONFIG_SYS_MEMTEST_END \ |
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(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) |
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/*
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* LowLevel Init |
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*/ |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 |
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#define CONFIG_SYS_USE_MAIN_OSCILLATOR |
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/* flash */ |
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#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 |
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#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ |
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@ -73,50 +89,26 @@ |
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#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 |
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#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ |
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#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ |
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#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ |
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#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ |
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#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ |
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#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ |
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#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ |
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#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ |
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#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ |
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#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ |
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#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ |
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#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ |
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#else |
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#define CONFIG_SKIP_RELOCATE_UBOOT |
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
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/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ |
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#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33 |
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/*
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* Memory Configuration |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define PHYS_SDRAM 0x20000000 |
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#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */ |
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
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#define CONFIG_SYS_MEMTEST_END \ |
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(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144) |
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/*
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* Hardware drivers |
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*/ |
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/*
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* UART Configuration |
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* |
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* define one of these to choose the DBGU, |
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* USART0 or USART1 as console |
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* Choose a USART for serial console |
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* CONFIG_DBGU is DBGU unit on J10 |
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* CONFIG_USART1 is USART1 on J14 |
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*/ |
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#define CONFIG_AT91RM9200_USART |
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#define CONFIG_DBGU |
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#undef CONFIG_USART0 |
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#undef CONFIG_USART1 |
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/* don't include RTS/CTS flow control support */ |
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#undef CONFIG_HWFLOW |
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/* disable modem initialization stuff */ |
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#undef CONFIG_MODEM_SUPPORT |
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
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#define CONFIG_BAUDRATE 115200 |
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@ -130,156 +122,75 @@ |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_PING |
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#undef CONFIG_CMD_BDI |
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#undef CONFIG_CMD_IMI |
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#define CONFIG_CMD_USB |
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#undef CONFIG_CMD_FPGA |
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#undef CONFIG_CMD_MISC |
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#undef CONFIG_CMD_LOADS |
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#include <asm/arch/AT91RM9200.h> /* needed for port definitions */ |
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/* Options for MMC/SD Card */ |
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#define CONFIG_DOS_PARTITION 1 |
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#undef CONFIG_MMC |
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#define CONFIG_SYS_MMC_BASE 0xFFFB4000 |
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#define CONFIG_SYS_MMC_BLOCKSIZE 512 |
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/*
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* Network Driver Setting |
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*/ |
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#define CONFIG_NET_MULTI 1 |
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#ifdef CONFIG_NET_MULTI |
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#define CONFIG_DRIVER_AT91EMAC 1 |
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#define CONFIG_SYS_RX_ETH_BUFFER 8 |
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#else |
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#define CONFIG_DRIVER_ETHER 1 |
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#endif |
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#define CONFIG_NET_RETRY_COUNT 20 |
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#define CONFIG_AT91C_USE_RMII |
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/*
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* AC Characteristics |
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* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns |
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*/ |
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#define DATAFLASH_TCSS (0xC << 16) |
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#define DATAFLASH_TCHS (0x1 << 24) |
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#if defined(CONFIG_HAS_DATAFLASH) |
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#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) |
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#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 |
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#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 |
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/* Logical adress for CS0 */ |
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 |
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/* Logical adress for CS3 */ |
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 |
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#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1 |
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#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22 |
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#endif |
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#define CONFIG_NET_MULTI |
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#define CONFIG_DRIVER_AT91EMAC |
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#define CONFIG_SYS_RX_ETH_BUFFER 16 |
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#define CONFIG_RMII |
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#define CONFIG_MII |
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/*
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* NOR Flash |
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*/ |
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#define CONFIG_SYS_FLASH_BASE 0x10000000 |
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#define PHYS_FLASH_SIZE 0x800000 /* 8MB */ |
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#define CONFIG_SYS_FLASH_CFI 1 |
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#define CONFIG_FLASH_CFI_DRIVER 1 |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 256 |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_SYS_FLASH_BASE 0x10000000 |
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#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE |
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#define PHYS_FLASH_SIZE SZ_8M |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 256 |
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#define CONFIG_SYS_FLASH_PROTECTION |
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/*
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* Environment Settings |
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*/ |
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#ifdef CONFIG_ENV_IS_IN_DATAFLASH |
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/*
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* Datasflash Environment Settings |
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* USB Config |
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*/ |
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#define CONFIG_ENV_OFFSET 0x4200 |
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#define CONFIG_ENV_ADDR \ |
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(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) |
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/* 8 * 1056 really , but start.s is not OK with this*/ |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_USB_ATMEL 1 |
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#define CONFIG_USB_OHCI_NEW 1 |
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#define CONFIG_USB_KEYBOARD 1 |
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#define CONFIG_USB_STORAGE 1 |
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#define CONFIG_DOS_PARTITION 1 |
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#else |
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/*
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* NOR Flash Environment Settings |
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*/ |
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
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#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE |
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" |
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT |
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/*
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* between boot.bin and u-boot.bin.gz |
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* Environment Settings |
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*/ |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000) |
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#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ |
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#else |
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#define CONFIG_ENV_IS_IN_FLASH |
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/*
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* after u-boot.bin |
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*/ |
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#define CONFIG_ENV_ADDR \ |
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(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
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#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ |
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#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */ |
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/* The following #defines are needed to get flash environment right */ |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_MONITOR_LEN \ |
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(CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE) |
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
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#endif /* CONFIG_ENV_IS_IN_DATAFLASH */ |
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#define CONFIG_SYS_MONITOR_LEN SZ_256K |
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/*
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* Boot option |
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*/ |
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#define CONFIG_BOOTDELAY 3 |
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT |
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/* boot.bin, env, u-boot.bin.gz */ |
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#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ |
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#define CONFIG_SYS_U_BOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x10000) |
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#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ |
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#else |
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/* u-boot.bin */ |
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#define CONFIG_SYS_BOOT_SIZE 0x0 /* 0 KBytes */ |
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#define CONFIG_SYS_U_BOOT_BASE CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_U_BOOT_SIZE 0x40000 /* 128 KBytes */ |
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
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#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ |
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#define CONFIG_ENV_OVERWRITE 1 |
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/*
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* USB Config |
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*/ |
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#define CONFIG_CMD_USB |
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#define CONFIG_USB_OHCI_NEW 1 |
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#define CONFIG_USB_KEYBOARD 1 |
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#define CONFIG_USB_STORAGE 1 |
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#define CONFIG_DOS_PARTITION 1 |
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#undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
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#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE |
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" |
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
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/*
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* I2C |
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*/ |
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#define CONFIG_HARD_I2C |
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#ifdef CONFIG_HARD_I2C |
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#define CONFIG_CMD_I2C |
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#define CONFIG_SYS_I2C_SPEED 0 /* not used */ |
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#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ |
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#endif |
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/* default load address */ |
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M |
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#define CONFIG_ENV_OVERWRITE |
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/*
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* Shell Settings |
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*/ |
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#define CONFIG_CMDLINE_EDITING 1 |
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#define CONFIG_SYS_LONGHELP 1 |
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#define CONFIG_AUTO_COMPLETE 1 |
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#define CONFIG_SYS_HUSH_PARSER 1 |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_AUTO_COMPLETE |
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#define CONFIG_SYS_HUSH_PARSER |
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#define CONFIG_SYS_PROMPT "U-Boot> " |
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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@ -288,41 +199,18 @@ |
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#define CONFIG_SYS_PBSIZE \ |
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
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#ifndef __ASSEMBLY__ |
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/*-----------------------------------------------------------------------
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* Board specific extension for bd_info |
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* |
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* This structure is embedded in the global bd_info (bd_t) structure |
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* and can be used by the board specific code (eg board/...) |
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*/ |
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struct bd_info_ext { |
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/* helper variable for board environment handling
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* |
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* env_crc_valid == 0 => uninitialised |
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* env_crc_valid > 0 => environment crc in flash is valid |
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* env_crc_valid < 0 => environment crc in flash is invalid |
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*/ |
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int env_crc_valid; |
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}; |
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#endif |
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#define CONFIG_SYS_HZ 1000 |
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/*
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* AT91C_TC0_CMR is implicitly set to |
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* AT91C_TC_TIMER_DIV1_CLOCK |
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*/ |
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#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) |
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/*
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* Size of malloc() pool |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \ |
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, 0x1000) |
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ |
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SZ_4K) |
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/* size in bytes reserved for initial data */ |
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#define CONFIG_SYS_GBL_DATA_SIZE 128 |
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#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ |
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#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* Unsure if to big or to small*/ |
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#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* Unsure if to big or to small*/ |
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#endif |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ |
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- CONFIG_SYS_GBL_DATA_SIZE) |
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#define CONFIG_STACKSIZE SZ_32K /* regular stack */ |
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#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/ |
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#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/ |
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#endif /* __AT91RM9200EK_CONFIG_H__ */ |
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Wolfgang Denk
15 years ago