This adds a new firefly-rk3399 board, MIPI support for rk3399 and rk3288, rk818 pmic support, mkimage improvements for rockchip and a few other things.master
Tom Rini
8 years ago
commit
1f5541c881
@ -0,0 +1,660 @@ |
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/* |
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/dts-v1/; |
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#include <dt-bindings/pwm/pwm.h> |
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#include <dt-bindings/pinctrl/rockchip.h> |
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#include "rk3399.dtsi" |
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#include "rk3399-sdram-ddr3-1333.dtsi" |
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/ { |
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model = "Firefly-RK3399 Board"; |
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compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; |
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|
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chosen { |
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stdout-path = &uart2; |
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}; |
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backlight: backlight { |
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compatible = "pwm-backlight"; |
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enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; |
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pwms = <&pwm0 0 25000 0>; |
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brightness-levels = < |
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0 1 2 3 4 5 6 7 |
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8 9 10 11 12 13 14 15 |
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16 17 18 19 20 21 22 23 |
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24 25 26 27 28 29 30 31 |
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32 33 34 35 36 37 38 39 |
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40 41 42 43 44 45 46 47 |
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48 49 50 51 52 53 54 55 |
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56 57 58 59 60 61 62 63 |
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64 65 66 67 68 69 70 71 |
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72 73 74 75 76 77 78 79 |
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80 81 82 83 84 85 86 87 |
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88 89 90 91 92 93 94 95 |
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96 97 98 99 100 101 102 103 |
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104 105 106 107 108 109 110 111 |
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112 113 114 115 116 117 118 119 |
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120 121 122 123 124 125 126 127 |
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128 129 130 131 132 133 134 135 |
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136 137 138 139 140 141 142 143 |
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144 145 146 147 148 149 150 151 |
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152 153 154 155 156 157 158 159 |
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160 161 162 163 164 165 166 167 |
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168 169 170 171 172 173 174 175 |
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176 177 178 179 180 181 182 183 |
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184 185 186 187 188 189 190 191 |
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192 193 194 195 196 197 198 199 |
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200 201 202 203 204 205 206 207 |
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208 209 210 211 212 213 214 215 |
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216 217 218 219 220 221 222 223 |
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224 225 226 227 228 229 230 231 |
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232 233 234 235 236 237 238 239 |
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240 241 242 243 244 245 246 247 |
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248 249 250 251 252 253 254 255>; |
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default-brightness-level = <200>; |
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}; |
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|
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clkin_gmac: external-gmac-clock { |
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compatible = "fixed-clock"; |
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clock-frequency = <125000000>; |
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clock-output-names = "clkin_gmac"; |
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#clock-cells = <0>; |
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}; |
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|
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rt5640-sound { |
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compatible = "simple-audio-card"; |
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simple-audio-card,name = "rockchip,rt5640-codec"; |
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simple-audio-card,format = "i2s"; |
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simple-audio-card,mclk-fs = <256>; |
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simple-audio-card,widgets = |
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"Microphone", "Mic Jack", |
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"Headphone", "Headphone Jack"; |
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simple-audio-card,routing = |
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"Mic Jack", "MICBIAS1", |
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"IN1P", "Mic Jack", |
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"Headphone Jack", "HPOL", |
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"Headphone Jack", "HPOR"; |
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simple-audio-card,cpu { |
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sound-dai = <&i2s1>; |
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}; |
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simple-audio-card,codec { |
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sound-dai = <&rt5640>; |
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}; |
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}; |
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|
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sdio_pwrseq: sdio-pwrseq { |
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compatible = "mmc-pwrseq-simple"; |
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clocks = <&rk808 1>; |
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clock-names = "ext_clock"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&wifi_enable_h>; |
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|
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/* |
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* On the module itself this is one of these (depending |
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* on the actual card populated): |
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* - SDIO_RESET_L_WL_REG_ON |
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* - PDN (power down when low) |
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*/ |
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reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; |
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}; |
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|
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vcc3v3_pcie: vcc3v3-pcie-regulator { |
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compatible = "regulator-fixed"; |
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enable-active-high; |
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gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pcie_drv>; |
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regulator-name = "vcc3v3_pcie"; |
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regulator-always-on; |
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regulator-boot-on; |
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}; |
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vcc3v3_sys: vcc3v3-sys { |
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compatible = "regulator-fixed"; |
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regulator-name = "vcc3v3_sys"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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}; |
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vcc5v0_host: vcc5v0-host-regulator { |
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compatible = "regulator-fixed"; |
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enable-active-high; |
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gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&host_vbus_drv>; |
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regulator-name = "vcc5v0_host"; |
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regulator-always-on; |
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}; |
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vcc5v0_sys: vcc5v0-sys { |
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compatible = "regulator-fixed"; |
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regulator-name = "vcc5v0_sys"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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}; |
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vcc_phy: vcc-phy-regulator { |
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compatible = "regulator-fixed"; |
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regulator-name = "vcc_phy"; |
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regulator-always-on; |
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regulator-boot-on; |
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}; |
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vdd_log: vdd-log { |
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compatible = "pwm-regulator"; |
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pwms = <&pwm2 0 25000 1>; |
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regulator-name = "vdd_log"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <800000>; |
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regulator-max-microvolt = <1400000>; |
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}; |
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vccadc_ref: vccadc-ref { |
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compatible = "regulator-fixed"; |
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regulator-name = "vcc1v8_sys"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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}; |
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}; |
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&cpu_l0 { |
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cpu-supply = <&vdd_cpu_l>; |
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}; |
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&cpu_l1 { |
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cpu-supply = <&vdd_cpu_l>; |
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}; |
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&cpu_l2 { |
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cpu-supply = <&vdd_cpu_l>; |
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}; |
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&cpu_l3 { |
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cpu-supply = <&vdd_cpu_l>; |
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}; |
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&cpu_b0 { |
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cpu-supply = <&vdd_cpu_b>; |
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}; |
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&cpu_b1 { |
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cpu-supply = <&vdd_cpu_b>; |
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}; |
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&emmc_phy { |
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status = "okay"; |
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}; |
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&gmac { |
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assigned-clocks = <&cru SCLK_RMII_SRC>; |
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assigned-clock-parents = <&clkin_gmac>; |
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clock_in_out = "input"; |
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phy-supply = <&vcc_phy>; |
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phy-mode = "rgmii"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&rgmii_pins>; |
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snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; |
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snps,reset-active-low; |
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snps,reset-delays-us = <0 10000 50000>; |
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tx_delay = <0x28>; |
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rx_delay = <0x11>; |
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status = "okay"; |
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}; |
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&i2c0 { |
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clock-frequency = <400000>; |
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i2c-scl-rising-time-ns = <168>; |
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i2c-scl-falling-time-ns = <4>; |
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status = "okay"; |
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rk808: pmic@1b { |
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compatible = "rockchip,rk808"; |
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reg = <0x1b>; |
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interrupt-parent = <&gpio1>; |
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interrupts = <21 IRQ_TYPE_LEVEL_LOW>; |
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#clock-cells = <1>; |
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clock-output-names = "xin32k", "rk808-clkout2"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pmic_int_l>; |
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rockchip,system-power-controller; |
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wakeup-source; |
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vcc1-supply = <&vcc3v3_sys>; |
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vcc2-supply = <&vcc3v3_sys>; |
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vcc3-supply = <&vcc3v3_sys>; |
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vcc4-supply = <&vcc3v3_sys>; |
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vcc6-supply = <&vcc3v3_sys>; |
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vcc7-supply = <&vcc3v3_sys>; |
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vcc8-supply = <&vcc3v3_sys>; |
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vcc9-supply = <&vcc3v3_sys>; |
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vcc10-supply = <&vcc3v3_sys>; |
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vcc11-supply = <&vcc3v3_sys>; |
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vcc12-supply = <&vcc3v3_sys>; |
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vddio-supply = <&vcc1v8_pmu>; |
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regulators { |
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vdd_center: DCDC_REG1 { |
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regulator-name = "vdd_center"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <750000>; |
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regulator-max-microvolt = <1350000>; |
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regulator-ramp-delay = <6001>; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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vdd_cpu_l: DCDC_REG2 { |
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regulator-name = "vdd_cpu_l"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <750000>; |
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regulator-max-microvolt = <1350000>; |
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regulator-ramp-delay = <6001>; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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vcc_ddr: DCDC_REG3 { |
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regulator-name = "vcc_ddr"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-state-mem { |
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regulator-on-in-suspend; |
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}; |
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}; |
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vcc_1v8: DCDC_REG4 { |
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regulator-name = "vcc_1v8"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-state-mem { |
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regulator-on-in-suspend; |
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regulator-suspend-microvolt = <1800000>; |
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}; |
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}; |
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vcc1v8_dvp: LDO_REG1 { |
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regulator-name = "vcc1v8_dvp"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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vcc3v0_tp: LDO_REG2 { |
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regulator-name = "vcc3v0_tp"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <3000000>; |
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regulator-max-microvolt = <3000000>; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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vcc1v8_pmu: LDO_REG3 { |
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regulator-name = "vcc1v8_pmu"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-state-mem { |
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regulator-on-in-suspend; |
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regulator-suspend-microvolt = <1800000>; |
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}; |
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}; |
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vcc_sd: LDO_REG4 { |
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regulator-name = "vcc_sd"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-state-mem { |
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regulator-on-in-suspend; |
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regulator-suspend-microvolt = <3300000>; |
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}; |
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}; |
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vcca3v0_codec: LDO_REG5 { |
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regulator-name = "vcca3v0_codec"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <3000000>; |
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regulator-max-microvolt = <3000000>; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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vcc_1v5: LDO_REG6 { |
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regulator-name = "vcc_1v5"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1500000>; |
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regulator-max-microvolt = <1500000>; |
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regulator-state-mem { |
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regulator-on-in-suspend; |
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regulator-suspend-microvolt = <1500000>; |
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}; |
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}; |
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vcca1v8_codec: LDO_REG7 { |
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regulator-name = "vcca1v8_codec"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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vcc_3v0: LDO_REG8 { |
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regulator-name = "vcc_3v0"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <3000000>; |
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regulator-max-microvolt = <3000000>; |
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regulator-state-mem { |
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regulator-on-in-suspend; |
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regulator-suspend-microvolt = <3000000>; |
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}; |
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}; |
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vcc3v3_s3: SWITCH_REG1 { |
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regulator-name = "vcc3v3_s3"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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vcc3v3_s0: SWITCH_REG2 { |
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regulator-name = "vcc3v3_s0"; |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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}; |
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}; |
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vdd_cpu_b: regulator@40 { |
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compatible = "silergy,syr827"; |
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reg = <0x40>; |
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fcs,suspend-voltage-selector = <0>; |
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regulator-name = "vdd_cpu_b"; |
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regulator-min-microvolt = <712500>; |
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regulator-max-microvolt = <1500000>; |
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regulator-ramp-delay = <1000>; |
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regulator-always-on; |
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regulator-boot-on; |
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vin-supply = <&vcc5v0_sys>; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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vdd_gpu: regulator@41 { |
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compatible = "silergy,syr828"; |
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reg = <0x41>; |
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fcs,suspend-voltage-selector = <1>; |
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regulator-name = "vdd_gpu"; |
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regulator-min-microvolt = <712500>; |
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regulator-max-microvolt = <1500000>; |
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regulator-ramp-delay = <1000>; |
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regulator-always-on; |
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regulator-boot-on; |
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vin-supply = <&vcc5v0_sys>; |
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regulator-state-mem { |
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regulator-off-in-suspend; |
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}; |
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}; |
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}; |
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&i2c1 { |
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i2c-scl-rising-time-ns = <300>; |
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i2c-scl-falling-time-ns = <15>; |
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status = "okay"; |
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rt5640: rt5640@1c { |
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compatible = "realtek,rt5640"; |
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reg = <0x1c>; |
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clocks = <&cru SCLK_I2S_8CH_OUT>; |
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clock-names = "mclk"; |
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realtek,in1-differential; |
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#sound-dai-cells = <0>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&rt5640_hpcon>; |
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}; |
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}; |
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&i2c3 { |
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i2c-scl-rising-time-ns = <450>; |
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i2c-scl-falling-time-ns = <15>; |
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status = "okay"; |
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}; |
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|
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&i2c4 { |
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i2c-scl-rising-time-ns = <600>; |
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i2c-scl-falling-time-ns = <20>; |
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status = "okay"; |
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accelerometer@68 { |
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compatible = "invensense,mpu6500"; |
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reg = <0x68>; |
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interrupt-parent = <&gpio1>; |
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interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>; |
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}; |
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}; |
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&i2s0 { |
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rockchip,playback-channels = <8>; |
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rockchip,capture-channels = <8>; |
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#sound-dai-cells = <0>; |
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status = "okay"; |
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}; |
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&i2s1 { |
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rockchip,playback-channels = <2>; |
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rockchip,capture-channels = <2>; |
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#sound-dai-cells = <0>; |
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status = "okay"; |
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}; |
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|
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&i2s2 { |
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#sound-dai-cells = <0>; |
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status = "okay"; |
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}; |
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&io_domains { |
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status = "okay"; |
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bt656-supply = <&vcc1v8_dvp>; |
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audio-supply = <&vcca1v8_codec>; |
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sdmmc-supply = <&vcc_sd>; |
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gpio1830-supply = <&vcc_3v0>; |
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}; |
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|
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&pcie_phy { |
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status = "okay"; |
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}; |
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|
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&pcie0 { |
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ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; |
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num-lanes = <4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pcie_clkreqn>; |
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status = "okay"; |
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}; |
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|
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&pmu_io_domains { |
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pmu1830-supply = <&vcc_3v0>; |
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status = "okay"; |
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}; |
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|
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&pinctrl { |
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buttons { |
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pwrbtn: pwrbtn { |
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rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; |
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}; |
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}; |
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|
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lcd-panel { |
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lcd_panel_reset: lcd-panel-reset { |
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rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; |
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}; |
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}; |
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|
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pcie { |
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pcie_drv: pcie-drv { |
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rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; |
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}; |
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|
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pcie_3g_drv: pcie-3g-drv { |
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rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; |
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}; |
||||
}; |
||||
|
||||
pmic { |
||||
vsel1_gpio: vsel1-gpio { |
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; |
||||
}; |
||||
|
||||
vsel2_gpio: vsel2-gpio { |
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; |
||||
}; |
||||
}; |
||||
|
||||
sdio-pwrseq { |
||||
wifi_enable_h: wifi-enable-h { |
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; |
||||
}; |
||||
}; |
||||
|
||||
rt5640 { |
||||
rt5640_hpcon: rt5640-hpcon { |
||||
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; |
||||
}; |
||||
}; |
||||
|
||||
pmic { |
||||
pmic_int_l: pmic-int-l { |
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; |
||||
}; |
||||
}; |
||||
|
||||
usb2 { |
||||
host_vbus_drv: host-vbus-drv { |
||||
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&pwm0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&pwm2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&saradc { |
||||
vref-supply = <&vccadc_ref>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhci { |
||||
bus-width = <8>; |
||||
keep-power-in-suspend; |
||||
mmc-hs400-1_8v; |
||||
mmc-hs400-enhanced-strobe; |
||||
non-removable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&tsadc { |
||||
/* tshut mode 0:CRU 1:GPIO */ |
||||
rockchip,hw-tshut-mode = <1>; |
||||
/* tshut polarity 0:LOW 1:HIGH */ |
||||
rockchip,hw-tshut-polarity = <1>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&u2phy0 { |
||||
status = "okay"; |
||||
|
||||
u2phy0_otg: otg-port { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
u2phy0_host: host-port { |
||||
phy-supply = <&vcc5v0_host>; |
||||
status = "okay"; |
||||
}; |
||||
}; |
||||
|
||||
&u2phy1 { |
||||
status = "okay"; |
||||
|
||||
u2phy1_otg: otg-port { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
u2phy1_host: host-port { |
||||
phy-supply = <&vcc5v0_host>; |
||||
status = "okay"; |
||||
}; |
||||
}; |
||||
|
||||
&uart0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart0_xfer &uart0_cts>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb_host0_ehci { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb_host0_ohci { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb_host1_ehci { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb_host1_ohci { |
||||
status = "okay"; |
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,195 @@ |
||||
/*
|
||||
* Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd |
||||
* author: Eric Gao <eric.gao@rock-chips.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef ROCKCHIP_MIPI_DSI_H |
||||
#define ROCKCHIP_MIPI_DSI_H |
||||
|
||||
/*
|
||||
* All these mipi controller register declaration provide reg address offset, |
||||
* bits width, bit offset for a specified register bits. With these message, we |
||||
* can set or clear every bits individually for a 32bit widthregister. We use |
||||
* DSI_HOST_BITS macro definition to combinat these message using the following |
||||
* format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit) |
||||
* For example: |
||||
* #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0) |
||||
* means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr |
||||
* offset is 0x004.The conbinat result = (0x004 << 16) | (1 << 8) | 0 |
||||
*/ |
||||
#define ADDR_SHIFT 16 |
||||
#define BITS_SHIFT 8 |
||||
#define OFFSET_SHIFT 0 |
||||
#define DSI_HOST_BITS(addr, bits, bit_offset) \ |
||||
((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT)) |
||||
|
||||
/* DWC_DSI_VERSION_0x3133302A */ |
||||
#define VERSION DSI_HOST_BITS(0x000, 32, 0) |
||||
#define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0) |
||||
#define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8) |
||||
#define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 0) |
||||
#define DPI_VCID DSI_HOST_BITS(0x00c, 2, 0) |
||||
#define EN18_LOOSELY DSI_HOST_BITS(0x010, 1, 8) |
||||
#define DPI_COLOR_CODING DSI_HOST_BITS(0x010, 4, 0) |
||||
#define COLORM_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 4) |
||||
#define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 3) |
||||
#define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 2) |
||||
#define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 1) |
||||
#define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 0) |
||||
#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 16) |
||||
#define INVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 0) |
||||
#define CRC_RX_EN DSI_HOST_BITS(0x02c, 1, 4) |
||||
#define ECC_RX_EN DSI_HOST_BITS(0x02c, 1, 3) |
||||
#define BTA_EN DSI_HOST_BITS(0x02c, 1, 2) |
||||
#define EOTP_RX_EN DSI_HOST_BITS(0x02c, 1, 1) |
||||
#define EOTP_TX_EN DSI_HOST_BITS(0x02c, 1, 0) |
||||
#define GEN_VID_RX DSI_HOST_BITS(0x030, 2, 0) |
||||
#define CMD_VIDEO_MODE DSI_HOST_BITS(0x034, 1, 0) |
||||
#define VPG_ORIENTATION DSI_HOST_BITS(0x038, 1, 24) |
||||
#define VPG_MODE DSI_HOST_BITS(0x038, 1, 20) |
||||
#define VPG_EN DSI_HOST_BITS(0x038, 1, 16) |
||||
#define LP_CMD_EN DSI_HOST_BITS(0x038, 1, 15) |
||||
#define FRAME_BTA_ACK_EN DSI_HOST_BITS(0x038, 1, 14) |
||||
#define LP_HFP_EN DSI_HOST_BITS(0x038, 1, 13) |
||||
#define LP_HBP_EN DSI_HOST_BITS(0x038, 1, 12) |
||||
#define LP_VACT_EN DSI_HOST_BITS(0x038, 1, 11) |
||||
#define LP_VFP_EN DSI_HOST_BITS(0x038, 1, 10) |
||||
#define LP_VBP_EN DSI_HOST_BITS(0x038, 1, 9) |
||||
#define LP_VSA_EN DSI_HOST_BITS(0x038, 1, 8) |
||||
#define VID_MODE_TYPE DSI_HOST_BITS(0x038, 2, 0) |
||||
#define VID_PKT_SIZE DSI_HOST_BITS(0x03c, 14, 0) |
||||
#define NUM_CHUNKS DSI_HOST_BITS(0x040, 13, 0) |
||||
#define NULL_PKT_SIZE DSI_HOST_BITS(0x044, 13, 0) |
||||
#define VID_HSA_TIME DSI_HOST_BITS(0x048, 12, 0) |
||||
#define VID_HBP_TIME DSI_HOST_BITS(0x04c, 12, 0) |
||||
#define VID_HLINE_TIME DSI_HOST_BITS(0x050, 15, 0) |
||||
#define VID_VSA_LINES DSI_HOST_BITS(0x054, 10, 0) |
||||
#define VID_VBP_LINES DSI_HOST_BITS(0x058, 10, 0) |
||||
#define VID_VFP_LINES DSI_HOST_BITS(0x05c, 10, 0) |
||||
#define VID_ACTIVE_LINES DSI_HOST_BITS(0x060, 14, 0) |
||||
#define EDPI_CMD_SIZE DSI_HOST_BITS(0x064, 16, 0) |
||||
#define MAX_RD_PKT_SIZE DSI_HOST_BITS(0x068, 1, 24) |
||||
#define DCS_LW_TX DSI_HOST_BITS(0x068, 1, 19) |
||||
#define DCS_SR_0P_TX DSI_HOST_BITS(0x068, 1, 18) |
||||
#define DCS_SW_1P_TX DSI_HOST_BITS(0x068, 1, 17) |
||||
#define DCS_SW_0P_TX DSI_HOST_BITS(0x068, 1, 16) |
||||
#define GEN_LW_TX DSI_HOST_BITS(0x068, 1, 14) |
||||
#define GEN_SR_2P_TX DSI_HOST_BITS(0x068, 1, 13) |
||||
#define GEN_SR_1P_TX DSI_HOST_BITS(0x068, 1, 12) |
||||
#define GEN_SR_0P_TX DSI_HOST_BITS(0x068, 1, 11) |
||||
#define GEN_SW_2P_TX DSI_HOST_BITS(0x068, 1, 10) |
||||
#define GEN_SW_1P_TX DSI_HOST_BITS(0x068, 1, 9) |
||||
#define GEN_SW_0P_TX DSI_HOST_BITS(0x068, 1, 8) |
||||
#define ACK_RQST_EN DSI_HOST_BITS(0x068, 1, 1) |
||||
#define TEAR_FX_EN DSI_HOST_BITS(0x068, 1, 0) |
||||
#define GEN_WC_MSBYTE DSI_HOST_BITS(0x06c, 14, 16) |
||||
#define GEN_WC_LSBYTE DSI_HOST_BITS(0x06c, 8, 8) |
||||
#define GEN_VC DSI_HOST_BITS(0x06c, 2, 6) |
||||
#define GEN_DT DSI_HOST_BITS(0x06c, 6, 0) |
||||
#define GEN_PLD_DATA DSI_HOST_BITS(0x070, 32, 0) |
||||
#define GEN_RD_CMD_BUSY DSI_HOST_BITS(0x074, 1, 6) |
||||
#define GEN_PLD_R_FULL DSI_HOST_BITS(0x074, 1, 5) |
||||
#define GEN_PLD_R_EMPTY DSI_HOST_BITS(0x074, 1, 4) |
||||
#define GEN_PLD_W_FULL DSI_HOST_BITS(0x074, 1, 3) |
||||
#define GEN_PLD_W_EMPTY DSI_HOST_BITS(0x074, 1, 2) |
||||
#define GEN_CMD_FULL DSI_HOST_BITS(0x074, 1, 1) |
||||
#define GEN_CMD_EMPTY DSI_HOST_BITS(0x074, 1, 0) |
||||
#define HSTX_TO_CNT DSI_HOST_BITS(0x078, 16, 16) |
||||
#define LPRX_TO_CNT DSI_HOST_BITS(0x078, 16, 0) |
||||
#define HS_RD_TO_CNT DSI_HOST_BITS(0x07c, 16, 0) |
||||
#define LP_RD_TO_CNT DSI_HOST_BITS(0x080, 16, 0) |
||||
#define PRESP_TO_MODE DSI_HOST_BITS(0x084, 1, 24) |
||||
#define HS_WR_TO_CNT DSI_HOST_BITS(0x084, 16, 0) |
||||
#define LP_WR_TO_CNT DSI_HOST_BITS(0x088, 16, 0) |
||||
#define BTA_TO_CNT DSI_HOST_BITS(0x08c, 16, 0) |
||||
#define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0x094, 1, 1) |
||||
#define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0x094, 1, 0) |
||||
#define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 16) |
||||
#define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 0) |
||||
#define PHY_HS2LP_TIME DSI_HOST_BITS(0x09c, 8, 24) |
||||
#define PHY_LP2HS_TIME DSI_HOST_BITS(0x09c, 8, 16) |
||||
#define MAX_RD_TIME DSI_HOST_BITS(0x09c, 15, 0) |
||||
#define PHY_FORCEPLL DSI_HOST_BITS(0x0a0, 1, 3) |
||||
#define PHY_ENABLECLK DSI_HOST_BITS(0x0a0, 1, 2) |
||||
#define PHY_RSTZ DSI_HOST_BITS(0x0a0, 1, 1) |
||||
#define PHY_SHUTDOWNZ DSI_HOST_BITS(0x0a0, 1, 0) |
||||
#define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0x0a4, 8, 8) |
||||
#define N_LANES DSI_HOST_BITS(0x0a4, 2, 0) |
||||
#define PHY_TXEXITULPSLAN DSI_HOST_BITS(0x0a8, 1, 3) |
||||
#define PHY_TXREQULPSLAN DSI_HOST_BITS(0x0a8, 1, 2) |
||||
#define PHY_TXEXITULPSCLK DSI_HOST_BITS(0x0a8, 1, 1) |
||||
#define PHY_TXREQULPSCLK DSI_HOST_BITS(0x0a8, 1, 0) |
||||
#define PHY_TX_TRIGGERS DSI_HOST_BITS(0x0ac, 4, 0) |
||||
#define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0x0b0, 1, 2) |
||||
#define PHYLOCK DSI_HOST_BITS(0x0b0, 1, 0) |
||||
#define PHY_TESTCLK DSI_HOST_BITS(0x0b4, 1, 1) |
||||
#define PHY_TESTCLR DSI_HOST_BITS(0x0b4, 1, 0) |
||||
#define PHY_TESTEN DSI_HOST_BITS(0x0b8, 1, 16) |
||||
#define PHY_TESTDOUT DSI_HOST_BITS(0x0b8, 8, 8) |
||||
#define PHY_TESTDIN DSI_HOST_BITS(0x0b8, 8, 0) |
||||
#define PHY_TEST_CTRL1 DSI_HOST_BITS(0x0b8, 17, 0) |
||||
#define PHY_TEST_CTRL0 DSI_HOST_BITS(0x0b4, 2, 0) |
||||
#define INT_ST0 DSI_HOST_BITS(0x0bc, 21, 0) |
||||
#define INT_ST1 DSI_HOST_BITS(0x0c0, 18, 0) |
||||
#define INT_MKS0 DSI_HOST_BITS(0x0c4, 21, 0) |
||||
#define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0) |
||||
#define INT_FORCE0 DSI_HOST_BITS(0x0d8, 21, 0) |
||||
#define INT_FORCE1 DSI_HOST_BITS(0x0dc, 18, 0) |
||||
|
||||
#define CODE_HS_RX_CLOCK 0x34 |
||||
#define CODE_HS_RX_LANE0 0x44 |
||||
#define CODE_HS_RX_LANE1 0x54 |
||||
#define CODE_HS_RX_LANE2 0x84 |
||||
#define CODE_HS_RX_LANE3 0x94 |
||||
|
||||
#define CODE_PLL_VCORANGE_VCOCAP 0x10 |
||||
#define CODE_PLL_CPCTRL 0x11 |
||||
#define CODE_PLL_LPF_CP 0x12 |
||||
#define CODE_PLL_INPUT_DIV_RAT 0x17 |
||||
#define CODE_PLL_LOOP_DIV_RAT 0x18 |
||||
#define CODE_PLL_INPUT_LOOP_DIV_RAT 0x19 |
||||
#define CODE_BANDGAP_BIAS_CTRL 0x20 |
||||
#define CODE_TERMINATION_CTRL 0x21 |
||||
#define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22 |
||||
|
||||
#define CODE_HSTXDATALANEREQUSETSTATETIME 0x70 |
||||
#define CODE_HSTXDATALANEPREPARESTATETIME 0x71 |
||||
#define CODE_HSTXDATALANEHSZEROSTATETIME 0x72 |
||||
|
||||
/* Transmission mode between vop and MIPI controller */ |
||||
enum vid_mode_type_t { |
||||
NON_BURST_SYNC_PLUSE = 0, |
||||
NON_BURST_SYNC_EVENT, |
||||
BURST_MODE, |
||||
}; |
||||
|
||||
enum cmd_video_mode { |
||||
VIDEO_MODE = 0, |
||||
CMD_MODE, |
||||
}; |
||||
|
||||
/* Indicate MIPI DSI color mode */ |
||||
enum dpi_color_coding { |
||||
DPI_16BIT_CFG_1 = 0, |
||||
DPI_16BIT_CFG_2, |
||||
DPI_16BIT_CFG_3, |
||||
DPI_18BIT_CFG_1, |
||||
DPI_18BIT_CFG_2, |
||||
DPI_24BIT, |
||||
DPI_20BIT_YCBCR_422_LP, |
||||
DPI_24BIT_YCBCR_422, |
||||
DPI_16BIT_YCBCR_422, |
||||
DPI_30BIT, |
||||
DPI_36BIT, |
||||
DPI_12BIT_YCBCR_420, |
||||
}; |
||||
|
||||
/* Indicate which VOP the MIPI DSI use, bit or little one */ |
||||
enum vop_id { |
||||
VOP_B = 0, |
||||
VOP_L, |
||||
}; |
||||
|
||||
#endif /* end of ROCKCHIP_MIPI_DSI_H */ |
||||
@ -0,0 +1,65 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_ROCKCHIP=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000 |
||||
CONFIG_ROCKCHIP_RK3399=y |
||||
CONFIG_SPL_STACK_R_ADDR=0x80000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" |
||||
CONFIG_FIT=y |
||||
CONFIG_SPL_LOAD_FIT=y |
||||
# CONFIG_DISPLAY_CPUINFO is not set |
||||
CONFIG_SPL_STACK_R=y |
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 |
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_GPT=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_USB=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_SPL_OF_CONTROL=y |
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
||||
CONFIG_SPL_OF_PLATDATA=y |
||||
CONFIG_REGMAP=y |
||||
CONFIG_SPL_REGMAP=y |
||||
CONFIG_SYSCON=y |
||||
CONFIG_SPL_SYSCON=y |
||||
CONFIG_CLK=y |
||||
CONFIG_SPL_CLK=y |
||||
CONFIG_ROCKCHIP_GPIO=y |
||||
CONFIG_SYS_I2C_ROCKCHIP=y |
||||
CONFIG_MMC_DW=y |
||||
CONFIG_MMC_SDHCI=y |
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ETH_DESIGNWARE=y |
||||
CONFIG_GMAC_ROCKCHIP=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_SPL_PINCTRL=y |
||||
CONFIG_ROCKCHIP_RK3399_PINCTRL=y |
||||
CONFIG_DM_PMIC=y |
||||
CONFIG_PMIC_RK8XX=y |
||||
CONFIG_REGULATOR_PWM=y |
||||
CONFIG_DM_REGULATOR_FIXED=y |
||||
CONFIG_REGULATOR_RK8XX=y |
||||
CONFIG_PWM_ROCKCHIP=y |
||||
CONFIG_RAM=y |
||||
CONFIG_SPL_RAM=y |
||||
CONFIG_BAUDRATE=1500000 |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_DEBUG_UART_BASE=0xFF1A0000 |
||||
CONFIG_DEBUG_UART_CLOCK=24000000 |
||||
CONFIG_DEBUG_UART_SHIFT=2 |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_SYSRESET=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_XHCI_HCD=y |
||||
CONFIG_USB_XHCI_DWC3=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_EHCI_GENERIC=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USE_TINY_PRINTF=y |
||||
CONFIG_ERRNO_STR=y |
||||
@ -0,0 +1,69 @@ |
||||
Specifying PWM information for devices |
||||
====================================== |
||||
|
||||
1) PWM user nodes |
||||
----------------- |
||||
|
||||
PWM users should specify a list of PWM devices that they want to use |
||||
with a property containing a 'pwm-list': |
||||
|
||||
pwm-list ::= <single-pwm> [pwm-list] |
||||
single-pwm ::= <pwm-phandle> <pwm-specifier> |
||||
pwm-phandle : phandle to PWM controller node |
||||
pwm-specifier : array of #pwm-cells specifying the given PWM |
||||
(controller specific) |
||||
|
||||
PWM properties should be named "pwms". The exact meaning of each pwms |
||||
property must be documented in the device tree binding for each device. |
||||
An optional property "pwm-names" may contain a list of strings to label |
||||
each of the PWM devices listed in the "pwms" property. If no "pwm-names" |
||||
property is given, the name of the user node will be used as fallback. |
||||
|
||||
Drivers for devices that use more than a single PWM device can use the |
||||
"pwm-names" property to map the name of the PWM device requested by the |
||||
pwm_get() call to an index into the list given by the "pwms" property. |
||||
|
||||
The following example could be used to describe a PWM-based backlight |
||||
device: |
||||
|
||||
pwm: pwm { |
||||
#pwm-cells = <2>; |
||||
}; |
||||
|
||||
[...] |
||||
|
||||
bl: backlight { |
||||
pwms = <&pwm 0 5000000>; |
||||
pwm-names = "backlight"; |
||||
}; |
||||
|
||||
Note that in the example above, specifying the "pwm-names" is redundant |
||||
because the name "backlight" would be used as fallback anyway. |
||||
|
||||
pwm-specifier typically encodes the chip-relative PWM number and the PWM |
||||
period in nanoseconds. |
||||
|
||||
Optionally, the pwm-specifier can encode a number of flags (defined in |
||||
<dt-bindings/pwm/pwm.h>) in a third cell: |
||||
- PWM_POLARITY_INVERTED: invert the PWM signal polarity |
||||
|
||||
Example with optional PWM specifier for inverse polarity |
||||
|
||||
bl: backlight { |
||||
pwms = <&pwm 0 5000000 PWM_POLARITY_INVERTED>; |
||||
pwm-names = "backlight"; |
||||
}; |
||||
|
||||
2) PWM controller nodes |
||||
----------------------- |
||||
|
||||
PWM controller nodes must specify the number of cells used for the |
||||
specifier using the '#pwm-cells' property. |
||||
|
||||
An example PWM controller might look like this: |
||||
|
||||
pwm: pwm@7000a000 { |
||||
compatible = "nvidia,tegra20-pwm"; |
||||
reg = <0x7000a000 0x100>; |
||||
#pwm-cells = <2>; |
||||
}; |
||||
@ -0,0 +1,50 @@ |
||||
# |
||||
# Video drivers selection for rockchip soc. These configs only impact the |
||||
# compile process. You can surely check all the options. In this case, all the |
||||
# display driver will be compiled, but which drivers finally will be used is |
||||
# decided by device tree configuration. What's more, enable needed power for |
||||
# display by configure the device tree, and the vop driver will do the rest. |
||||
# |
||||
# Author: Eric Gao <eric.gao@rock-chips.com> |
||||
# |
||||
|
||||
menuconfig VIDEO_ROCKCHIP |
||||
bool "Enable Rockchip Video Support" |
||||
depends on DM_VIDEO |
||||
help |
||||
Rockchip SoCs provide video output capabilities for High-Definition |
||||
Multimedia Interface (HDMI), Low-voltage Differential Signalling |
||||
(LVDS), embedded DisplayPort (eDP) and Display Serial Interface |
||||
(DSI). This driver supports the on-chip video output device, and |
||||
targets the Rockchip RK3288 and RK3399. |
||||
|
||||
if VIDEO_ROCKCHIP |
||||
|
||||
config DISPLAY_ROCKCHIP_EDP |
||||
bool "EDP Port" |
||||
depends on VIDEO_ROCKCHIP |
||||
help |
||||
This enables Embedded DisplayPort(EDP) display support. |
||||
|
||||
config DISPLAY_ROCKCHIP_LVDS |
||||
bool "LVDS Port" |
||||
depends on VIDEO_ROCKCHIP |
||||
help |
||||
This enables Low-voltage Differential Signaling(LVDS) display |
||||
support. |
||||
|
||||
config DISPLAY_ROCKCHIP_HDMI |
||||
bool "HDMI port" |
||||
depends on VIDEO_ROCKCHIP |
||||
help |
||||
This enables High-Definition Multimedia Interface display support. |
||||
|
||||
config DISPLAY_ROCKCHIP_MIPI |
||||
bool "MIPI Port" |
||||
depends on VIDEO_ROCKCHIP |
||||
help |
||||
This enables Mobile Industry Processor Interface(MIPI) display |
||||
support. The mipi controller and dphy on rk3288& rk3399 support |
||||
16,18, 24 bits per pixel with upto 2k resolution ratio. |
||||
|
||||
endif |
||||
@ -0,0 +1,491 @@ |
||||
/*
|
||||
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd |
||||
* Author: Eric Gao <eric.gao@rock-chips.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk.h> |
||||
#include <display.h> |
||||
#include <dm.h> |
||||
#include <fdtdec.h> |
||||
#include <panel.h> |
||||
#include <regmap.h> |
||||
#include <syscon.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/hardware.h> |
||||
#include <asm/io.h> |
||||
#include <dm/uclass-internal.h> |
||||
#include <linux/kernel.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/cru_rk3399.h> |
||||
#include <asm/arch/grf_rk3399.h> |
||||
#include <asm/arch/rockchip_mipi_dsi.h> |
||||
#include <dt-bindings/clock/rk3288-cru.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Private information for rk mipi |
||||
* |
||||
* @regs: mipi controller address |
||||
* @grf: GRF register |
||||
* @panel: panel assined by device tree |
||||
* @ref_clk: reference clock for mipi dsi pll |
||||
* @sysclk: config clock for mipi dsi register |
||||
* @pix_clk: pixel clock for vop->dsi data transmission |
||||
* @phy_clk: mipi dphy output clock |
||||
* @txbyte_clk: clock for dsi->dphy high speed data transmission |
||||
* @txesc_clk: clock for tx esc mode |
||||
*/ |
||||
struct rk_mipi_priv { |
||||
void __iomem *regs; |
||||
struct rk3399_grf_regs *grf; |
||||
struct udevice *panel; |
||||
struct mipi_dsi *dsi; |
||||
u32 ref_clk; |
||||
u32 sys_clk; |
||||
u32 pix_clk; |
||||
u32 phy_clk; |
||||
u32 txbyte_clk; |
||||
u32 txesc_clk; |
||||
}; |
||||
|
||||
static int rk_mipi_read_timing(struct udevice *dev, |
||||
struct display_timing *timing) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), |
||||
0, timing); |
||||
if (ret) { |
||||
debug("%s: Failed to decode display timing (ret=%d)\n", |
||||
__func__, ret); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Register write function used only for mipi dsi controller. |
||||
* Parameter: |
||||
* @regs: mipi controller address |
||||
* @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can |
||||
* use define in rk_mipi.h directly for this parameter |
||||
* @val: value that will be write to specified bits of register |
||||
*/ |
||||
static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val) |
||||
{ |
||||
u32 dat; |
||||
u32 mask; |
||||
u32 offset = (reg >> OFFSET_SHIFT) & 0xff; |
||||
u32 bits = (reg >> BITS_SHIFT) & 0xff; |
||||
u64 addr = (reg >> ADDR_SHIFT) + regs; |
||||
|
||||
/* Mask for specifiled bits,the corresponding bits will be clear */ |
||||
mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); |
||||
|
||||
/* Make sure val in the available range */ |
||||
val &= ~(0xffffffff << bits); |
||||
|
||||
/* Get register's original val */ |
||||
dat = readl(addr); |
||||
|
||||
/* Clear specified bits */ |
||||
dat &= mask; |
||||
|
||||
/* Fill specified bits */ |
||||
dat |= val << offset; |
||||
|
||||
writel(dat, addr); |
||||
} |
||||
|
||||
static int rk_mipi_dsi_enable(struct udevice *dev, |
||||
const struct display_timing *timing) |
||||
{ |
||||
int node, timing_node; |
||||
int val; |
||||
struct rk_mipi_priv *priv = dev_get_priv(dev); |
||||
u64 regs = (u64)priv->regs; |
||||
struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); |
||||
u32 txbyte_clk = priv->txbyte_clk; |
||||
u32 txesc_clk = priv->txesc_clk; |
||||
|
||||
txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1); |
||||
|
||||
/* Select the video source */ |
||||
switch (disp_uc_plat->source_id) { |
||||
case VOP_B: |
||||
rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, |
||||
GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT); |
||||
break; |
||||
case VOP_L: |
||||
rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, |
||||
GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT); |
||||
break; |
||||
default: |
||||
debug("%s: Invalid VOP id\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
/* Set Controller as TX mode */ |
||||
val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT; |
||||
rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); |
||||
|
||||
/* Exit tx stop mode */ |
||||
val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT; |
||||
rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val); |
||||
|
||||
/* Disable turnequest */ |
||||
val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT; |
||||
rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val); |
||||
|
||||
/* Set Display timing parameter */ |
||||
rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); |
||||
rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); |
||||
rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ |
||||
+ timing->hback_porch.typ + timing->hactive.typ |
||||
+ timing->hfront_porch.typ)); |
||||
rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); |
||||
rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); |
||||
rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ); |
||||
rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ); |
||||
|
||||
/* Set Signal Polarity */ |
||||
val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0; |
||||
rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val); |
||||
|
||||
val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0; |
||||
rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val); |
||||
|
||||
val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0; |
||||
rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val); |
||||
|
||||
val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0; |
||||
rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val); |
||||
|
||||
/* Set video mode */ |
||||
rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE); |
||||
|
||||
/* Set video mode transmission type as burst mode */ |
||||
rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE); |
||||
|
||||
/* Set pix num in a video package */ |
||||
rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0); |
||||
|
||||
/* Set dpi color coding depth 24 bit */ |
||||
timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), |
||||
"display-timings"); |
||||
node = fdt_first_subnode(gd->fdt_blob, timing_node); |
||||
val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1); |
||||
switch (val) { |
||||
case 16: |
||||
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1); |
||||
break; |
||||
case 24: |
||||
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); |
||||
break; |
||||
case 30: |
||||
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT); |
||||
break; |
||||
default: |
||||
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); |
||||
} |
||||
/* Enable low power mode */ |
||||
rk_mipi_dsi_write(regs, LP_CMD_EN, 1); |
||||
rk_mipi_dsi_write(regs, LP_HFP_EN, 1); |
||||
rk_mipi_dsi_write(regs, LP_VACT_EN, 1); |
||||
rk_mipi_dsi_write(regs, LP_VFP_EN, 1); |
||||
rk_mipi_dsi_write(regs, LP_VBP_EN, 1); |
||||
rk_mipi_dsi_write(regs, LP_VSA_EN, 1); |
||||
|
||||
/* Division for timeout counter clk */ |
||||
rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a); |
||||
|
||||
/* Tx esc clk division from txbyte clk */ |
||||
rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk); |
||||
|
||||
/* Timeout count for hs<->lp transation between Line period */ |
||||
rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8); |
||||
|
||||
/* Phy State transfer timing */ |
||||
rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32); |
||||
rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1); |
||||
rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14); |
||||
rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10); |
||||
rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710); |
||||
|
||||
/* Power on */ |
||||
rk_mipi_dsi_write(regs, SHUTDOWNZ, 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* rk mipi dphy write function. It is used to write test data to dphy */ |
||||
static void rk_mipi_phy_write(u32 regs, unsigned char test_code, |
||||
unsigned char *test_data, unsigned char size) |
||||
{ |
||||
int i = 0; |
||||
|
||||
/* Write Test code */ |
||||
rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); |
||||
rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code); |
||||
rk_mipi_dsi_write(regs, PHY_TESTEN, 1); |
||||
rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); |
||||
rk_mipi_dsi_write(regs, PHY_TESTEN, 0); |
||||
|
||||
/* Write Test data */ |
||||
for (i = 0; i < size; i++) { |
||||
rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); |
||||
rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]); |
||||
rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Mipi dphy config function. Calculate the suitable prediv, feedback div, |
||||
* fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate, |
||||
* and then enable phy. |
||||
*/ |
||||
static int rk_mipi_phy_enable(struct udevice *dev) |
||||
{ |
||||
int i; |
||||
struct rk_mipi_priv *priv = dev_get_priv(dev); |
||||
u64 regs = (u64)priv->regs; |
||||
u64 fbdiv; |
||||
u64 prediv = 1; |
||||
u32 max_fbdiv = 512; |
||||
u32 max_prediv, min_prediv; |
||||
u64 ddr_clk = priv->phy_clk; |
||||
u32 refclk = priv->ref_clk; |
||||
u32 remain = refclk; |
||||
unsigned char test_data[2] = {0}; |
||||
|
||||
int freq_rang[][2] = { |
||||
{90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01}, |
||||
{140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12}, |
||||
{200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23}, |
||||
{270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15}, |
||||
{400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07}, |
||||
{600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09}, |
||||
{800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a}, |
||||
{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, |
||||
{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, |
||||
{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} |
||||
}; |
||||
|
||||
/* Shutdown mode */ |
||||
rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0); |
||||
rk_mipi_dsi_write(regs, PHY_RSTZ, 0); |
||||
rk_mipi_dsi_write(regs, PHY_TESTCLR, 1); |
||||
|
||||
/* Pll locking */ |
||||
rk_mipi_dsi_write(regs, PHY_TESTCLR, 0); |
||||
|
||||
/* config cp and lfp */ |
||||
test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; |
||||
rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1); |
||||
|
||||
test_data[0] = 0x8; |
||||
rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1); |
||||
|
||||
test_data[0] = 0x80 | 0x40; |
||||
rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1); |
||||
|
||||
/* select the suitable value for fsfreqrang reg */ |
||||
for (i = 0; i < ARRAY_SIZE(freq_rang); i++) { |
||||
if (ddr_clk / (MHz) >= freq_rang[i][0]) |
||||
break; |
||||
} |
||||
if (i == ARRAY_SIZE(freq_rang)) { |
||||
debug("%s: Dphy freq out of range!\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
test_data[0] = freq_rang[i][1] << 1; |
||||
rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1); |
||||
|
||||
/*
|
||||
* Calculate the best ddrclk and it's corresponding div value. If the |
||||
* given pixelclock is great than 250M, ddrclk will be fix 1500M. |
||||
* Otherwise, |
||||
* it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz |
||||
* according to spec. |
||||
*/ |
||||
max_prediv = (refclk / (5 * MHz)); |
||||
min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1); |
||||
|
||||
debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv, |
||||
min_prediv); |
||||
|
||||
if (max_prediv < min_prediv) { |
||||
debug("%s: Invalid refclk value\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
/* Calculate the best refclk and feedback division value for dphy pll */ |
||||
for (i = min_prediv; i < max_prediv; i++) { |
||||
if ((ddr_clk * i % refclk < remain) && |
||||
(ddr_clk * i / refclk) < max_fbdiv) { |
||||
prediv = i; |
||||
remain = ddr_clk * i % refclk; |
||||
} |
||||
} |
||||
fbdiv = ddr_clk * prediv / refclk; |
||||
ddr_clk = refclk * fbdiv / prediv; |
||||
priv->phy_clk = ddr_clk; |
||||
|
||||
debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n", |
||||
__func__, refclk, prediv, fbdiv, ddr_clk); |
||||
|
||||
/* config prediv and feedback reg */ |
||||
test_data[0] = prediv - 1; |
||||
rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1); |
||||
test_data[0] = (fbdiv - 1) & 0x1f; |
||||
rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1); |
||||
test_data[0] = (fbdiv - 1) >> 5 | 0x80; |
||||
rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1); |
||||
test_data[0] = 0x30; |
||||
rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1); |
||||
|
||||
/* rest config */ |
||||
test_data[0] = 0x4d; |
||||
rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1); |
||||
|
||||
test_data[0] = 0x3d; |
||||
rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1); |
||||
|
||||
test_data[0] = 0xdf; |
||||
rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1); |
||||
|
||||
test_data[0] = 0x7; |
||||
rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1); |
||||
|
||||
test_data[0] = 0x80 | 0x7; |
||||
rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1); |
||||
|
||||
test_data[0] = 0x80 | 15; |
||||
rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME, |
||||
test_data, 1); |
||||
test_data[0] = 0x80 | 85; |
||||
rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME, |
||||
test_data, 1); |
||||
test_data[0] = 0x40 | 10; |
||||
rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME, |
||||
test_data, 1); |
||||
|
||||
/* enter into stop mode */ |
||||
rk_mipi_dsi_write(regs, N_LANES, 0x03); |
||||
rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1); |
||||
rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1); |
||||
rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1); |
||||
rk_mipi_dsi_write(regs, PHY_RSTZ, 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* This function is called by rk_display_init() using rk_mipi_dsi_enable() and |
||||
* rk_mipi_phy_enable() to initialize mipi controller and dphy. If success, |
||||
* enable backlight. |
||||
*/ |
||||
static int rk_display_enable(struct udevice *dev, int panel_bpp, |
||||
const struct display_timing *timing) |
||||
{ |
||||
int ret; |
||||
struct rk_mipi_priv *priv = dev_get_priv(dev); |
||||
|
||||
/* Fill the mipi controller parameter */ |
||||
priv->ref_clk = 24 * MHz; |
||||
priv->sys_clk = priv->ref_clk; |
||||
priv->pix_clk = timing->pixelclock.typ; |
||||
priv->phy_clk = priv->pix_clk * 6; |
||||
priv->txbyte_clk = priv->phy_clk / 8; |
||||
priv->txesc_clk = 20 * MHz; |
||||
|
||||
/* Config and enable mipi dsi according to timing */ |
||||
ret = rk_mipi_dsi_enable(dev, timing); |
||||
if (ret) { |
||||
debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n", |
||||
__func__, ret); |
||||
return ret; |
||||
} |
||||
|
||||
/* Config and enable mipi phy */ |
||||
ret = rk_mipi_phy_enable(dev); |
||||
if (ret) { |
||||
debug("%s: rk_mipi_phy_enable() failed (err=%d)\n", |
||||
__func__, ret); |
||||
return ret; |
||||
} |
||||
|
||||
/* Enable backlight */ |
||||
ret = panel_enable_backlight(priv->panel); |
||||
if (ret) { |
||||
debug("%s: panel_enable_backlight() failed (err=%d)\n", |
||||
__func__, ret); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int rk_mipi_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct rk_mipi_priv *priv = dev_get_priv(dev); |
||||
|
||||
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
||||
if (priv->grf <= 0) { |
||||
debug("%s: Get syscon grf failed (ret=%llu)\n", |
||||
__func__, (u64)priv->grf); |
||||
return -ENXIO; |
||||
} |
||||
priv->regs = (void *)dev_get_addr(dev); |
||||
if (priv->regs <= 0) { |
||||
debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__, |
||||
(u64)priv->regs); |
||||
return -ENXIO; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Probe function: check panel existence and readingit's timing. Then config |
||||
* mipi dsi controller and enable it according to the timing parameter. |
||||
*/ |
||||
static int rk_mipi_probe(struct udevice *dev) |
||||
{ |
||||
int ret; |
||||
struct rk_mipi_priv *priv = dev_get_priv(dev); |
||||
|
||||
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel", |
||||
&priv->panel); |
||||
if (ret) { |
||||
debug("%s: Can not find panel (err=%d)\n", __func__, ret); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct dm_display_ops rk_mipi_dsi_ops = { |
||||
.read_timing = rk_mipi_read_timing, |
||||
.enable = rk_display_enable, |
||||
}; |
||||
|
||||
static const struct udevice_id rk_mipi_dsi_ids[] = { |
||||
{ .compatible = "rockchip,rk3399_mipi_dsi" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(rk_mipi_dsi) = { |
||||
.name = "rk_mipi_dsi", |
||||
.id = UCLASS_DISPLAY, |
||||
.of_match = rk_mipi_dsi_ids, |
||||
.ofdata_to_platdata = rk_mipi_ofdata_to_platdata, |
||||
.probe = rk_mipi_probe, |
||||
.ops = &rk_mipi_dsi_ops, |
||||
.priv_auto_alloc_size = sizeof(struct rk_mipi_priv), |
||||
}; |
||||
@ -0,0 +1,53 @@ |
||||
#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ |
||||
#define __DT_BINDINGS_POWER_RK3399_POWER_H__ |
||||
|
||||
/* VD_CORE_L */ |
||||
#define RK3399_PD_A53_L0 0 |
||||
#define RK3399_PD_A53_L1 1 |
||||
#define RK3399_PD_A53_L2 2 |
||||
#define RK3399_PD_A53_L3 3 |
||||
#define RK3399_PD_SCU_L 4 |
||||
|
||||
/* VD_CORE_B */ |
||||
#define RK3399_PD_A72_B0 5 |
||||
#define RK3399_PD_A72_B1 6 |
||||
#define RK3399_PD_SCU_B 7 |
||||
|
||||
/* VD_LOGIC */ |
||||
#define RK3399_PD_TCPD0 8 |
||||
#define RK3399_PD_TCPD1 9 |
||||
#define RK3399_PD_CCI 10 |
||||
#define RK3399_PD_CCI0 11 |
||||
#define RK3399_PD_CCI1 12 |
||||
#define RK3399_PD_PERILP 13 |
||||
#define RK3399_PD_PERIHP 14 |
||||
#define RK3399_PD_VIO 15 |
||||
#define RK3399_PD_VO 16 |
||||
#define RK3399_PD_VOPB 17 |
||||
#define RK3399_PD_VOPL 18 |
||||
#define RK3399_PD_ISP0 19 |
||||
#define RK3399_PD_ISP1 20 |
||||
#define RK3399_PD_HDCP 21 |
||||
#define RK3399_PD_GMAC 22 |
||||
#define RK3399_PD_EMMC 23 |
||||
#define RK3399_PD_USB3 24 |
||||
#define RK3399_PD_EDP 25 |
||||
#define RK3399_PD_GIC 26 |
||||
#define RK3399_PD_SD 27 |
||||
#define RK3399_PD_SDIOAUDIO 28 |
||||
#define RK3399_PD_ALIVE 29 |
||||
|
||||
/* VD_CENTER */ |
||||
#define RK3399_PD_CENTER 30 |
||||
#define RK3399_PD_VCODEC 31 |
||||
#define RK3399_PD_VDU 32 |
||||
#define RK3399_PD_RGA 33 |
||||
#define RK3399_PD_IEP 34 |
||||
|
||||
/* VD_GPU */ |
||||
#define RK3399_PD_GPU 35 |
||||
|
||||
/* VD_PMU */ |
||||
#define RK3399_PD_PMU 36 |
||||
|
||||
#endif |
||||
@ -1,77 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Google, Inc |
||||
* Written by Simon Glass <sjg@chromium.org> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _PMIC_RK808_H_ |
||||
#define _PMIC_RK808_H_ |
||||
|
||||
enum { |
||||
REG_DCDC_EN = 0x23, |
||||
REG_LDO_EN, |
||||
REG_SLEEP_SET_OFF1, |
||||
REG_SLEEP_SET_OFF2, |
||||
REG_DCDC_UV_STS, |
||||
|
||||
REG_DCDC_UV_ACT, |
||||
REG_LDO_UV_STS, |
||||
REG_LDO_UV_ACT, |
||||
REG_DCDC_PG, |
||||
REG_LDO_PG, |
||||
REG_VOUT_MON_TDB, |
||||
REG_BUCK1_CONFIG, |
||||
REG_BUCK1_ON_VSEL, |
||||
|
||||
REG_BUCK1_SLP_VSEL, |
||||
REG_BUCK1_DVS_VSEL, |
||||
REG_BUCK2_CONFIG, |
||||
REG_BUCK2_ON_VSEL, |
||||
REG_BUCK2_SLP_VSEL, |
||||
REG_BUCK2_DVS_VSEL, |
||||
REG_BUCK3_CONFIG, |
||||
REG_BUCK4_CONFIG, |
||||
|
||||
REG_BUCK4_ON_VSEL, |
||||
REG_BUCK4_SLP_VSEL, |
||||
LDO1_ON_VSEL = 0x3b, |
||||
LDO1_SLP_VSEL, |
||||
LDO2_ON_VSEL, |
||||
LDO2_SLP_VSEL, |
||||
LDO3_ON_VSEL, |
||||
|
||||
LDO3_SLP_VSEL, |
||||
LDO4_ON_VSEL, |
||||
LDO4_SLP_VSEL, |
||||
LDO5_ON_VSEL, |
||||
LDO5_SLP_VSEL, |
||||
LDO6_ON_VSEL, |
||||
LDO6_SLP_VSEL, |
||||
LDO7_ON_VSEL, |
||||
|
||||
LDO7_SLP_VSEL, |
||||
LDO8_ON_VSEL, |
||||
LDO8_SLP_VSEL, |
||||
DEVCTRL, |
||||
INT_STS1, |
||||
INT_STS_MSK1, |
||||
INT_STS2, |
||||
INT_STS_MSK2, |
||||
IO_POL, |
||||
|
||||
/* Not sure what this does */ |
||||
DCDC_ILMAX = 0x90, |
||||
|
||||
RK808_NUM_OF_REGS, |
||||
}; |
||||
|
||||
struct rk808_reg_table { |
||||
char *name; |
||||
u8 reg_ctl; |
||||
u8 reg_vol; |
||||
}; |
||||
|
||||
int rk808_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); |
||||
|
||||
#endif |
||||
@ -0,0 +1,193 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Google, Inc |
||||
* Written by Simon Glass <sjg@chromium.org> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _PMIC_RK8XX_H_ |
||||
#define _PMIC_RK8XX_H_ |
||||
|
||||
enum { |
||||
REG_SECONDS = 0x00, |
||||
REG_MINUTES, |
||||
REG_HOURS, |
||||
REG_DAYS, |
||||
REG_MONTHS, |
||||
REG_YEARS, |
||||
REG_WEEKS, |
||||
REG_ALARM_SECONDS, |
||||
REG_ALARM_MINUTES, |
||||
REG_ALARM_HOURS, |
||||
REG_ALARM_DAYS, |
||||
REG_ALARM_MONTHS, |
||||
REG_ALARM_YEARS, |
||||
|
||||
REG_RTC_CTRL = 0x10, |
||||
REG_RTC_STATUS, |
||||
REG_RTC_INT, |
||||
REG_RTC_COMP_LSB, |
||||
REG_RTC_COMP_MSB, |
||||
|
||||
ID_MSB = 0x17, |
||||
ID_LSB, |
||||
|
||||
REG_CLK32OUT = 0x20, |
||||
REG_VB_MON, |
||||
REG_THERMAL, |
||||
REG_DCDC_EN, |
||||
REG_LDO_EN, |
||||
REG_SLEEP_SET_OFF1, |
||||
REG_SLEEP_SET_OFF2, |
||||
REG_DCDC_UV_STS, |
||||
REG_DCDC_UV_ACT, |
||||
REG_LDO_UV_STS, |
||||
REG_LDO_UV_ACT, |
||||
REG_DCDC_PG, |
||||
REG_LDO_PG, |
||||
REG_VOUT_MON_TDB, |
||||
REG_BUCK1_CONFIG, |
||||
REG_BUCK1_ON_VSEL, |
||||
REG_BUCK1_SLP_VSEL, |
||||
REG_BUCK1_DVS_VSEL, |
||||
REG_BUCK2_CONFIG, |
||||
REG_BUCK2_ON_VSEL, |
||||
REG_BUCK2_SLP_VSEL, |
||||
REG_BUCK2_DVS_VSEL, |
||||
REG_BUCK3_CONFIG, |
||||
REG_BUCK4_CONFIG, |
||||
REG_BUCK4_ON_VSEL, |
||||
REG_BUCK4_SLP_VSEL, |
||||
REG_BOOST_CONFIG_REG, |
||||
REG_LDO1_ON_VSEL, |
||||
REG_LDO1_SLP_VSEL, |
||||
REG_LDO2_ON_VSEL, |
||||
REG_LDO2_SLP_VSEL, |
||||
REG_LDO3_ON_VSEL, |
||||
REG_LDO3_SLP_VSEL, |
||||
REG_LDO4_ON_VSEL, |
||||
REG_LDO4_SLP_VSEL, |
||||
REG_LDO5_ON_VSEL, |
||||
REG_LDO5_SLP_VSEL, |
||||
REG_LDO6_ON_VSEL, |
||||
REG_LDO6_SLP_VSEL, |
||||
REG_LDO7_ON_VSEL, |
||||
REG_LDO7_SLP_VSEL, |
||||
REG_LDO8_ON_VSEL, |
||||
REG_LDO8_SLP_VSEL, |
||||
REG_DEVCTRL, |
||||
REG_INT_STS1, |
||||
REG_INT_STS_MSK1, |
||||
REG_INT_STS2, |
||||
REG_INT_STS_MSK2, |
||||
REG_IO_POL, |
||||
REG_OTP_VDD_EN, |
||||
REG_H5V_EN, |
||||
REG_SLEEP_SET_OFF, |
||||
REG_BOOST_LDO9_ON_VSEL, |
||||
REG_BOOST_LDO9_SLP_VSEL, |
||||
REG_BOOST_CTRL, |
||||
|
||||
/* Not sure what this does */ |
||||
REG_DCDC_ILMAX = 0x90, |
||||
REG_CHRG_COMP = 0x9a, |
||||
REG_SUP_STS = 0xa0, |
||||
REG_USB_CTRL, |
||||
REG1_CHRG_CTRL, |
||||
REG2_CHRG_CTRL, |
||||
REG3_CHRG_CTRL, |
||||
REG_BAT_CTRL, |
||||
REG_BAT_HTS_TS1, |
||||
REG_BAT_LTS_TS1, |
||||
REG_BAT_HTS_TS2, |
||||
REG_BAT_LTS_TS2, |
||||
REG_TS_CTRL, |
||||
REG_ADC_CTRL, |
||||
REG_ON_SOURCE, |
||||
REG_OFF_SOURCE, |
||||
REG_GGCON, |
||||
REG_GGSTS, |
||||
REG_FRAME_SMP_INTERV, |
||||
REG_AUTO_SLP_CUR_THR, |
||||
REG3_GASCNT_CAL, |
||||
REG2_GASCNT_CAL, |
||||
REG1_GASCNT_CAL, |
||||
REG0_GASCNT_CAL, |
||||
REG3_GASCNT, |
||||
REG2_GASCNT, |
||||
REG1_GASCNT, |
||||
REG0_GASCNT, |
||||
REGH_BAT_CUR_AVG, |
||||
REGL_BAT_CUR_AVG, |
||||
REGH_TS1_ADC, |
||||
REGL_TS1_ADC, |
||||
REGH_TS2_ADC, |
||||
REGL_TS2_ADC, |
||||
REGH_BAT_OCV, |
||||
REGL_BAT_OCV, |
||||
REGH_BAT_VOL, |
||||
REGL_BAT_VOL, |
||||
REGH_RELAX_ENTRY_THRES, |
||||
REGL_RELAX_ENTRY_THRES, |
||||
REGH_RELAX_EXIT_THRES, |
||||
REGL_RELAX_EXIT_THRES, |
||||
REGH_RELAX_VOL1, |
||||
REGL_RELAX_VOL1, |
||||
REGH_RELAX_VOL2, |
||||
REGL_RELAX_VOL2, |
||||
REGH_BAT_CUR_R_CALC, |
||||
REGL_BAT_CUR_R_CALC, |
||||
REGH_BAT_VOL_R_CALC, |
||||
REGL_BAT_VOL_R_CALC, |
||||
REGH_CAL_OFFSET, |
||||
REGL_CAL_OFFSET, |
||||
REG_NON_ACT_TIMER_CNT, |
||||
REGH_VCALIB0, |
||||
REGL_VCALIB0, |
||||
REGH_VCALIB1, |
||||
REGL_VCALIB1, |
||||
REGH_IOFFSET, |
||||
REGL_IOFFSET, |
||||
REG_SOC, |
||||
REG3_REMAIN_CAP, |
||||
REG2_REMAIN_CAP, |
||||
REG1_REMAIN_CAP, |
||||
REG0_REMAIN_CAP, |
||||
REG_UPDAT_LEVE, |
||||
REG3_NEW_FCC, |
||||
REG2_NEW_FCC, |
||||
REG1_NEW_FCC, |
||||
REG0_NEW_FCC, |
||||
REG_NON_ACT_TIMER_CNT_SAVE, |
||||
REG_OCV_VOL_VALID, |
||||
REG_REBOOT_CNT, |
||||
REG_POFFSET, |
||||
REG_MISC_MARK, |
||||
REG_HALT_CNT, |
||||
REGH_CALC_REST, |
||||
REGL_CALC_REST, |
||||
SAVE_DATA19, |
||||
RK808_NUM_OF_REGS, |
||||
}; |
||||
|
||||
enum { |
||||
RK805_ID = 0x8050, |
||||
RK808_ID = 0x0000, |
||||
RK818_ID = 0x8180, |
||||
}; |
||||
|
||||
#define RK8XX_ID_MSK 0xfff0 |
||||
|
||||
struct rk8xx_reg_table { |
||||
char *name; |
||||
u8 reg_ctl; |
||||
u8 reg_vol; |
||||
}; |
||||
|
||||
struct rk8xx_priv { |
||||
int variant; |
||||
}; |
||||
|
||||
int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue