The patch adds support for Freescale ls1021a-iot board. Signed-off-by: Feng Li <feng.li_2@nxp.com> [YS: rewrite commit message, fix whitespace in Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>master
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/* |
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* Freescale ls1021a IOT board device tree source |
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* |
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/dts-v1/; |
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#include "ls1021a-iot.dtsi" |
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|
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/ { |
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chosen { |
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stdout-path = &uart0; |
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}; |
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}; |
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/* |
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* Freescale ls1021a IOT board device tree source |
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* |
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include "ls1021a.dtsi" |
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/ { |
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model = "LS1021A IOT Board"; |
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aliases { |
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enet2_rgmii_phy = &rgmii_phy1; |
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enet0_sgmii_phy = &sgmii_phy2; |
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enet1_sgmii_phy = &sgmii_phy0; |
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spi0 = &qspi; |
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spi1 = &dspi1; |
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}; |
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}; |
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&qspi { |
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bus-num = <0>; |
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status = "okay"; |
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qflash0: n25q128a13@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <20000000>; |
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reg = <0>; |
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}; |
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}; |
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|
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&dspi1 { |
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bus-num = <0>; |
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status = "okay"; |
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dspiflash: at26df081a@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <16000000>; |
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spi-cpol; |
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spi-cpha; |
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reg = <0>; |
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}; |
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}; |
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|
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&i2c0 { |
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status = "okay"; |
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}; |
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&i2c1 { |
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status = "okay"; |
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}; |
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&ifc { |
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#address-cells = <2>; |
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#size-cells = <1>; |
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/* NOR Flash on board */ |
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ranges = <0x0 0x0 0x60000000 0x08000000>; |
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status = "okay"; |
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nor@0,0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "cfi-flash"; |
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reg = <0x0 0x0 0x8000000>; |
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bank-width = <2>; |
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device-width = <1>; |
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}; |
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}; |
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&lpuart0 { |
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status = "okay"; |
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}; |
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&mdio0 { |
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sgmii_phy0: ethernet-phy@0 { |
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reg = <0x0>; |
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}; |
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rgmii_phy1: ethernet-phy@1 { |
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reg = <0x1>; |
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}; |
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sgmii_phy2: ethernet-phy@2 { |
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reg = <0x2>; |
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}; |
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tbi1: tbi-phy@1f { |
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reg = <0x1f>; |
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device_type = "tbi-phy"; |
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}; |
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}; |
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&uart0 { |
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status = "okay"; |
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}; |
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&uart1 { |
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status = "okay"; |
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}; |
@ -0,0 +1,15 @@ |
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if TARGET_LS1021AIOT |
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config SYS_BOARD |
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default "ls1021aiot" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_SOC |
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default "ls102xa" |
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config SYS_CONFIG_NAME |
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default "ls1021aiot" |
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endif |
@ -0,0 +1,7 @@ |
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LS1021AIOT BOARD |
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M: Feng Li <feng.li_2@nxp.com> |
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S: Maintained |
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F: board/freescale/ls1021aiot/ |
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F: include/configs/ls1021aiot.h |
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F: configs/ls1021aiot_sdcard_defconfig |
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F: configs/ls1021aiot_qspi_defconfig |
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#
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# Copyright 2016 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += ls1021aiot.o
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obj-$(CONFIG_FSL_DCU_FB) += dcu.o
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obj-$(CONFIG_ARMV7_PSCI) += psci.o
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@ -0,0 +1,58 @@ |
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Overview |
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-------- |
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The LS1021A-IOT is a Freescale reference board that hosts |
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the LS1021A SoC. |
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LS1021AIOT board Overview |
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------------------------- |
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- DDR Controller |
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- Supports 1GB un-buffered DDR3L SDRAM discrete |
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devices(32-bit bus) with 4 bit ECC |
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- DDR power supplies 1.35V to all devices with |
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automatic tracking of VTT |
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- Soldered DDR chip |
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- Supprot one fixed speed |
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- Ethernet |
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- Two on-board SGMII 10/100/1G ethernet ports |
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- One Gbit Etherent RGMII interface to 4-ports switch |
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with 4x 10/100/1000 RJ145 ports |
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- CPLD |
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- 8-bit registers in CPLD for system configuration |
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- connected to IFC_AD[0:7] |
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- Power Supplies |
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- 12V@5A DC |
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- SDHC |
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- SDHC port connects directly to a full 8-bit SD/MMC slot |
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- Support for SDIO devices |
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- USB |
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- Two on-board USB 3.0 |
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- One on-board USB k22 |
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- PCIe |
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- Two MiniPCIe Solts |
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- SATA |
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- Support SATA Connector |
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- AUDIO |
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- AUDIO in and out |
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- I/O Expansion |
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- Arduino Shield Connector |
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- Port0 - CAN/GPIO/Flextimer |
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- Port1 - GPIO/CPLD Expansion |
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- Port2 - SPI/I2C/UART |
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Memory map |
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----------- |
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The addresses in brackets are physical addresses. |
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Start Address End Address Description Size |
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0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB |
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0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB |
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0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB |
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0x00_6000_0000 0x00_6000_FFFF CPLD 64K |
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0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB |
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Boot description |
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----------------- |
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LS1021A-IOT support two ways of boot: |
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Qspi boot and SD boot |
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The board doesn't support boot from another |
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source without changing any switch/jumper. |
@ -0,0 +1,47 @@ |
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/*
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* |
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* FSL DCU Framebuffer driver |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <fsl_dcu_fb.h> |
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#include "div64.h" |
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#include "../common/dcu_sii9022a.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned int dcu_set_pixel_clock(unsigned int pixclock) |
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{ |
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unsigned long long div; |
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div = (unsigned long long)(gd->bus_clk / 1000); |
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div *= (unsigned long long)pixclock; |
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do_div(div, 1000000000); |
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return div; |
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} |
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int platform_dcu_init(unsigned int xres, unsigned int yres, |
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const char *port, |
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struct fb_videomode *dcu_fb_videomode) |
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{ |
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const char *name; |
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unsigned int pixel_format; |
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if (strncmp(port, "twr_lcd", 4) == 0) { |
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name = "TWR_LCD_RGB card"; |
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} else { |
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name = "HDMI"; |
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dcu_set_dvi_encoder(dcu_fb_videomode); |
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} |
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printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); |
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pixel_format = 32; |
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fsl_dcu_init(xres, yres, pixel_format); |
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return 0; |
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} |
@ -0,0 +1,259 @@ |
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/*
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/immap_ls102xa.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/fsl_serdes.h> |
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#include <asm/arch/ls102xa_stream_id.h> |
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#include <asm/arch/ls102xa_devdis.h> |
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#include <asm/arch/ls102xa_soc.h> |
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#include <asm/arch/ls102xa_sata.h> |
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#include <fsl_csu.h> |
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#include <fsl_esdhc.h> |
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#include <fsl_immap.h> |
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#include <netdev.h> |
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#include <fsl_mdio.h> |
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#include <tsec.h> |
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#include <spl.h> |
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#include <fsl_validate.h> |
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#include "../common/sleep.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#define DDR_SIZE 0x40000000 |
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int checkboard(void) |
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{ |
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puts("Board: LS1021AIOT\n"); |
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#ifndef CONFIG_QSPI_BOOT |
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struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; |
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u32 cpldrev; |
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cpldrev = in_be32(&dcfg->gpporcr1); |
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printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & |
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0xf)); |
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#endif |
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return 0; |
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} |
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void ddrmc_init(void) |
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{ |
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struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; |
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u32 temp_sdram_cfg, tmp; |
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); |
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out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); |
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out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); |
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out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); |
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out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); |
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out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); |
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out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); |
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out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); |
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out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); |
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out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); |
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out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); |
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out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); |
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out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); |
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out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); |
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out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); |
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out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); |
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out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); |
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out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); |
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out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); |
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out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); |
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out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); |
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/* DDR erratum A-009942 */ |
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tmp = in_be32(&ddr->debug[28]); |
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out_be32(&ddr->debug[28], tmp | 0x0070006f); |
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udelay(500); |
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temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); |
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); |
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} |
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int dram_init(void) |
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{ |
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#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
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ddrmc_init(); |
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#endif |
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gd->ram_size = DDR_SIZE; |
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return 0; |
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} |
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#ifdef CONFIG_FSL_ESDHC |
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struct fsl_esdhc_cfg esdhc_cfg[1] = { |
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{CONFIG_SYS_FSL_ESDHC_ADDR}, |
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}; |
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int board_mmc_init(bd_t *bis) |
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{ |
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
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} |
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#endif |
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#ifdef CONFIG_TSEC_ENET |
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int board_eth_init(bd_t *bis) |
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{ |
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struct fsl_pq_mdio_info mdio_info; |
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struct tsec_info_struct tsec_info[4]; |
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int num = 0; |
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#ifdef CONFIG_TSEC1 |
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SET_STD_TSEC_INFO(tsec_info[num], 1); |
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if (is_serdes_configured(SGMII_TSEC1)) { |
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puts("eTSEC1 is in sgmii mode.\n"); |
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tsec_info[num].flags |= TSEC_SGMII; |
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} |
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num++; |
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#endif |
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#ifdef CONFIG_TSEC2 |
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SET_STD_TSEC_INFO(tsec_info[num], 2); |
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if (is_serdes_configured(SGMII_TSEC2)) { |
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puts("eTSEC2 is in sgmii mode.\n"); |
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tsec_info[num].flags |= TSEC_SGMII; |
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} |
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num++; |
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#endif |
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if (!num) { |
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printf("No TSECs initialized\n"); |
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return 0; |
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} |
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; |
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mdio_info.name = DEFAULT_MII_NAME; |
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fsl_pq_mdio_init(bis, &mdio_info); |
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tsec_eth_init(bis, tsec_info, num); |
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return pci_eth_init(bis); |
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} |
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#endif |
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int board_early_init_f(void) |
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{ |
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
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#ifdef CONFIG_TSEC_ENET |
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/* clear BD & FR bits for BE BD's and frame data */ |
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clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); |
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); |
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#endif |
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arch_soc_init(); |
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return 0; |
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} |
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#ifdef CONFIG_SPL_BUILD |
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void board_init_f(ulong dummy) |
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{ |
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/* Clear the BSS */ |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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get_clocks(); |
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preloader_console_init(); |
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dram_init(); |
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/* Allow OCRAM access permission as R/W */ |
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
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enable_layerscape_ns_access(); |
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#endif |
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board_init_r(NULL, 0); |
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} |
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#endif |
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int board_init(void) |
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{ |
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#ifndef CONFIG_SYS_FSL_NO_SERDES |
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fsl_serdes_init(); |
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#endif |
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ls102xa_smmu_stream_id_init(); |
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
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enable_layerscape_ns_access(); |
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#endif |
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return 0; |
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} |
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#ifdef CONFIG_BOARD_LATE_INIT |
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int board_late_init(void) |
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{ |
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#ifdef CONFIG_SCSI_AHCI_PLAT |
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ls1021a_sata_init(); |
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#endif |
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return 0; |
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} |
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#endif |
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#if defined(CONFIG_MISC_INIT_R) |
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int misc_init_r(void) |
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{ |
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#ifdef CONFIG_FSL_DEVICE_DISABLE |
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device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); |
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#endif |
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#ifdef CONFIG_FSL_CAAM |
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return sec_init(); |
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#endif |
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} |
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#endif |
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int ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup(blob, bd); |
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#ifdef CONFIG_PCI |
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ft_pci_setup(blob, bd); |
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#endif |
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return 0; |
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} |
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void flash_write16(u16 val, void *addr) |
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{ |
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); |
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__raw_writew(shftval, addr); |
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} |
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u16 flash_read16(void *addr) |
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{ |
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u16 val = __raw_readw(addr); |
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); |
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} |
@ -0,0 +1,14 @@ |
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#PBI commands |
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09570200 ffffffff |
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09570158 00000300 |
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8940007c 21f47300 |
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#Configure Scratch register |
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09ee0200 10000000 |
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#Configure alternate space |
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09570158 00001000 |
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#Flush PBL data |
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096100c0 000FFFFF |
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09ea085c 00502880 |
@ -0,0 +1,27 @@ |
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#PBL preamble and RCW header |
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aa55aa55 01ee0100 |
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# serdes protocol |
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#Default with 2 x SGMII (no SATA) |
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0608000a 00000000 00000000 00000000 |
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20000000 08407900 60025a00 21046000 |
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00000000 00000000 00000000 20038000 |
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20024800 881b1340 00000000 00000000 |
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#SATA set-up |
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#0608000a 00000000 00000000 00000000 |
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#70000000 08007900 60025a00 21046000 |
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#00000000 00000000 00000000 20038000 |
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#20024800 881b1340 00000000 00000000 |
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#HDMI set-up |
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#0608000a 00000000 00000000 00000000 |
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#20000000 08407900 60025a00 21046000 |
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#00000000 00000000 00000000 20038000 |
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#00000000 881b1340 00000000 00000000 |
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#QE testing |
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#0608000a 00000000 00000000 00000000 |
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#20000000 08407900 60025a00 21046000 |
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#00000000 00000000 00000000 00038000 |
||||
#20094800 881b1340 00000000 00000000 |
@ -0,0 +1,28 @@ |
||||
/* |
||||
* Copyright 2016 NXP Semiconductor. |
||||
* Author: Feng Li <feng.li_2@nxp.com>
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <linux/linkage.h> |
||||
|
||||
#include <asm/armv7.h> |
||||
#include <asm/psci.h> |
||||
|
||||
.pushsection ._secure.text, "ax" |
||||
|
||||
.arch_extension sec
|
||||
|
||||
.align 5
|
||||
|
||||
.globl psci_system_off
|
||||
psci_system_off: |
||||
1: wfi |
||||
b 1b |
||||
|
||||
.globl psci_text_end
|
||||
psci_text_end: |
||||
nop |
||||
.popsection |
@ -0,0 +1,15 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" |
||||
CONFIG_ARM=y |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_DM=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_ATMEL=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_FSL_DSPI=y |
||||
CONFIG_FSL_QSPI=y |
||||
CONFIG_TARGET_LS1021AIOT=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" |
@ -0,0 +1,17 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1021AIOT=y |
||||
CONFIG_SPL=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" |
||||
CONFIG_CMD_DM=y |
||||
CONFIG_DM=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_ATMEL=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_FSL_DSPI=y |
||||
CONFIG_FSL_QSPI=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_SYS_NS16550=y |
@ -0,0 +1,367 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_LS102XA |
||||
|
||||
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
||||
|
||||
#define CONFIG_SYS_FSL_CLK |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) |
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE |
||||
|
||||
/* XHCI Support - enabled by default */ |
||||
#define CONFIG_HAS_FSL_XHCI_USB |
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB |
||||
#define CONFIG_USB_XHCI_FSL |
||||
#define CONFIG_USB_XHCI_DWC3 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
||||
#endif |
||||
|
||||
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_CMD_EXT2 |
||||
#endif |
||||
|
||||
/*
|
||||
* Generic Timer Definitions |
||||
*/ |
||||
#define GENERIC_TIMER_CLK 12500000 |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000 |
||||
#define CONFIG_DDR_CLK_FREQ 100000000 |
||||
|
||||
/*
|
||||
* DDR: 800 MHz ( 1600 MT/s data rate ) |
||||
*/ |
||||
|
||||
#define DDR_SDRAM_CFG 0x470c0008 |
||||
#define DDR_CS0_BNDS 0x008000bf |
||||
#define DDR_CS0_CONFIG 0x80014302 |
||||
#define DDR_TIMING_CFG_0 0x50550004 |
||||
#define DDR_TIMING_CFG_1 0xbcb38c56 |
||||
#define DDR_TIMING_CFG_2 0x0040d120 |
||||
#define DDR_TIMING_CFG_3 0x010e1000 |
||||
#define DDR_TIMING_CFG_4 0x00000001 |
||||
#define DDR_TIMING_CFG_5 0x03401400 |
||||
#define DDR_SDRAM_CFG_2 0x00401010 |
||||
#define DDR_SDRAM_MODE 0x00061c60 |
||||
#define DDR_SDRAM_MODE_2 0x00180000 |
||||
#define DDR_SDRAM_INTERVAL 0x18600618 |
||||
#define DDR_DDR_WRLVL_CNTL 0x8655f605 |
||||
#define DDR_DDR_WRLVL_CNTL_2 0x05060607 |
||||
#define DDR_DDR_WRLVL_CNTL_3 0x05050505 |
||||
#define DDR_DDR_CDR1 0x80040000 |
||||
#define DDR_DDR_CDR2 0x00000001 |
||||
#define DDR_SDRAM_CLK_CNTL 0x02000000 |
||||
#define DDR_DDR_ZQ_CNTL 0x89080600 |
||||
#define DDR_CS0_CONFIG_2 0 |
||||
#define DDR_SDRAM_CFG_MEM_EN 0x80000000 |
||||
#define SDRAM_CFG2_D_INIT 0x00000010 |
||||
#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 |
||||
#define SDRAM_CFG2_FRC_SR 0x80000000 |
||||
#define SDRAM_CFG_BI 0x00000001 |
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL |
||||
#define CONFIG_SYS_FSL_PBL_PBI \ |
||||
board/freescale/ls1021aiot/ls102xa_pbi.cfg |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SD_BOOT |
||||
#define CONFIG_SYS_FSL_PBL_RCW \ |
||||
board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_ENV_SUPPORT |
||||
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
||||
#define CONFIG_SPL_I2C_SUPPORT |
||||
#define CONFIG_SPL_WATCHDOG_SUPPORT |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_MMC_SUPPORT |
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 |
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 |
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10000000 |
||||
#define CONFIG_SPL_MAX_SIZE 0x1a000 |
||||
#define CONFIG_SPL_STACK 0x1001d000 |
||||
#define CONFIG_SPL_PAD_TO 0x1c000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x82000000 |
||||
|
||||
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
||||
CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
||||
#define CONFIG_SYS_MONITOR_LEN 0x80000 |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#endif |
||||
|
||||
#ifdef CONFIG_QSPI_BOOT |
||||
#define CONFIG_SYS_TEXT_BASE 0x40010000 |
||||
#endif |
||||
|
||||
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#endif |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
#define CONFIG_FSL_CAAM /* Enable CAAM */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock() |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
||||
|
||||
/* EEPROM */ |
||||
#define CONFIG_ID_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
||||
|
||||
/*
|
||||
* MMC |
||||
*/ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_GENERIC_MMC |
||||
|
||||
/* SATA */ |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
#define CONFIG_CMD_SCSI |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_SCSI_AHCI |
||||
#define CONFIG_SCSI_AHCI_PLAT |
||||
#ifndef PCI_DEVICE_ID_FREESCALE_AHCI |
||||
#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 |
||||
#endif |
||||
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ |
||||
PCI_DEVICE_ID_FREESCALE_AHCI} |
||||
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 |
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1 |
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
||||
CONFIG_SYS_SCSI_MAX_LUN) |
||||
|
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* SPI */ |
||||
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
|
||||
/* QSPI */ |
||||
#define QSPI0_AMBA_BASE 0x40000000 |
||||
#define FSL_QSPI_FLASH_SIZE (1 << 24) |
||||
#define FSL_QSPI_FLASH_NUM 2 |
||||
#define CONFIG_SPI_FLASH_BAR |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#endif |
||||
|
||||
/* DM SPI */ |
||||
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_DM_SPI_FLASH |
||||
#endif |
||||
|
||||
/*
|
||||
* eTSEC |
||||
*/ |
||||
#define CONFIG_TSEC_ENET |
||||
|
||||
#ifdef CONFIG_TSEC_ENET |
||||
#define CONFIG_MII |
||||
#define CONFIG_MII_DEFAULT_TSEC 1 |
||||
#define CONFIG_TSEC1 1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC1" |
||||
#define CONFIG_TSEC2 1 |
||||
#define CONFIG_TSEC2_NAME "eTSEC2" |
||||
|
||||
#define TSEC1_PHY_ADDR 1 |
||||
#define TSEC2_PHY_ADDR 3 |
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
|
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC2" |
||||
|
||||
#define CONFIG_PHY_GIGE |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_ATHEROS |
||||
|
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_HAS_ETH2 |
||||
#endif |
||||
|
||||
/* PCIe */ |
||||
#define CONFIG_PCI /* Enable PCI/PCIE */ |
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */ |
||||
#define CONFIG_PCIE2 /* PCIE controler 2 */ |
||||
|
||||
/* Use common FSL Layerscape PCIe code */ |
||||
#define CONFIG_PCIE_LAYERSCAPE |
||||
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" |
||||
|
||||
#define CONFIG_SYS_PCI_64BIT |
||||
|
||||
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 |
||||
#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ |
||||
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 |
||||
#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ |
||||
|
||||
#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 |
||||
#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 |
||||
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 |
||||
#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_PCI_SCAN_SHOW |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_MII |
||||
|
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) |
||||
#undef CONFIG_CMD_IMLS |
||||
#endif |
||||
|
||||
#define CONFIG_PEN_ADDR_BIG_ENDIAN |
||||
#define CONFIG_LAYERSCAPE_NS_ACCESS |
||||
#define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
||||
#define CONFIG_TIMER_CLK_FREQ 12500000 |
||||
|
||||
#define CONFIG_HWCONFIG |
||||
#define HWCONFIG_BUFFER_SIZE 256 |
||||
|
||||
#define CONFIG_FSL_DEVICE_DISABLE |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_high=0xffffffff\0" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE \ |
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_CMD_GREPENV |
||||
#define CONFIG_CMD_MEMINFO |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x82000000 |
||||
|
||||
#define CONFIG_LS102XA_STREAM_ID |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (30 * 1024) |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
||||
#else |
||||
/* start of monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_SD_BOOT) |
||||
#define CONFIG_ENV_OFFSET 0x100000 |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#elif defined(CONFIG_QSPI_BOOT) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_OFFSET 0x100000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#endif |
||||
|
||||
#define CONFIG_OF_BOARD_SETUP |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||
#define CONFIG_CMD_BOOTZ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/* Hash command with SHA acceleration supported in hardware */ |
||||
|
||||
#ifdef CONFIG_FSL_CAAM |
||||
|
||||
#define CONFIG_CMD_HASH |
||||
|
||||
#define CONFIG_SHA_HW_ACCEL |
||||
|
||||
#endif |
||||
|
||||
#include <asm/fsl_secure_boot.h> |
||||
|
||||
#endif |
Loading…
Reference in new issue