@ -114,11 +114,12 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
u16 data_ctl = 0 ;
u16 dma_cfg = 0 ;
int ret = 0 ;
unsigned long data_size = data - > blocksize * data - > blocks ;
/* Don't support write yet. */
if ( data - > flags & MMC_DATA_WRITE )
return UNUSABLE_ERR ;
data_ctl | = ( ( ffs ( data - > block size) - 1 ) < < 4 ) ;
data_ctl | = ( ( ffs ( data_ size ) - 1 ) < < 4 ) ;
data_ctl | = DTX_DIR ;
bfin_write_SDH_DATA_CTL ( data_ctl ) ;
dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN ;
@ -126,13 +127,13 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
bfin_write_SDH_DATA_TIMER ( - 1 ) ;
blackfin_dcache_flush_invalidate_range ( data - > dest ,
data - > dest + data - > block size) ;
data - > dest + data_ size ) ;
/* configure DMA */
bfin_write_DMA_START_ADDR ( data - > dest ) ;
bfin_write_DMA_X_COUNT ( data - > block size / 4 ) ;
bfin_write_DMA_X_COUNT ( data_ size / 4 ) ;
bfin_write_DMA_X_MODIFY ( 4 ) ;
bfin_write_DMA_CONFIG ( dma_cfg ) ;
bfin_write_SDH_DATA_LGTH ( data - > block size) ;
bfin_write_SDH_DATA_LGTH ( data_ size ) ;
/* kick off transfer */
bfin_write_SDH_DATA_CTL ( bfin_read_SDH_DATA_CTL ( ) | DTX_DMA_E | DTX_E ) ;