Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.master
parent
604364e42c
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230fe9b202
@ -0,0 +1,78 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* This file contains only support functions used also by the SoCFPGA |
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* platform code, the real meat is located in drivers/fpga/socfpga.c . |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/fpga_manager.h> |
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#include <asm/arch/reset_manager.h> |
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#include <asm/arch/system_manager.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Timeout count */ |
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#define FPGA_TIMEOUT_CNT 0x1000000 |
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static struct socfpga_fpga_manager *fpgamgr_regs = |
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(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
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/* Check whether FPGA Init_Done signal is high */ |
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static int is_fpgamgr_initdone_high(void) |
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{ |
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unsigned long val; |
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val = readl(&fpgamgr_regs->gpio_ext_porta); |
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return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK; |
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} |
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/* Get the FPGA mode */ |
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int fpgamgr_get_mode(void) |
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{ |
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unsigned long val; |
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val = readl(&fpgamgr_regs->stat); |
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return val & FPGAMGRREGS_STAT_MODE_MASK; |
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} |
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/* Check whether FPGA is ready to be accessed */ |
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int fpgamgr_test_fpga_ready(void) |
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{ |
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/* Check for init done signal */ |
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if (!is_fpgamgr_initdone_high()) |
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return 0; |
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/* Check again to avoid false glitches */ |
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if (!is_fpgamgr_initdone_high()) |
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return 0; |
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE) |
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return 0; |
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return 1; |
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} |
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/* Poll until FPGA is ready to be accessed or timeout occurred */ |
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int fpgamgr_poll_fpga_ready(void) |
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{ |
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unsigned long i; |
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/* If FPGA is blank, wait till WD invoke warm reset */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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/* check for init done signal */ |
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if (!is_fpgamgr_initdone_high()) |
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continue; |
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/* check again to avoid false glitches */ |
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if (!is_fpgamgr_initdone_high()) |
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continue; |
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return 1; |
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} |
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return 0; |
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} |
@ -0,0 +1,77 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef _FPGA_MANAGER_H_ |
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#define _FPGA_MANAGER_H_ |
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#include <altera.h> |
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struct socfpga_fpga_manager { |
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/* FPGA Manager Module */ |
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u32 stat; /* 0x00 */ |
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u32 ctrl; |
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u32 dclkcnt; |
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u32 dclkstat; |
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u32 gpo; /* 0x10 */ |
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u32 gpi; |
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u32 misci; /* 0x18 */ |
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u32 _pad_0x1c_0x82c[517]; |
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/* Configuration Monitor (MON) Registers */ |
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u32 gpio_inten; /* 0x830 */ |
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u32 gpio_intmask; |
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u32 gpio_inttype_level; |
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u32 gpio_int_polarity; |
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u32 gpio_intstatus; /* 0x840 */ |
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u32 gpio_raw_intstatus; |
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u32 _pad_0x848; |
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u32 gpio_porta_eoi; |
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u32 gpio_ext_porta; /* 0x850 */ |
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u32 _pad_0x854_0x85c[3]; |
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u32 gpio_1s_sync; /* 0x860 */ |
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u32 _pad_0x864_0x868[2]; |
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u32 gpio_ver_id_code; |
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u32 gpio_config_reg2; /* 0x870 */ |
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u32 gpio_config_reg1; |
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}; |
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#define FPGAMGRREGS_STAT_MODE_MASK 0x7 |
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#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 |
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#define FPGAMGRREGS_STAT_MSEL_LSB 3 |
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#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 |
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#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 |
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#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 |
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#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 |
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#define FPGAMGRREGS_CTRL_EN_MASK 0x1 |
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#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 |
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/* FPGA Mode */ |
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#define FPGAMGRREGS_MODE_FPGAOFF 0x0 |
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#define FPGAMGRREGS_MODE_RESETPHASE 0x1 |
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#define FPGAMGRREGS_MODE_CFGPHASE 0x2 |
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#define FPGAMGRREGS_MODE_INITPHASE 0x3 |
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#define FPGAMGRREGS_MODE_USERMODE 0x4 |
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#define FPGAMGRREGS_MODE_UNKNOWN 0x5 |
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/* FPGA CD Ratio Value */ |
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#define CDRATIO_x1 0x0 |
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#define CDRATIO_x2 0x1 |
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#define CDRATIO_x4 0x2 |
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#define CDRATIO_x8 0x3 |
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/* SoCFPGA support functions */ |
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int fpgamgr_test_fpga_ready(void); |
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int fpgamgr_poll_fpga_ready(void); |
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int fpgamgr_get_mode(void); |
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#endif /* _FPGA_MANAGER_H_ */ |
@ -0,0 +1,301 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/fpga_manager.h> |
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#include <asm/arch/reset_manager.h> |
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#include <asm/arch/system_manager.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Timeout count */ |
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#define FPGA_TIMEOUT_CNT 0x1000000 |
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static struct socfpga_fpga_manager *fpgamgr_regs = |
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(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
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static struct socfpga_system_manager *sysmgr_regs = |
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
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/* Set CD ratio */ |
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static void fpgamgr_set_cd_ratio(unsigned long ratio) |
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{ |
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clrsetbits_le32(&fpgamgr_regs->ctrl, |
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0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB, |
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(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); |
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} |
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static int fpgamgr_dclkcnt_set(unsigned long cnt) |
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{ |
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unsigned long i; |
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/* Clear any existing done status */ |
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if (readl(&fpgamgr_regs->dclkstat)) |
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writel(0x1, &fpgamgr_regs->dclkstat); |
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/* Write the dclkcnt */ |
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writel(cnt, &fpgamgr_regs->dclkcnt); |
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/* Wait till the dclkcnt done */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (!readl(&fpgamgr_regs->dclkstat)) |
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continue; |
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writel(0x1, &fpgamgr_regs->dclkstat); |
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return 0; |
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} |
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return -ETIMEDOUT; |
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} |
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/* Start the FPGA programming by initialize the FPGA Manager */ |
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static int fpgamgr_program_init(void) |
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{ |
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unsigned long msel, i; |
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/* Get the MSEL value */ |
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msel = readl(&fpgamgr_regs->stat); |
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msel &= FPGAMGRREGS_STAT_MSEL_MASK; |
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msel >>= FPGAMGRREGS_STAT_MSEL_LSB; |
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/*
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* Set the cfg width |
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* If MSEL[3] = 1, cfg width = 32 bit |
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*/ |
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if (msel & 0x8) { |
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setbits_le32(&fpgamgr_regs->ctrl, |
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FPGAMGRREGS_CTRL_CFGWDTH_MASK); |
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/* To determine the CD ratio */ |
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/* MSEL[1:0] = 0, CD Ratio = 1 */ |
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if ((msel & 0x3) == 0x0) |
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fpgamgr_set_cd_ratio(CDRATIO_x1); |
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/* MSEL[1:0] = 1, CD Ratio = 4 */ |
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else if ((msel & 0x3) == 0x1) |
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fpgamgr_set_cd_ratio(CDRATIO_x4); |
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/* MSEL[1:0] = 2, CD Ratio = 8 */ |
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else if ((msel & 0x3) == 0x2) |
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fpgamgr_set_cd_ratio(CDRATIO_x8); |
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} else { /* MSEL[3] = 0 */ |
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clrbits_le32(&fpgamgr_regs->ctrl, |
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FPGAMGRREGS_CTRL_CFGWDTH_MASK); |
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/* To determine the CD ratio */ |
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/* MSEL[1:0] = 0, CD Ratio = 1 */ |
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if ((msel & 0x3) == 0x0) |
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fpgamgr_set_cd_ratio(CDRATIO_x1); |
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/* MSEL[1:0] = 1, CD Ratio = 2 */ |
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else if ((msel & 0x3) == 0x1) |
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fpgamgr_set_cd_ratio(CDRATIO_x2); |
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/* MSEL[1:0] = 2, CD Ratio = 4 */ |
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else if ((msel & 0x3) == 0x2) |
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fpgamgr_set_cd_ratio(CDRATIO_x4); |
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} |
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/* To enable FPGA Manager configuration */ |
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); |
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/* To enable FPGA Manager drive over configuration line */ |
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); |
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/* Put FPGA into reset phase */ |
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); |
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/* (1) wait until FPGA enter reset phase */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE) |
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break; |
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} |
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/* If not in reset state, return error */ |
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) { |
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puts("FPGA: Could not reset\n"); |
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return -1; |
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} |
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/* Release FPGA from reset phase */ |
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); |
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/* (2) wait until FPGA enter configuration phase */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE) |
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break; |
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} |
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/* If not in configuration state, return error */ |
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) { |
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puts("FPGA: Could not configure\n"); |
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return -2; |
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} |
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/* Clear all interrupts in CB Monitor */ |
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writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi); |
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/* Enable AXI configuration */ |
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); |
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return 0; |
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} |
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/* Write the RBF data to FPGA Manager */ |
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static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) |
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{ |
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uint32_t src = (uint32_t)rbf_data; |
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uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS; |
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/* Number of loops for 32-byte long copying. */ |
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uint32_t loops32 = rbf_size / 32; |
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/* Number of loops for 4-byte long copying + trailing bytes */ |
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uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); |
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asm volatile( |
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"1: ldmia %0!, {r0-r7}\n" |
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" stmia %1!, {r0-r7}\n" |
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" sub %1, #32\n" |
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" subs %2, #1\n" |
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" bne 1b\n" |
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"2: ldr %2, [%0], #4\n" |
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" str %2, [%1]\n" |
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" subs %3, #1\n" |
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" bne 2b\n" |
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: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : |
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); |
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} |
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/* Ensure the FPGA entering config done */ |
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static int fpgamgr_program_poll_cd(void) |
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{ |
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const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | |
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FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; |
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unsigned long reg, i; |
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/* (3) wait until full config done */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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reg = readl(&fpgamgr_regs->gpio_ext_porta); |
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/* Config error */ |
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if (!(reg & mask)) { |
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printf("FPGA: Configuration error.\n"); |
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return -3; |
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} |
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/* Config done without error */ |
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if (reg & mask) |
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break; |
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} |
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/* Timeout happened, return error */ |
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if (i == FPGA_TIMEOUT_CNT) { |
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printf("FPGA: Timeout waiting for program.\n"); |
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return -4; |
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} |
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/* Disable AXI configuration */ |
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); |
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return 0; |
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} |
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/* Ensure the FPGA entering init phase */ |
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static int fpgamgr_program_poll_initphase(void) |
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{ |
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unsigned long i; |
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/* Additional clocks for the CB to enter initialization phase */ |
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if (fpgamgr_dclkcnt_set(0x4)) |
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return -5; |
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/* (4) wait until FPGA enter init phase or user mode */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) |
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break; |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) |
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break; |
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} |
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/* If not in configuration state, return error */ |
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if (i == FPGA_TIMEOUT_CNT) |
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return -6; |
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return 0; |
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} |
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/* Ensure the FPGA entering user mode */ |
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static int fpgamgr_program_poll_usermode(void) |
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{ |
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unsigned long i; |
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/* Additional clocks for the CB to exit initialization phase */ |
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if (fpgamgr_dclkcnt_set(0x5000)) |
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return -7; |
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/* (5) wait until FPGA enter user mode */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) |
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break; |
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} |
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/* If not in configuration state, return error */ |
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if (i == FPGA_TIMEOUT_CNT) |
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return -8; |
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/* To release FPGA Manager drive over configuration line */ |
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); |
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return 0; |
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} |
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/*
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* FPGA Manager to program the FPGA. This is the interface used by FPGA driver. |
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* Return 0 for sucess, non-zero for error. |
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*/ |
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int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) |
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{ |
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unsigned long status; |
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if ((uint32_t)rbf_data & 0x3) { |
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puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); |
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return -EINVAL; |
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} |
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/* Prior programming the FPGA, all bridges need to be shut off */ |
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/* Disable all signals from hps peripheral controller to fpga */ |
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writel(0, &sysmgr_regs->fpgaintfgrp_module); |
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/* Disable all signals from FPGA to HPS SDRAM */ |
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#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 |
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writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); |
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/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ |
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socfpga_bridges_reset(1); |
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/* Unmap the bridges from NIC-301 */ |
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writel(0x1, SOCFPGA_L3REGS_ADDRESS); |
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/* Initialize the FPGA Manager */ |
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status = fpgamgr_program_init(); |
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if (status) |
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return status; |
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/* Write the RBF data to FPGA Manager */ |
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fpgamgr_program_write(rbf_data, rbf_size); |
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/* Ensure the FPGA entering config done */ |
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status = fpgamgr_program_poll_cd(); |
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if (status) |
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return status; |
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/* Ensure the FPGA entering init phase */ |
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status = fpgamgr_program_poll_initphase(); |
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if (status) |
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return status; |
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/* Ensure the FPGA entering user mode */ |
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return fpgamgr_program_poll_usermode(); |
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} |
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