diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 72e7981..b9ebee1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -641,10 +641,12 @@ config TARGET_VEXPRESS64_JUNO
 config TARGET_LS2085A_EMU
 	bool "Support ls2085a_emu"
 	select ARM64
+	select ARMV8_MULTIENTRY
 
 config TARGET_LS2085A_SIMU
 	bool "Support ls2085a_simu"
 	select ARM64
+	select ARMV8_MULTIENTRY
 
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
@@ -757,6 +759,8 @@ source "arch/arm/cpu/armv7/zynq/Kconfig"
 
 source "arch/arm/cpu/armv7/Kconfig"
 
+source "arch/arm/cpu/armv8/Kconfig"
+
 source "board/aristainetos/Kconfig"
 source "board/BuR/kwb/Kconfig"
 source "board/BuR/tseries/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
new file mode 100644
index 0000000..4cd84b0
--- /dev/null
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -0,0 +1,6 @@
+if ARM64
+
+config ARMV8_MULTIENTRY
+        boolean "Enable multiple CPUs to enter into U-boot"
+
+endif
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4..df80a4e 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -77,6 +77,7 @@ reset:
 	/* Processor specific initialization */
 	bl	lowlevel_init
 
+#ifdef CONFIG_ARMV8_MULTIENTRY
 	branch_if_master x0, x1, master_cpu
 
 	/*
@@ -88,11 +89,10 @@ slave_cpu:
 	ldr	x0, [x1]
 	cbz	x0, slave_cpu
 	br	x0			/* branch to the given address */
-
-	/*
-	 * Master CPU
-	 */
 master_cpu:
+	/* On the master CPU */
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
 	bl	_main
 
 /*-----------------------------------------------------------------------*/
@@ -100,6 +100,15 @@ master_cpu:
 WEAK(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
+#ifndef CONFIG_ARMV8_MULTIENTRY
+	/*
+	 * For single-entry systems the lowlevel init is very simple.
+	 */
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+
+#else /* CONFIG_ARMV8_MULTIENTRY is set */
+
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 	branch_if_slave x0, 1f
 	ldr	x0, =GICD_BASE
@@ -137,6 +146,8 @@ WEAK(lowlevel_init)
 	bl	armv8_switch_to_el1
 #endif
 
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
 2:
 	mov	lr, x29			/* Restore LR */
 	ret
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1c8c425..3b3146a 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -78,6 +78,8 @@ lr	.req	x30
  * choose processor with all zero affinity value as the master.
  */
 .macro	branch_if_slave, xreg, slave_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+	/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
 	mrs	\xreg, mpidr_el1
 	tst	\xreg, #0xff		/* Test Affinity 0 */
 	b.ne	\slave_label
@@ -90,6 +92,7 @@ lr	.req	x30
 	lsr	\xreg, \xreg, #16
 	tst	\xreg, #0xff		/* Test Affinity 3 */
 	b.ne	\slave_label
+#endif
 .endm
 
 /*
@@ -97,12 +100,17 @@ lr	.req	x30
  * choose processor with all zero affinity value as the master.
  */
 .macro	branch_if_master, xreg1, xreg2, master_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+	/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
 	mrs	\xreg1, mpidr_el1
 	lsr	\xreg2, \xreg1, #32
 	lsl	\xreg1, \xreg1, #40
 	lsr	\xreg1, \xreg1, #40
 	orr	\xreg1, \xreg1, \xreg2
 	cbz	\xreg1, \master_label
+#else
+	b 	\master_label
+#endif
 .endm
 
 .macro armv8_switch_to_el2_m, xreg1
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 20db812..de62864 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -22,12 +22,6 @@ int board_init(void)
 
 int dram_init(void)
 {
-	/*
-	 * Clear spin table so that secondary processors
-	 * observe the correct value after waken up from wfe.
-	 */
-	*(unsigned long *)CPU_RELEASE_ADDR = 0;
-
 	gd->ram_size = PHYS_SDRAM_1_SIZE;
 	return 0;
 }
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index e6cd881..810eef1 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -54,13 +54,6 @@
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_LIBFDT
 
-/* SMP Spin Table Definitions */
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
-#define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x03f00000)
-#else
-#define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#endif
-
 /* CS register bases for the original memory map. */
 #define V2M_PA_CS0			0x00000000
 #define V2M_PA_CS1			0x14000000