- add new arch stm32mp for STM32 MPU/Soc based on Cortex A - support for stm32mp157 SOC - SPL is used as first boot stage loader - using driver model for all the drivers, even in SPL - all security feature are deactivated (ETZC and TZC) - reused STM32 MCU drivers when it is possible Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>master
Patrick Delaunay
6 years ago
committed by
Tom Rini
parent
35746c0138
commit
2514c2d0e6
@ -0,0 +1,41 @@ |
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if ARCH_STM32MP |
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|
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config SPL |
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select SPL_BOARD_INIT |
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select SPL_CLK |
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select SPL_DM |
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select SPL_DM_SEQ_ALIAS |
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select SPL_FRAMEWORK |
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select SPL_GPIO_SUPPORT |
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select SPL_LIBCOMMON_SUPPORT |
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select SPL_LIBGENERIC_SUPPORT |
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select SPL_OF_CONTROL |
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select SPL_OF_TRANSLATE |
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select SPL_PINCTRL |
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select SPL_REGMAP |
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select SPL_RESET_SUPPORT |
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select SPL_SERIAL_SUPPORT |
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select SPL_SYSCON |
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imply SPL_LIBDISK_SUPPORT |
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config SYS_SOC |
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default "stm32mp" |
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config TARGET_STM32MP1 |
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bool "Support stm32mp1xx" |
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select CPU_V7 |
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select PINCTRL_STM32 |
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select STM32_RESET |
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help |
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target STMicroelectronics SOC STM32MP1 family |
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STMicroelectronics MPU with core ARMv7 |
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config SYS_TEXT_BASE |
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prompt "U-Boot base address" |
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default 0xC0100000 |
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help |
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configure the U-Boot base address |
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when DDR driver is used: |
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DDR + 1MB (0xC0100000) |
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endif |
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@ -0,0 +1,10 @@ |
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#
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# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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#
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# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
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#
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obj-y += cpu.o
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obj-y += dram_init.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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@ -0,0 +1,14 @@ |
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#
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# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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#
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# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
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#
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ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32
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MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
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spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log |
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spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE |
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$(call if_changed,mkimage)
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@ -0,0 +1,139 @@ |
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause |
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*/ |
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#include <common.h> |
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#include <clk.h> |
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#include <asm/io.h> |
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#include <asm/arch/stm32.h> |
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|
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void enable_caches(void) |
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{ |
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/* Enable D-cache. I-cache is already enabled in start.S */ |
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dcache_enable(); |
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} |
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) |
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/**********************************************
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* Security init |
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*********************************************/ |
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#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) |
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#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) |
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#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) |
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#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) |
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#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) |
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#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) |
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#define PWR_CR1 (STM32_PWR_BASE + 0x00) |
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#define PWR_CR1_DBP BIT(8) |
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#define RCC_TZCR (STM32_RCC_BASE + 0x00) |
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#define RCC_BDCR (STM32_RCC_BASE + 0x0140) |
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#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) |
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#define RCC_BDCR_VSWRST BIT(31) |
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#define RCC_BDCR_RTCSRC GENMASK(17, 16) |
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static void security_init(void) |
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{ |
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/* Disable the backup domain write protection */ |
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/* the protection is enable at each reset by hardware */ |
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/* And must be disable by software */ |
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setbits_le32(PWR_CR1, PWR_CR1_DBP); |
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while (!(readl(PWR_CR1) & PWR_CR1_DBP)) |
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; |
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/* If RTC clock isn't enable so this is a cold boot then we need
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* to reset the backup domain |
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*/ |
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if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { |
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setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); |
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while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) |
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; |
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clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); |
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} |
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/* allow non secure access in Write/Read for all peripheral */ |
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writel(GENMASK(25, 0), ETZPC_DECPROT0); |
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/* Open SYSRAM for no secure access */ |
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writel(0x0, ETZPC_TZMA1_SIZE); |
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/* enable TZC1 TZC2 clock */ |
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writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); |
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/* Region 0 set to no access by default */ |
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/* bit 0 / 16 => nsaid0 read/write Enable
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* bit 1 / 17 => nsaid1 read/write Enable |
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* ... |
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* bit 15 / 31 => nsaid15 read/write Enable |
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*/ |
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writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); |
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/* bit 30 / 31 => Secure Global Enable : write/read */ |
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/* bit 0 / 1 => Region Enable for filter 0/1 */ |
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writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); |
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/* Enable Filter 0 and 1 */ |
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setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); |
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/* RCC trust zone deactivated */ |
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writel(0x0, RCC_TZCR); |
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/* TAMP: deactivate the internal tamper
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* Bit 23 ITAMP8E: monotonic counter overflow |
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* Bit 20 ITAMP5E: RTC calendar overflow |
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* Bit 19 ITAMP4E: HSE monitoring |
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* Bit 18 ITAMP3E: LSE monitoring |
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* Bit 16 ITAMP1E: RTC power domain supply monitoring |
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*/ |
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writel(0x0, TAMP_CR1); |
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} |
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/**********************************************
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* Debug init |
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*********************************************/ |
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#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) |
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#define RCC_DBGCFGR_DBGCKEN BIT(8) |
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#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) |
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#define DBGMCU_APB4FZ1_IWDG2 BIT(2) |
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static void dbgmcu_init(void) |
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{ |
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setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); |
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/* Freeze IWDG2 if Cortex-A7 is in debug mode */ |
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setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); |
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} |
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#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ |
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int arch_cpu_init(void) |
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{ |
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/* early armv7 timer init: needed for polling */ |
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timer_init(); |
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) |
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dbgmcu_init(); |
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security_init(); |
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#endif |
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return 0; |
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} |
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#if defined(CONFIG_DISPLAY_CPUINFO) |
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int print_cpuinfo(void) |
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{ |
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printf("CPU: STM32MP15x\n"); |
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return 0; |
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} |
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#endif /* CONFIG_DISPLAY_CPUINFO */ |
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void reset_cpu(ulong addr) |
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{ |
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} |
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@ -0,0 +1,34 @@ |
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <ram.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int dram_init(void) |
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{ |
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struct ram_info ram; |
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struct udevice *dev; |
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int ret; |
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ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
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if (ret) { |
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debug("RAM init failed: %d\n", ret); |
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return ret; |
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} |
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ret = ram_get_info(dev, &ram); |
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if (ret) { |
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debug("Cannot get RAM size: %d\n", ret); |
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return ret; |
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} |
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debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); |
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gd->ram_size = ram.size; |
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return 0; |
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} |
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@ -0,0 +1,115 @@ |
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/*
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* (C) Copyright 2016 |
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* Vikas Manocha, <vikas.manocha@st.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _STM32_GPIO_H_ |
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#define _STM32_GPIO_H_ |
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#include <asm/gpio.h> |
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enum stm32_gpio_port { |
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STM32_GPIO_PORT_A = 0, |
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STM32_GPIO_PORT_B, |
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STM32_GPIO_PORT_C, |
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STM32_GPIO_PORT_D, |
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STM32_GPIO_PORT_E, |
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STM32_GPIO_PORT_F, |
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STM32_GPIO_PORT_G, |
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STM32_GPIO_PORT_H, |
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STM32_GPIO_PORT_I |
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}; |
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enum stm32_gpio_pin { |
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STM32_GPIO_PIN_0 = 0, |
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STM32_GPIO_PIN_1, |
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STM32_GPIO_PIN_2, |
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STM32_GPIO_PIN_3, |
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STM32_GPIO_PIN_4, |
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STM32_GPIO_PIN_5, |
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STM32_GPIO_PIN_6, |
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STM32_GPIO_PIN_7, |
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STM32_GPIO_PIN_8, |
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STM32_GPIO_PIN_9, |
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STM32_GPIO_PIN_10, |
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STM32_GPIO_PIN_11, |
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STM32_GPIO_PIN_12, |
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STM32_GPIO_PIN_13, |
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STM32_GPIO_PIN_14, |
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STM32_GPIO_PIN_15 |
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}; |
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enum stm32_gpio_mode { |
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STM32_GPIO_MODE_IN = 0, |
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STM32_GPIO_MODE_OUT, |
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STM32_GPIO_MODE_AF, |
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STM32_GPIO_MODE_AN |
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}; |
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enum stm32_gpio_otype { |
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STM32_GPIO_OTYPE_PP = 0, |
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STM32_GPIO_OTYPE_OD |
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}; |
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enum stm32_gpio_speed { |
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STM32_GPIO_SPEED_2M = 0, |
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STM32_GPIO_SPEED_25M, |
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STM32_GPIO_SPEED_50M, |
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STM32_GPIO_SPEED_100M |
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}; |
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enum stm32_gpio_pupd { |
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STM32_GPIO_PUPD_NO = 0, |
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STM32_GPIO_PUPD_UP, |
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STM32_GPIO_PUPD_DOWN |
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}; |
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enum stm32_gpio_af { |
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STM32_GPIO_AF0 = 0, |
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STM32_GPIO_AF1, |
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STM32_GPIO_AF2, |
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STM32_GPIO_AF3, |
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STM32_GPIO_AF4, |
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STM32_GPIO_AF5, |
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STM32_GPIO_AF6, |
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STM32_GPIO_AF7, |
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STM32_GPIO_AF8, |
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STM32_GPIO_AF9, |
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STM32_GPIO_AF10, |
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STM32_GPIO_AF11, |
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STM32_GPIO_AF12, |
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STM32_GPIO_AF13, |
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STM32_GPIO_AF14, |
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STM32_GPIO_AF15 |
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}; |
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struct stm32_gpio_dsc { |
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enum stm32_gpio_port port; |
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enum stm32_gpio_pin pin; |
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}; |
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struct stm32_gpio_ctl { |
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enum stm32_gpio_mode mode; |
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enum stm32_gpio_otype otype; |
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enum stm32_gpio_speed speed; |
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enum stm32_gpio_pupd pupd; |
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enum stm32_gpio_af af; |
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}; |
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struct stm32_gpio_regs { |
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u32 moder; /* GPIO port mode */ |
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u32 otyper; /* GPIO port output type */ |
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u32 ospeedr; /* GPIO port output speed */ |
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u32 pupdr; /* GPIO port pull-up/pull-down */ |
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u32 idr; /* GPIO port input data */ |
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u32 odr; /* GPIO port output data */ |
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u32 bsrr; /* GPIO port bit set/reset */ |
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u32 lckr; /* GPIO port configuration lock */ |
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u32 afr[2]; /* GPIO alternate function */ |
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}; |
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struct stm32_gpio_priv { |
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struct stm32_gpio_regs *regs; |
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}; |
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#endif /* _STM32_GPIO_H_ */ |
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@ -0,0 +1,27 @@ |
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause |
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*/ |
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#ifndef _MACH_STM32_H_ |
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#define _MACH_STM32_H_ |
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/*
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* Peripheral memory map |
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* only address used before device tree parsing |
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*/ |
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#define STM32_RCC_BASE 0x50000000 |
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#define STM32_PWR_BASE 0x50001000 |
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#define STM32_DBGMCU_BASE 0x50081000 |
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#define STM32_TZC_BASE 0x5C006000 |
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#define STM32_ETZPC_BASE 0x5C007000 |
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#define STM32_TAMP_BASE 0x5C00A000 |
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#define STM32_SYSRAM_BASE 0x2FFC0000 |
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#define STM32_SYSRAM_SIZE SZ_256K |
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#define STM32_DDR_BASE 0xC0000000 |
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#define STM32_DDR_SIZE SZ_1G |
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#endif /* _MACH_STM32_H_ */ |
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@ -0,0 +1,60 @@ |
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <spl.h> |
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u32 spl_boot_device(void) |
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{ |
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return BOOT_DEVICE_MMC1; |
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} |
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u32 spl_boot_mode(const u32 boot_device) |
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{ |
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return MMCSD_MODE_RAW; |
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} |
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void board_init_f(ulong dummy) |
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{ |
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struct udevice *dev; |
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int ret; |
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arch_cpu_init(); |
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ret = spl_early_init(); |
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if (ret) { |
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debug("spl_early_init() failed: %d\n", ret); |
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hang(); |
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} |
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ret = uclass_get_device(UCLASS_CLK, 0, &dev); |
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if (ret) { |
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debug("Clock init failed: %d\n", ret); |
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return; |
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} |
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ret = uclass_get_device(UCLASS_RESET, 0, &dev); |
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if (ret) { |
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debug("Reset init failed: %d\n", ret); |
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return; |
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} |
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev); |
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if (ret) { |
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debug("%s: Cannot find pinctrl device\n", __func__); |
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return; |
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} |
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/* enable console uart printing */ |
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preloader_console_init(); |
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ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
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if (ret) { |
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debug("DRAM init failed: %d\n", ret); |
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return; |
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} |
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} |
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Reference in new issue