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stm32: Add SDRAM support for stm32f746 discovery board

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This patch adds SDRAM support for stm32f746 discovery board.
This patch depends on previous patch.
This patch is based on STM32F4 and emcraft's[1].

[1]:  https://github.com/EmcraftSystems/u-boot

Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
master
Toshifumi NISHINAGA 8 years ago committed by Tom Rini
parent ba0a3c16e0
commit 25c1b1353c
6 changed files with 357 additions and 14 deletions
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  1. 2
      arch/arm/cpu/armv7m/config.mk
  2. 75
      arch/arm/include/asm/arch-stm32f7/fmc.h
  3. 11
      arch/arm/include/asm/armv7m.h
  4. 49
      arch/arm/mach-stm32/stm32f7/soc.c
  5. 226
      board/st/stm32f746-disco/stm32f746-disco.c
  6. 8
      include/configs/stm32f746-disco.h

2
arch/arm/cpu/armv7m/config.mk
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@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -march=armv7-m -mthumb
PLATFORM_CPPFLAGS += -march=armv7-m -mthumb -mno-unaligned-access

75
arch/arm/include/asm/arch-stm32f7/fmc.h
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@ -0,0 +1,75 @@
/*
* (C) Copyright 2013
* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MACH_FMC_H_
#define _MACH_FMC_H_
struct stm32_fmc_regs {
u32 sdcr1; /* Control register 1 */
u32 sdcr2; /* Control register 2 */
u32 sdtr1; /* Timing register 1 */
u32 sdtr2; /* Timing register 2 */
u32 sdcmr; /* Mode register */
u32 sdrtr; /* Refresh timing register */
u32 sdsr; /* Status register */
};
/*
* FMC registers base
*/
#define STM32_SDRAM_FMC_BASE 0xA0000140
#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
/* Control register SDCR */
#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
/* Timings register SDTR */
#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
#define FMC_SDCMR_NRFS_SHIFT 5
#define FMC_SDCMR_MODE_NORMAL 0
#define FMC_SDCMR_MODE_START_CLOCK 1
#define FMC_SDCMR_MODE_PRECHARGE 2
#define FMC_SDCMR_MODE_AUTOREFRESH 3
#define FMC_SDCMR_MODE_WRITE_MODE 4
#define FMC_SDCMR_MODE_SELFREFRESH 5
#define FMC_SDCMR_MODE_POWERDOWN 6
#define FMC_SDCMR_BANK_1 (1 << 4)
#define FMC_SDCMR_BANK_2 (1 << 3)
#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
#define FMC_SDSR_BUSY (1 << 5)
#define FMC_BUSY_WAIT() do { \
__asm__ __volatile__ ("dsb" : : : "memory"); \
while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
; \
} while (0)
#endif /* _MACH_FMC_H_ */

11
arch/arm/include/asm/armv7m.h
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@ -51,10 +51,21 @@ struct v7m_mpu {
#define V7M_MPU_CTRL_ENABLE (1 << 0)
#define V7M_MPU_CTRL_HFNMIENA (1 << 1)
#define V7M_MPU_CTRL_ENABLE (1 << 0)
#define V7M_MPU_CTRL_DISABLE (0 << 0)
#define V7M_MPU_CTRL_HFNMIENA (1 << 1)
#define V7M_MPU_RASR_EN (1 << 0)
#define V7M_MPU_RASR_SIZE_BITS 1
#define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS)
#define V7M_MPU_RASR_SIZE_8MB (24 << V7M_MPU_RASR_SIZE_BITS)
#define V7M_MPU_RASR_TEX_SHIFT 19
#define V7M_MPU_RASR_S_SHIFT 18
#define V7M_MPU_RASR_C_SHIFT 17
#define V7M_MPU_RASR_B_SHIFT 16
#define V7M_MPU_RASR_AP_RW_RW (3 << 24)
#define V7M_MPU_RASR_XN_ENABLE (0 << 28)
#define V7M_MPU_RASR_XN_DISABLE (1 << 28)
#endif /* !defined(__ASSEMBLY__) */
#endif /* ARMV7M_H */

49
arch/arm/mach-stm32/stm32f7/soc.c
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@ -19,6 +19,55 @@ int arch_cpu_init(void)
{
configure_clocks();
/*
* Configure the memory protection unit (MPU)
* 0x00000000 - 0xffffffff: Strong-order, Shareable
* 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable
*/
/* Disable MPU */
writel(0, &V7M_MPU->ctrl);
writel(
0x00000000 /* address */
| 1 << 4 /* VALID */
| 0 << 0 /* REGION */
, &V7M_MPU->rbar
);
/* Strong-order, Shareable */
/* TEX=000, S=1, C=0, B=0*/
writel(
(V7M_MPU_RASR_XN_ENABLE
| V7M_MPU_RASR_AP_RW_RW
| 0x01 << V7M_MPU_RASR_S_SHIFT
| 0x00 << V7M_MPU_RASR_TEX_SHIFT
| V7M_MPU_RASR_SIZE_4GB
| V7M_MPU_RASR_EN)
, &V7M_MPU->rasr
);
writel(
0xC0000000 /* address */
| 1 << 4 /* VALID */
| 1 << 0 /* REGION */
, &V7M_MPU->rbar
);
/* Normal, Outer and inner Non-cacheable */
/* TEX=001, S=0, C=0, B=0*/
writel(
(V7M_MPU_RASR_XN_ENABLE
| V7M_MPU_RASR_AP_RW_RW
| 0x01 << V7M_MPU_RASR_TEX_SHIFT
| V7M_MPU_RASR_SIZE_8MB
| V7M_MPU_RASR_EN)
, &V7M_MPU->rasr
);
/* Enable MPU */
writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
return 0;
}

226
board/st/stm32f746-disco/stm32f746-disco.c
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@ -10,6 +10,8 @@
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rcc.h>
#include <asm/arch/fmc.h>
#include <dm/platdata.h>
#include <dm/platform_data/serial_stm32x7.h>
#include <asm/arch/stm32_periph.h>
@ -33,6 +35,221 @@ const struct stm32_gpio_ctl gpio_ctl_usart = {
.af = STM32_GPIO_AF7
};
const struct stm32_gpio_ctl gpio_ctl_fmc = {
.mode = STM32_GPIO_MODE_AF,
.otype = STM32_GPIO_OTYPE_PP,
.speed = STM32_GPIO_SPEED_100M,
.pupd = STM32_GPIO_PUPD_NO,
.af = STM32_GPIO_AF12
};
static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
/* Chip is LQFP144, see DM00077036.pdf for details */
{STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
{STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
{STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
{STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
{STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
{STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
{STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
{STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
{STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
{STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
{STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
{STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
{STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */
{STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
{STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
{STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */
{STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */
{STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
};
static int fmc_setup_gpio(void)
{
int rv = 0;
int i;
clock_setup(GPIO_B_CLOCK_CFG);
clock_setup(GPIO_C_CLOCK_CFG);
clock_setup(GPIO_D_CLOCK_CFG);
clock_setup(GPIO_E_CLOCK_CFG);
clock_setup(GPIO_F_CLOCK_CFG);
clock_setup(GPIO_G_CLOCK_CFG);
clock_setup(GPIO_H_CLOCK_CFG);
for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
&gpio_ctl_fmc);
if (rv)
goto out;
}
out:
return rv;
}
/*
* STM32 RCC FMC specific definitions
*/
#define RCC_ENR_FMC (1 << 0) /* FMC module clock */
static inline u32 _ns2clk(u32 ns, u32 freq)
{
u32 tmp = freq/1000000;
return (tmp * ns) / 1000;
}
#define NS2CLK(ns) (_ns2clk(ns, freq))
/*
* Following are timings for IS42S16400J, from corresponding datasheet
*/
#define SDRAM_CAS 3 /* 3 cycles */
#define SDRAM_NB 1 /* Number of banks */
#define SDRAM_MWID 1 /* 16 bit memory */
#define SDRAM_NR 0x1 /* 12-bit row */
#define SDRAM_NC 0x0 /* 8-bit col */
#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
#define SDRAM_TRRD NS2CLK(12)
#define SDRAM_TRCD NS2CLK(18)
#define SDRAM_TRP NS2CLK(18)
#define SDRAM_TRAS NS2CLK(42)
#define SDRAM_TRC NS2CLK(60)
#define SDRAM_TRFC NS2CLK(60)
#define SDRAM_TCDL (1 - 1)
#define SDRAM_TRDL NS2CLK(12)
#define SDRAM_TBDL (1 - 1)
#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
#define SDRAM_TCCD (1 - 1)
#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */
/* Last data in to row precharge, need also comply ineq on page 1648 */
#define SDRAM_TWR max(\
(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
)
#define SDRAM_MODE_BL_SHIFT 0
#define SDRAM_MODE_CAS_SHIFT 4
#define SDRAM_MODE_BL 0
#define SDRAM_MODE_CAS SDRAM_CAS
int dram_init(void)
{
u32 freq;
int rv;
rv = fmc_setup_gpio();
if (rv)
return rv;
setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC);
/*
* Get frequency for NS2CLK calculation.
*/
freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
writel(
CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
| SDRAM_NB << FMC_SDCR_NB_SHIFT
| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
| SDRAM_NR << FMC_SDCR_NR_SHIFT
| SDRAM_NC << FMC_SDCR_NC_SHIFT
| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
&STM32_SDRAM_FMC->sdcr1);
writel(
SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
&STM32_SDRAM_FMC->sdtr1);
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
&STM32_SDRAM_FMC->sdcmr);
udelay(200); /* 200 us delay, page 10, "Power-Up" */
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
&STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
&STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
&STM32_SDRAM_FMC->sdcmr);
FMC_BUSY_WAIT();
/* Refresh timer */
writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
/*
* Fill in global info with description of SRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
gd->ram_size = CONFIG_SYS_RAM_SIZE;
return rv;
}
static const struct stm32_gpio_dsc usart_gpio[] = {
{STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */
{STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */
@ -88,12 +305,3 @@ int board_init(void)
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
gd->ram_size = CONFIG_SYS_RAM_SIZE;
return 0;
}

8
include/configs/stm32f746-disco.h
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@ -24,13 +24,13 @@
* Configuration of the external SDRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_SIZE ((64 + 192) << 10)
#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024)
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
#define CONFIG_SYS_RAM_BASE 0x20000000
#define CONFIG_SYS_RAM_BASE 0xC0000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
#define CONFIG_SYS_LOAD_ADDR 0x20000000
#define CONFIG_LOADADDR 0x20000000
#define CONFIG_SYS_LOAD_ADDR 0xC0400000
#define CONFIG_LOADADDR 0xC0400000
#define CONFIG_SYS_MAX_FLASH_SECT 8
#define CONFIG_SYS_MAX_FLASH_BANKS 1

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