Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
master
Masahiro Yamada
11 years ago
committed by
Tom Rini
parent
ba8dd7755e
commit
26bf6d77a6
@ -1,87 +0,0 @@ |
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#
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# Copyright 2010-2011 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PAD_TO := 0xfff01000
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nandobj := $(objtree)/nand_spl/
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LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
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LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
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$(LDFLAGS) $(LDFLAGS_FINAL)
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asflags-y += -DCONFIG_NAND_SPL
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ccflags-y += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o
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COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
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nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
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OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(nandobj)board/$(BOARDDIR)
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targets += $(__OBJS)
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all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin |
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds |
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
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-Map $(nandobj)u-boot-spl.map -o $@
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$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) |
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$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
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-ansi -D__ASSEMBLY__ -P - <$< >$@
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# create symbolic links for common files
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$(obj)/cache.c: |
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@rm -f $@
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ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
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$(obj)/cpu_init_early.c: |
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@rm -f $@
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ln -sf $(srctree)/$(CPUDIR)/cpu_init_early.c $@
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$(obj)/spl_minimal.c: |
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@rm -f $@
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ln -sf $(srctree)/$(CPUDIR)/spl_minimal.c $@
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$(obj)/fsl_law.c: |
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@rm -f $@
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ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
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$(obj)/law.c: |
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@rm -f $@
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ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
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$(obj)/nand_boot_fsl_elbc.c: |
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@rm -f $@
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ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
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$(obj)/ns16550.c: |
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@rm -f $@
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ln -sf $(srctree)/drivers/serial/ns16550.c $@
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$(obj)/resetvec.S: |
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@rm -f $@
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ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
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$(obj)/start.S: |
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@rm -f $@
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ln -sf $(srctree)/$(CPUDIR)/start.S $@
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$(obj)/tlb.c: |
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@rm -f $@
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ln -sf $(srctree)/$(CPUDIR)/tlb.c $@
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$(obj)/tlb_table.c: |
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@rm -f $@
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ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
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@ -1,96 +0,0 @@ |
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc. |
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* Author: Roy Zang <tie-fei.zang@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <ns16550.h> |
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#include <asm/io.h> |
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#include <nand.h> |
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#include <asm/fsl_law.h> |
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#include <fsl_ddr_sdram.h> |
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#include <asm/global_data.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Fixed sdram init -- doesn't use serial presence detect. */ |
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void sdram_init(void) |
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{ |
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struct ccsr_ddr __iomem *ddr = |
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(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; |
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set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); |
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); |
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); |
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__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); |
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__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); |
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__raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2); |
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__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); |
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__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); |
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__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); |
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); |
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); |
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__raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl); |
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl); |
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__raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1); |
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__raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2); |
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/* Set, but do not enable the memory */ |
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__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); |
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asm volatile("sync;isync"); |
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udelay(500); |
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/* Let the controller go */ |
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out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); |
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} |
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void board_init_f(ulong bootflag) |
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{ |
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u32 plat_ratio; |
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
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/* initialize selected port with appropriate baud rate */ |
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
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plat_ratio >>= 1; |
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
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gd->bus_clk / 16 / CONFIG_BAUDRATE); |
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puts("\nNAND boot... "); |
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/* Initialize the DDR3 */ |
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sdram_init(); |
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/* copy code to RAM and jump to it - this should not return */ |
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read. |
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*/ |
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, |
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CONFIG_SYS_NAND_U_BOOT_RELOC); |
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} |
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void board_init_r(gd_t *gd, ulong dest_addr) |
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{ |
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nand_boot(); |
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} |
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void putc(char c) |
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{ |
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if (c == '\n') |
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); |
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); |
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} |
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void puts(const char *str) |
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{ |
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while (*str) |
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putc(*str++); |
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} |
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