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@ -201,10 +201,9 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) |
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/*
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* Stop I2C transaction |
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*/ |
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void i2c_imx_stop(void) |
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static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) |
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{ |
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int ret; |
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; |
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unsigned int temp = readb(&i2c_regs->i2cr); |
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temp &= ~(I2CR_MSTA | I2CR_MTX); |
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@ -271,7 +270,7 @@ static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, |
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ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); |
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if (ret >= 0) |
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return 0; |
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i2c_imx_stop(); |
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i2c_imx_stop(i2c_regs); |
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if (ret == -ENODEV) |
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return ret; |
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@ -305,7 +304,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) |
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ret = tx_byte(i2c_regs, (chip << 1) | 1); |
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if (ret < 0) { |
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i2c_imx_stop(); |
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i2c_imx_stop(i2c_regs); |
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return ret; |
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} |
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@ -322,7 +321,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) |
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for (i = 0; i < len; i++) { |
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ret = wait_for_sr_state(i2c_regs, ST_IIF); |
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if (ret < 0) { |
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i2c_imx_stop(); |
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i2c_imx_stop(i2c_regs); |
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return ret; |
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} |
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@ -331,7 +330,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) |
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* controller from generating another clock cycle |
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*/ |
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if (i == (len - 1)) { |
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i2c_imx_stop(); |
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i2c_imx_stop(i2c_regs); |
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} else if (i == (len - 2)) { |
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temp = readb(&i2c_regs->i2cr); |
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temp |= I2CR_TX_NO_AK; |
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@ -340,9 +339,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) |
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writeb(0, &i2c_regs->i2sr); |
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buf[i] = readb(&i2c_regs->i2dr); |
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} |
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i2c_imx_stop(); |
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i2c_imx_stop(i2c_regs); |
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return 0; |
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} |
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@ -364,9 +361,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) |
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if (ret < 0) |
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break; |
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} |
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i2c_imx_stop(); |
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i2c_imx_stop(i2c_regs); |
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return ret; |
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} |
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